From 26d26f77a6960600da70dbddc81beb294f59a88a Mon Sep 17 00:00:00 2001
From: Emily <vcs@emily.moe>
Date: Fri, 27 Sep 2019 15:06:42 +0100
Subject: [PATCH] yosys: enable tests

---
 pkgs/development/compilers/yosys/default.nix | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/pkgs/development/compilers/yosys/default.nix b/pkgs/development/compilers/yosys/default.nix
index 47c3259099cb..79c8f67b9e06 100644
--- a/pkgs/development/compilers/yosys/default.nix
+++ b/pkgs/development/compilers/yosys/default.nix
@@ -2,6 +2,7 @@
 , pkgconfig, bison, flex
 , tcl, readline, libffi, python3
 , protobuf, zlib
+, verilog
 }:
 
 with builtins;
@@ -49,6 +50,7 @@ stdenv.mkDerivation rec {
       --replace 'LD = gcc' 'LD = $(CXX)' \
       --replace 'ABCMKARGS = CC="$(CXX)" CXX="$(CXX)"' 'ABCMKARGS =' \
       --replace 'echo UNKNOWN' 'echo ${substring 0 10 (elemAt srcs 0).rev}'
+    patchShebangs tests
   '';
 
   preBuild = ''
@@ -62,6 +64,13 @@ stdenv.mkDerivation rec {
     (cd misc && ${protobuf}/bin/protoc --cpp_out ../backends/protobuf/ ./yosys.proto)
   '';
 
+  doCheck = true;
+  checkInputs = [ verilog ];
+  # checkPhase defaults to VERBOSE=y, which gets passed down to abc,
+  # which then does $(VERBOSE)gcc, which then complains about not
+  # being able to find ygcc. Life is pain.
+  checkFlags = [ " " ];
+
   meta = {
     description = "Framework for RTL synthesis tools";
     longDescription = ''