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lib/systems/architectures: add sapphirerapids/emeraldrapids

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For reference: https://en.wikichip.org/wiki/intel/microarchitectures/sapphire_rapids

https://www.phoronix.com/news/GCC-13-Initial-Emerald-Rapids
https://www.phoronix.com/news/LLVM-Adds-Intel-Emerald-Rapids
This commit is contained in:
Jörg Thalheim 2024-10-07 12:54:21 +02:00 • committed by Alyssa Ross
parent d74f0ecb14
commit 8885a1e21a
2 changed files with 8 additions and 0 deletions
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4
lib/systems/architectures.nix
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@ -26,6 +26,8 @@ rec {
cooperlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
tigerlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
alderlake = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "fma" ];
sapphirerapids = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
emeraldrapids = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" "avx2" "avx512" "fma" ];
# x86_64 AMD
btver1 = [ "sse3" "ssse3" "sse4_1" "sse4_2" ];
btver2 = [ "sse3" "ssse3" "sse4_1" "sse4_2" "aes" "avx" ];
@ -73,6 +75,8 @@ rec {
cascadelake = [ "cannonlake" ] ++ inferiors.cannonlake;
cooperlake = [ "cascadelake" ] ++ inferiors.cascadelake;
tigerlake = [ "icelake-server" ] ++ inferiors.icelake-server;
sapphirerapids = [ "tigerlake" ] ++ inferiors.tigerlake;
emeraldrapids = [ "sapphirerapids" ] ++ inferiors.sapphirerapids;
# CX16 does not exist on alderlake, while it does on nearly all other intel CPUs
alderlake = [ ];