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61f0a17d3c
The iverilog project is commonly known as ... iverilog, not verilog. The package name `verilog` so far has been confusing, rename to `iverilog`. While doing so, move the package to the new by-name/ convention directory. Fix all the fall-out of packages that referred to the old name.
49 lines
1 KiB
Nix
49 lines
1 KiB
Nix
{
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lib,
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buildPythonPackage,
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fetchPypi,
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pythonOlder,
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jinja2,
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ply,
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iverilog,
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pytestCheckHook,
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}:
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buildPythonPackage rec {
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pname = "pyverilog";
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version = "1.3.0";
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format = "setuptools";
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src = fetchPypi {
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inherit pname version;
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sha256 = "1a74k8r21swmfwvgv4c014y6nbcyl229fspxw89ygsgb0j83xnar";
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};
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disabled = pythonOlder "3.7";
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patchPhase = ''
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# The path to Icarus can still be overridden via an environment variable at runtime.
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substituteInPlace pyverilog/vparser/preprocessor.py \
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--replace "iverilog = 'iverilog'" "iverilog = '${iverilog}/bin/iverilog'"
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'';
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propagatedBuildInputs = [
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jinja2
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ply
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iverilog
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];
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preCheck = ''
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substituteInPlace pytest.ini \
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--replace "python_paths" "pythonpath"
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'';
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nativeCheckInputs = [ pytestCheckHook ];
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meta = with lib; {
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homepage = "https://github.com/PyHDI/Pyverilog";
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description = "Python-based Hardware Design Processing Toolkit for Verilog HDL";
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license = licenses.asl20;
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maintainers = with maintainers; [ trepetti ];
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};
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}
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