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Revert "Сделал отдельную ветку для работы с urdf"

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This reverts commit e26579ae8e.
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Igor Brylyov 2022-09-01 11:43:24 +03:00
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Ветка для работы с пакетом urdf
![roboarm_diy_version](img/robossembler-arm.png)
Сделаны папки для версии манипулятора с захватом и без него
# Робот-манипулятор Robossembler
Доступный открытый промышленный робот-манипулятор с 6-ю степенями свободы, адаптированный для автоматической сборки. Все детали, кроме электрических плат и компонентов, магнитопровода, постоянных магнитов и катушек индуктивности, могут быть изготовлены с помощью технологии трёхмерной печати.
## Ключевые особенности
* **Open Source**
* Все разработанные 3D-модели, исходные коды программ, электрические схемы открыты и доступны для копирования и модификации
* Все файлы созданы с помощью свободных программ (KiCAD, Blender) или публикуются в открытых форматах (STEP)
* **Векторное управление серводвигателями**
* Энергоэффективность
* Простота охлаждения
* **Универсальный симметричный стыковочный механизм**
* Гибкость, модульность
* Возможность перемещения робота в другие посадочные места
* **Управление звеньям робота на уровне Realtime-протокола DDS**
* ROS2 совместимость по умолчанию на уровне звеньев
* Полное отсутствие проприетарных протоколов
* **Сборочно-ориентированный дизайн с печатными деталями без единого болта**
* Быстрая сборка робота вручную без использования специальных инструментов
* Возможность полной автоматизации сборки
* **Интеграция с сетью Robonomics**
* Безопасность в удалённом управлении роботом и обновлении ПО
* Инструменты эффективного федеративного обучения роботов, формирования базы мета-навыков и предсказаний сбоев
## Компоненты
| Опорное звено | Вилка | Соединительное звено | Конечное звено |
|------|-------|------|-------|
| ![](img/base-link.png) | ![](img/fork.png) | ![](img/link.png) | ![](img/end-effector-link.png) |
## Основные характеристики
| Характеристика | Значение |
|------|-------|
| Число степеней свободы (Degrees of Freedom) | 6 DoF |
| Диапазоны движения звеньев (Motion Range) | A – 360”, B – 270”, C – 360”, D – 270”, E – 360”, F – 270” |
| Максимальная скорость (Max speed), град/с | 30 |
| Повторяемость (Pose Repeatability), мм | 0.1 |
| Момент силы (Rated torque), Н*м | 78 |
| Максимальная нагрузка (Max payload), кг | 2 |
| Максимальная потребляемая мощность (Max Consumption Power), Вт | 150 |
| Производимый шум (Acoustic noise level), dB | 65 |
| Влагозащищенность (water-proof) | IP65 |
| Вес (Weight), кг | 4,79 (конечное звено 0,63, соединительная вилка 1,68, соединительное звено 1,58, опорное звено 0,9) |
| Высота (Height), мм | 900 |
| Дальность (Reach), мм | 600 |
| Размер места для монтажа (Footprint), мм | 200х200 |
| Масштабирование/модульность | может быть собран в конфигурациях с кратным двум количеством степеней свободы - 2,4,6,8 |
| Robotics framework | ROS2 |
| Интерфейсы (Communication Interfaces) | RS485 |
| Безопасность (Security) | Robonomics Network & ROS2 Security |
| Автоматическое обновление ПО (Automatic updates) | Robonomics Network |
## Приспособления
Приспособления монтируются к конечному звену манипулятора через стыковочный интерфейс. На данный момент наиболее проработан [Механический захват](https://gitlab.com/robosphere/arm-tools/grip-tool).
## Обзор директорий и файлов
* **brd** - исходные файлы печатных плат в формате [KiCAD](https://www.kicad.org/)
* **calc** - расчёты механических узлов манипулятора
* **img** - изображения моделей, включая предыдущие версии
* **src** - исходные файлы деталей конструкции в формате Solidworks. Со временем будут переведены во FreeCAD. Сейчас же доступна STEP-сборка (arm_assembly) в корне репозитория
* **BOM_price_spec.xls** - закупочная ведомость
* **assembly.xls** - карта сборки
## Степень готовности
* Механическая конструкция разработана и в настоящий момент прототипируется
* Схемотехника готова, трассировка печатных плат в разработке
* Встроенное программное обеспечение в разработке. Мы планируем использовать и дорабатывать открытые библиотеки [SimpleFOC](https://github.com/simplefoc/Arduino-FOC), [microROS](https://micro.ros.org/)
* Программное обеспечение ROS2 в разработке - см. репозиторий [robossembler-ros2](https://gitlab.com/robosphere/robossembler-ros2)
## FAQ
* **Зачем печатать мотор, если можно просто купить недорого в Китае?**
- В самом начале мы рассматривали китайские моторы для позиционирования камер GM6208, но потом отказались от них по ряду причин: они относительно дорогостоящие(а для манипулятора их нужно много), не подходят для автоматической сборки и монтажа(нет мест для позиционирования механического захвата).
* **Какие компоненты не печатаются?**
- Не печатаются магниты, платы и компоненты, контакты, подшипники, катушки, магнитопровод (М3 болт).
* **Почему Вы заявляете, что open source, а исходники в Solidworks?**
- Полный перевод исходных файлов проекта будет осуществляться по мере испытаний прототипа и выпуска alpha-версии манипулятора. Чтобы ознакомиться с исходными моделями, можно открыть STEP-файл сборки. Например, с помощью свободных программ [FreeCAD](https://www.freecadweb.org/), [Mayo](https://github.com/fougue/mayo) или [Analysis situs](http://quaoar.su/blog/page/analysis-situs)
* **Почему не применили open source контроллеры моторов - ODrive, MIT Cheetah?**
- При всём уважении к указанным проектам, платы их контроллеров не подходят к нашей конструкции манипулятора. Также мы старались разработать контроллер из максимально дешёвых и доступных компонентов.
## Участие в проекте
Будем рады принять помощь в любом виде: проектирование, критика, предложения, обнаруженные ошибки. Не стесняйтесь, [создавайте issues](https://gitlab.com/robosphere/roboarm-diy-version/-/issues/new).
Подписывайтесь на наши медийные ресурсы! Там публикуются результаты проекта и другая информация по теме Open Source промышленной робототехники.
* Youtube-канал [Robosphere](https://www.youtube.com/channel/UC32Xgbsw9XQlN1QH59pe8HA)
* Telegram-канал [@robossembler_ru](https://t.me/robossembler_ru)
## Спонсоры
[![](img/robonomics_logo.png)](https://robonomics.network/)

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F 0 "#PWR?" H 6100 4250 50 0001 C CNN
F 1 "GND" H 6105 4327 50 0000 C CNN
F 2 "" H 6100 4500 50 0001 C CNN
F 3 "" H 6100 4500 50 0001 C CNN
1 6100 4500
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5B73DD
P 6600 4500
F 0 "#PWR?" H 6600 4250 50 0001 C CNN
F 1 "GND" H 6605 4327 50 0000 C CNN
F 2 "" H 6600 4500 50 0001 C CNN
F 3 "" H 6600 4500 50 0001 C CNN
1 6600 4500
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5B7677
P 8050 4400
F 0 "#PWR?" H 8050 4150 50 0001 C CNN
F 1 "GND" H 8055 4227 50 0000 C CNN
F 2 "" H 8050 4400 50 0001 C CNN
F 3 "" H 8050 4400 50 0001 C CNN
1 8050 4400
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5B7E36
P 8550 4400
F 0 "#PWR?" H 8550 4150 50 0001 C CNN
F 1 "GND" H 8555 4227 50 0000 C CNN
F 2 "" H 8550 4400 50 0001 C CNN
F 3 "" H 8550 4400 50 0001 C CNN
1 8550 4400
1 0 0 -1
$EndComp
$Comp
L Device:CP C?
U 1 1 6E5C4915
P 2650 2750
F 0 "C?" H 2768 2796 50 0000 L CNN
F 1 "270uF" H 2768 2705 50 0000 L CNN
F 2 "Capacitor_THT:CP_Radial_D10.0mm_P5.00mm" H 2688 2600 50 0001 C CNN
F 3 "~" H 2650 2750 50 0001 C CNN
1 2650 2750
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5C5160
P 2650 2600
F 0 "#PWR?" H 2650 2450 50 0001 C CNN
F 1 "+24V" H 2665 2773 50 0000 C CNN
F 2 "" H 2650 2600 50 0001 C CNN
F 3 "" H 2650 2600 50 0001 C CNN
1 2650 2600
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5C557B
P 2650 2900
F 0 "#PWR?" H 2650 2650 50 0001 C CNN
F 1 "GND" H 2655 2727 50 0000 C CNN
F 2 "" H 2650 2900 50 0001 C CNN
F 3 "" H 2650 2900 50 0001 C CNN
1 2650 2900
1 0 0 -1
$EndComp
$Comp
L Device:CP C?
U 1 1 6E5C5BF2
P 3100 2750
F 0 "C?" H 3218 2796 50 0000 L CNN
F 1 "270uF" H 3218 2705 50 0000 L CNN
F 2 "Capacitor_THT:CP_Radial_D10.0mm_P5.00mm" H 3138 2600 50 0001 C CNN
F 3 "~" H 3100 2750 50 0001 C CNN
1 3100 2750
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5C5BF8
P 3100 2600
F 0 "#PWR?" H 3100 2450 50 0001 C CNN
F 1 "+24V" H 3115 2773 50 0000 C CNN
F 2 "" H 3100 2600 50 0001 C CNN
F 3 "" H 3100 2600 50 0001 C CNN
1 3100 2600
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5C5BFE
P 3100 2900
F 0 "#PWR?" H 3100 2650 50 0001 C CNN
F 1 "GND" H 3105 2727 50 0000 C CNN
F 2 "" H 3100 2900 50 0001 C CNN
F 3 "" H 3100 2900 50 0001 C CNN
1 3100 2900
1 0 0 -1
$EndComp
$Comp
L Device:CP C?
U 1 1 6E5C769E
P 7100 2800
F 0 "C?" H 7218 2846 50 0000 L CNN
F 1 "270uF" H 7218 2755 50 0000 L CNN
F 2 "Capacitor_THT:CP_Radial_D10.0mm_P5.00mm" H 7138 2650 50 0001 C CNN
F 3 "~" H 7100 2800 50 0001 C CNN
1 7100 2800
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5C76A4
P 7100 2650
F 0 "#PWR?" H 7100 2500 50 0001 C CNN
F 1 "+24V" H 7115 2823 50 0000 C CNN
F 2 "" H 7100 2650 50 0001 C CNN
F 3 "" H 7100 2650 50 0001 C CNN
1 7100 2650
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5C76AA
P 7100 2950
F 0 "#PWR?" H 7100 2700 50 0001 C CNN
F 1 "GND" H 7105 2777 50 0000 C CNN
F 2 "" H 7100 2950 50 0001 C CNN
F 3 "" H 7100 2950 50 0001 C CNN
1 7100 2950
1 0 0 -1
$EndComp
$Comp
L Device:CP C?
U 1 1 6E5C923D
P 7450 2800
F 0 "C?" H 7568 2846 50 0000 L CNN
F 1 "270uF" H 7568 2755 50 0000 L CNN
F 2 "Capacitor_THT:CP_Radial_D10.0mm_P5.00mm" H 7488 2650 50 0001 C CNN
F 3 "~" H 7450 2800 50 0001 C CNN
1 7450 2800
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5C9243
P 7450 2650
F 0 "#PWR?" H 7450 2500 50 0001 C CNN
F 1 "+24V" H 7465 2823 50 0000 C CNN
F 2 "" H 7450 2650 50 0001 C CNN
F 3 "" H 7450 2650 50 0001 C CNN
1 7450 2650
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5C9249
P 7450 2950
F 0 "#PWR?" H 7450 2700 50 0001 C CNN
F 1 "GND" H 7455 2777 50 0000 C CNN
F 2 "" H 7450 2950 50 0001 C CNN
F 3 "" H 7450 2950 50 0001 C CNN
1 7450 2950
1 0 0 -1
$EndComp
$Comp
L Connector_Generic:Conn_02x08_Odd_Even J?
U 1 1 62A239EC
P 3700 3850
F 0 "J?" H 3750 4367 50 0000 C CNN
F 1 "Conn_02x08_Odd_Even" H 3750 4276 50 0000 C CNN
F 2 "" H 3700 3850 50 0001 C CNN
F 3 "~" H 3700 3850 50 0001 C CNN
1 3700 3850
1 0 0 -1
$EndComp
Wire Wire Line
3500 3200 3500 3550
Wire Wire Line
4000 3200 4000 3550
Wire Wire Line
6100 3200 6100 3550
Wire Wire Line
6600 3200 6600 3550
Wire Wire Line
3500 3650 3500 3750
Wire Wire Line
3500 4250 3500 4500
Wire Wire Line
4000 4250 4000 4500
Wire Wire Line
4000 3650 4000 3750
Wire Wire Line
4000 3650 4000 3550
Connection ~ 4000 3650
Connection ~ 4000 3550
Wire Wire Line
3500 3650 3500 3550
Connection ~ 3500 3650
Connection ~ 3500 3550
Connection ~ 3500 4250
Wire Wire Line
3500 4050 3500 4150
Connection ~ 3500 4150
Wire Wire Line
3500 4150 3500 4250
Connection ~ 4000 4250
Wire Wire Line
4000 4050 4000 4150
Connection ~ 4000 4150
Wire Wire Line
4000 4150 4000 4250
$Comp
L Connector_Generic:Conn_02x08_Odd_Even J?
U 1 1 62A2BA86
P 6300 3850
F 0 "J?" H 6350 4367 50 0000 C CNN
F 1 "Conn_02x08_Odd_Even" H 6350 4276 50 0000 C CNN
F 2 "" H 6300 3850 50 0001 C CNN
F 3 "~" H 6300 3850 50 0001 C CNN
1 6300 3850
1 0 0 -1
$EndComp
Wire Wire Line
6100 3650 6100 3750
Wire Wire Line
6100 4250 6100 4500
Wire Wire Line
6600 4250 6600 4500
Wire Wire Line
6600 3650 6600 3750
Wire Wire Line
6100 3650 6100 3550
Connection ~ 6100 3650
Connection ~ 6100 3550
Wire Wire Line
6600 3650 6600 3550
Connection ~ 6600 3650
Connection ~ 6600 3550
Wire Wire Line
6100 4250 6100 4150
Connection ~ 6100 4250
Connection ~ 6100 4150
Wire Wire Line
6100 4150 6100 4050
Wire Wire Line
6600 4250 6600 4150
Connection ~ 6600 4250
Connection ~ 6600 4150
Wire Wire Line
6600 4150 6600 4050
$Comp
L Device:LED D?
U 1 1 62A331FE
P 3000 4300
F 0 "D?" V 3039 4182 50 0000 R CNN
F 1 "LED" V 2948 4182 50 0000 R CNN
F 2 "" H 3000 4300 50 0001 C CNN
F 3 "~" H 3000 4300 50 0001 C CNN
1 3000 4300
0 -1 -1 0
$EndComp
$Comp
L Device:LED D?
U 1 1 62A33CB9
P 4400 4300
F 0 "D?" V 4439 4182 50 0000 R CNN
F 1 "LED" V 4348 4182 50 0000 R CNN
F 2 "" H 4400 4300 50 0001 C CNN
F 3 "~" H 4400 4300 50 0001 C CNN
1 4400 4300
0 -1 -1 0
$EndComp
Wire Wire Line
4000 3950 4400 3950
Wire Wire Line
4400 3950 4400 4150
Wire Wire Line
3500 3950 3000 3950
Wire Wire Line
3000 3950 3000 4150
$Comp
L power:GND #PWR?
U 1 1 62A37B88
P 3000 4500
F 0 "#PWR?" H 3000 4250 50 0001 C CNN
F 1 "GND" H 3005 4327 50 0000 C CNN
F 2 "" H 3000 4500 50 0001 C CNN
F 3 "" H 3000 4500 50 0001 C CNN
1 3000 4500
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 62A37E78
P 4400 4500
F 0 "#PWR?" H 4400 4250 50 0001 C CNN
F 1 "GND" H 4405 4327 50 0000 C CNN
F 2 "" H 4400 4500 50 0001 C CNN
F 3 "" H 4400 4500 50 0001 C CNN
1 4400 4500
1 0 0 -1
$EndComp
Wire Wire Line
3000 4500 3000 4450
Wire Wire Line
4400 4500 4400 4450
Wire Wire Line
3500 3800 6100 3800
Connection ~ 6100 3800
Wire Wire Line
4000 3900 6600 3900
Connection ~ 6600 3900
$Comp
L Device:LED D?
U 1 1 62A31AD3
P 5600 4300
F 0 "D?" V 5639 4182 50 0000 R CNN
F 1 "LED" V 5548 4182 50 0000 R CNN
F 2 "" H 5600 4300 50 0001 C CNN
F 3 "~" H 5600 4300 50 0001 C CNN
1 5600 4300
0 -1 -1 0
$EndComp
Wire Wire Line
5600 3950 5600 4150
$Comp
L power:GND #PWR?
U 1 1 62A31ADA
P 5600 4500
F 0 "#PWR?" H 5600 4250 50 0001 C CNN
F 1 "GND" H 5605 4327 50 0000 C CNN
F 2 "" H 5600 4500 50 0001 C CNN
F 3 "" H 5600 4500 50 0001 C CNN
1 5600 4500
1 0 0 -1
$EndComp
Wire Wire Line
5600 4500 5600 4450
$Comp
L Device:LED D?
U 1 1 62A3477C
P 6850 4300
F 0 "D?" V 6889 4182 50 0000 R CNN
F 1 "LED" V 6798 4182 50 0000 R CNN
F 2 "" H 6850 4300 50 0001 C CNN
F 3 "~" H 6850 4300 50 0001 C CNN
1 6850 4300
0 -1 -1 0
$EndComp
Wire Wire Line
6850 3950 6850 4150
$Comp
L power:GND #PWR?
U 1 1 62A34783
P 6850 4500
F 0 "#PWR?" H 6850 4250 50 0001 C CNN
F 1 "GND" H 6855 4327 50 0000 C CNN
F 2 "" H 6850 4500 50 0001 C CNN
F 3 "" H 6850 4500 50 0001 C CNN
1 6850 4500
1 0 0 -1
$EndComp
Wire Wire Line
6850 4500 6850 4450
Wire Wire Line
5600 3950 6100 3950
Wire Wire Line
6600 3950 6850 3950
$EndSCHEMATC

592
brd/MainConBrd/MainConBrd.sch-bak Normal file
View file

@ -0,0 +1,592 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector_Generic:Conn_02x07_Odd_Even J?
U 1 1 6E59A9F7
P 3250 3850
F 0 "J?" H 3300 4367 50 0000 C CNN
F 1 "Conn_02x07_Odd_Even" H 3300 4276 50 0000 C CNN
F 2 "" H 3250 3850 50 0001 C CNN
F 3 "~" H 3250 3850 50 0001 C CNN
1 3250 3850
1 0 0 -1
$EndComp
$Comp
L Connector_Generic:Conn_02x07_Odd_Even J?
U 1 1 6E59B935
P 8250 3850
F 0 "J?" H 8300 4367 50 0000 C CNN
F 1 "Conn_02x07_Odd_Even" H 8300 4276 50 0000 C CNN
F 2 "" H 8250 3850 50 0001 C CNN
F 3 "~" H 8250 3850 50 0001 C CNN
1 8250 3850
1 0 0 -1
$EndComp
Wire Wire Line
3550 3850 3550 3900
Wire Wire Line
8650 3850 8550 3850
Wire Wire Line
2950 3800 2950 3850
Wire Wire Line
2950 3850 3050 3850
Wire Wire Line
3550 3750 3550 3650
Connection ~ 3550 3550
Wire Wire Line
3550 3550 3550 3200
Connection ~ 3550 3650
Wire Wire Line
3550 3650 3550 3550
Wire Wire Line
3050 3750 3050 3650
Connection ~ 3050 3550
Wire Wire Line
3050 3550 3050 3200
Connection ~ 3050 3650
Wire Wire Line
3050 3650 3050 3550
Wire Wire Line
3050 3950 3050 4050
Connection ~ 3050 4050
Wire Wire Line
3050 4050 3050 4150
Connection ~ 3050 4150
Wire Wire Line
3050 4150 3050 4500
Wire Wire Line
3550 3950 3550 4050
Connection ~ 3550 4050
Wire Wire Line
3550 4050 3550 4150
Connection ~ 3550 4150
Wire Wire Line
3550 4150 3550 4500
$Comp
L power:GND #PWR?
U 1 1 6E5A568F
P 3550 4500
F 0 "#PWR?" H 3550 4250 50 0001 C CNN
F 1 "GND" H 3555 4327 50 0000 C CNN
F 2 "" H 3550 4500 50 0001 C CNN
F 3 "" H 3550 4500 50 0001 C CNN
1 3550 4500
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5A5B89
P 3050 4500
F 0 "#PWR?" H 3050 4250 50 0001 C CNN
F 1 "GND" H 3055 4327 50 0000 C CNN
F 2 "" H 3050 4500 50 0001 C CNN
F 3 "" H 3050 4500 50 0001 C CNN
1 3050 4500
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5A5EB1
P 3550 3200
F 0 "#PWR?" H 3550 3050 50 0001 C CNN
F 1 "+24V" H 3565 3373 50 0000 C CNN
F 2 "" H 3550 3200 50 0001 C CNN
F 3 "" H 3550 3200 50 0001 C CNN
1 3550 3200
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5A6291
P 3050 3200
F 0 "#PWR?" H 3050 3050 50 0001 C CNN
F 1 "+24V" H 3065 3373 50 0000 C CNN
F 2 "" H 3050 3200 50 0001 C CNN
F 3 "" H 3050 3200 50 0001 C CNN
1 3050 3200
1 0 0 -1
$EndComp
Text Label 3850 3800 0 50 ~ 0
canh
Text Label 3850 3900 0 50 ~ 0
canl
Wire Wire Line
2950 3800 4700 3800
Wire Wire Line
4700 3800 4700 3850
Wire Wire Line
3550 3900 5200 3900
Wire Wire Line
5200 3900 5200 3850
Wire Wire Line
4700 3800 6100 3800
Wire Wire Line
6100 3800 6100 3850
Connection ~ 4700 3800
Wire Wire Line
5200 3900 6600 3900
Wire Wire Line
6600 3900 6600 3850
Connection ~ 5200 3900
Wire Wire Line
6100 3800 8050 3800
Wire Wire Line
8050 3800 8050 3850
Connection ~ 6100 3800
Wire Wire Line
6600 3900 8650 3900
Wire Wire Line
8650 3900 8650 3850
Connection ~ 6600 3900
Wire Wire Line
8050 3950 8050 4050
Connection ~ 8050 4050
Wire Wire Line
8050 4050 8050 4150
Connection ~ 8050 4150
Wire Wire Line
8050 4150 8050 4400
Wire Wire Line
8550 3950 8550 4050
Connection ~ 8550 4050
Wire Wire Line
8550 4050 8550 4150
Connection ~ 8550 4150
Wire Wire Line
8550 4150 8550 4400
Wire Wire Line
8050 3750 8050 3650
Connection ~ 8050 3550
Wire Wire Line
8050 3550 8050 3200
Connection ~ 8050 3650
Wire Wire Line
8050 3650 8050 3550
Wire Wire Line
8550 3750 8550 3650
Connection ~ 8550 3550
Wire Wire Line
8550 3550 8550 3200
Connection ~ 8550 3650
Wire Wire Line
8550 3650 8550 3550
$Comp
L power:+24V #PWR?
U 1 1 6E5B5261
P 4700 3200
F 0 "#PWR?" H 4700 3050 50 0001 C CNN
F 1 "+24V" H 4715 3373 50 0000 C CNN
F 2 "" H 4700 3200 50 0001 C CNN
F 3 "" H 4700 3200 50 0001 C CNN
1 4700 3200
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5B56B3
P 5200 3200
F 0 "#PWR?" H 5200 3050 50 0001 C CNN
F 1 "+24V" H 5215 3373 50 0000 C CNN
F 2 "" H 5200 3200 50 0001 C CNN
F 3 "" H 5200 3200 50 0001 C CNN
1 5200 3200
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5B5A85
P 6100 3200
F 0 "#PWR?" H 6100 3050 50 0001 C CNN
F 1 "+24V" H 6115 3373 50 0000 C CNN
F 2 "" H 6100 3200 50 0001 C CNN
F 3 "" H 6100 3200 50 0001 C CNN
1 6100 3200
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5B5EA8
P 6600 3200
F 0 "#PWR?" H 6600 3050 50 0001 C CNN
F 1 "+24V" H 6615 3373 50 0000 C CNN
F 2 "" H 6600 3200 50 0001 C CNN
F 3 "" H 6600 3200 50 0001 C CNN
1 6600 3200
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5B6183
P 8050 3200
F 0 "#PWR?" H 8050 3050 50 0001 C CNN
F 1 "+24V" H 8065 3373 50 0000 C CNN
F 2 "" H 8050 3200 50 0001 C CNN
F 3 "" H 8050 3200 50 0001 C CNN
1 8050 3200
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5B6625
P 8550 3200
F 0 "#PWR?" H 8550 3050 50 0001 C CNN
F 1 "+24V" H 8565 3373 50 0000 C CNN
F 2 "" H 8550 3200 50 0001 C CNN
F 3 "" H 8550 3200 50 0001 C CNN
1 8550 3200
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5B6A30
P 4700 4500
F 0 "#PWR?" H 4700 4250 50 0001 C CNN
F 1 "GND" H 4705 4327 50 0000 C CNN
F 2 "" H 4700 4500 50 0001 C CNN
F 3 "" H 4700 4500 50 0001 C CNN
1 4700 4500
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5B6D86
P 5200 4500
F 0 "#PWR?" H 5200 4250 50 0001 C CNN
F 1 "GND" H 5205 4327 50 0000 C CNN
F 2 "" H 5200 4500 50 0001 C CNN
F 3 "" H 5200 4500 50 0001 C CNN
1 5200 4500
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5B7076
P 6100 4500
F 0 "#PWR?" H 6100 4250 50 0001 C CNN
F 1 "GND" H 6105 4327 50 0000 C CNN
F 2 "" H 6100 4500 50 0001 C CNN
F 3 "" H 6100 4500 50 0001 C CNN
1 6100 4500
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5B73DD
P 6600 4500
F 0 "#PWR?" H 6600 4250 50 0001 C CNN
F 1 "GND" H 6605 4327 50 0000 C CNN
F 2 "" H 6600 4500 50 0001 C CNN
F 3 "" H 6600 4500 50 0001 C CNN
1 6600 4500
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5B7677
P 8050 4400
F 0 "#PWR?" H 8050 4150 50 0001 C CNN
F 1 "GND" H 8055 4227 50 0000 C CNN
F 2 "" H 8050 4400 50 0001 C CNN
F 3 "" H 8050 4400 50 0001 C CNN
1 8050 4400
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5B7E36
P 8550 4400
F 0 "#PWR?" H 8550 4150 50 0001 C CNN
F 1 "GND" H 8555 4227 50 0000 C CNN
F 2 "" H 8550 4400 50 0001 C CNN
F 3 "" H 8550 4400 50 0001 C CNN
1 8550 4400
1 0 0 -1
$EndComp
$Comp
L Device:CP C?
U 1 1 6E5C4915
P 3850 2750
F 0 "C?" H 3968 2796 50 0000 L CNN
F 1 "270uF" H 3968 2705 50 0000 L CNN
F 2 "Capacitor_THT:CP_Radial_D10.0mm_P5.00mm" H 3888 2600 50 0001 C CNN
F 3 "~" H 3850 2750 50 0001 C CNN
1 3850 2750
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5C5160
P 3850 2600
F 0 "#PWR?" H 3850 2450 50 0001 C CNN
F 1 "+24V" H 3865 2773 50 0000 C CNN
F 2 "" H 3850 2600 50 0001 C CNN
F 3 "" H 3850 2600 50 0001 C CNN
1 3850 2600
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5C557B
P 3850 2900
F 0 "#PWR?" H 3850 2650 50 0001 C CNN
F 1 "GND" H 3855 2727 50 0000 C CNN
F 2 "" H 3850 2900 50 0001 C CNN
F 3 "" H 3850 2900 50 0001 C CNN
1 3850 2900
1 0 0 -1
$EndComp
$Comp
L Device:CP C?
U 1 1 6E5C5BF2
P 4300 2750
F 0 "C?" H 4418 2796 50 0000 L CNN
F 1 "270uF" H 4418 2705 50 0000 L CNN
F 2 "Capacitor_THT:CP_Radial_D10.0mm_P5.00mm" H 4338 2600 50 0001 C CNN
F 3 "~" H 4300 2750 50 0001 C CNN
1 4300 2750
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5C5BF8
P 4300 2600
F 0 "#PWR?" H 4300 2450 50 0001 C CNN
F 1 "+24V" H 4315 2773 50 0000 C CNN
F 2 "" H 4300 2600 50 0001 C CNN
F 3 "" H 4300 2600 50 0001 C CNN
1 4300 2600
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5C5BFE
P 4300 2900
F 0 "#PWR?" H 4300 2650 50 0001 C CNN
F 1 "GND" H 4305 2727 50 0000 C CNN
F 2 "" H 4300 2900 50 0001 C CNN
F 3 "" H 4300 2900 50 0001 C CNN
1 4300 2900
1 0 0 -1
$EndComp
$Comp
L Device:CP C?
U 1 1 6E5C769E
P 7100 2800
F 0 "C?" H 7218 2846 50 0000 L CNN
F 1 "270uF" H 7218 2755 50 0000 L CNN
F 2 "Capacitor_THT:CP_Radial_D10.0mm_P5.00mm" H 7138 2650 50 0001 C CNN
F 3 "~" H 7100 2800 50 0001 C CNN
1 7100 2800
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5C76A4
P 7100 2650
F 0 "#PWR?" H 7100 2500 50 0001 C CNN
F 1 "+24V" H 7115 2823 50 0000 C CNN
F 2 "" H 7100 2650 50 0001 C CNN
F 3 "" H 7100 2650 50 0001 C CNN
1 7100 2650
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5C76AA
P 7100 2950
F 0 "#PWR?" H 7100 2700 50 0001 C CNN
F 1 "GND" H 7105 2777 50 0000 C CNN
F 2 "" H 7100 2950 50 0001 C CNN
F 3 "" H 7100 2950 50 0001 C CNN
1 7100 2950
1 0 0 -1
$EndComp
$Comp
L Device:CP C?
U 1 1 6E5C923D
P 7450 2800
F 0 "C?" H 7568 2846 50 0000 L CNN
F 1 "270uF" H 7568 2755 50 0000 L CNN
F 2 "Capacitor_THT:CP_Radial_D10.0mm_P5.00mm" H 7488 2650 50 0001 C CNN
F 3 "~" H 7450 2800 50 0001 C CNN
1 7450 2800
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5C9243
P 7450 2650
F 0 "#PWR?" H 7450 2500 50 0001 C CNN
F 1 "+24V" H 7465 2823 50 0000 C CNN
F 2 "" H 7450 2650 50 0001 C CNN
F 3 "" H 7450 2650 50 0001 C CNN
1 7450 2650
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5C9249
P 7450 2950
F 0 "#PWR?" H 7450 2700 50 0001 C CNN
F 1 "GND" H 7455 2777 50 0000 C CNN
F 2 "" H 7450 2950 50 0001 C CNN
F 3 "" H 7450 2950 50 0001 C CNN
1 7450 2950
1 0 0 -1
$EndComp
$Comp
L Connector_Generic:Conn_02x08_Odd_Even J?
U 1 1 62A239EC
P 4900 3850
F 0 "J?" H 4950 4367 50 0000 C CNN
F 1 "Conn_02x08_Odd_Even" H 4950 4276 50 0000 C CNN
F 2 "" H 4900 3850 50 0001 C CNN
F 3 "~" H 4900 3850 50 0001 C CNN
1 4900 3850
1 0 0 -1
$EndComp
Wire Wire Line
4700 3200 4700 3550
Wire Wire Line
5200 3200 5200 3550
Wire Wire Line
6100 3200 6100 3550
Wire Wire Line
6600 3200 6600 3550
Wire Wire Line
4700 3650 4700 3750
Wire Wire Line
4700 4250 4700 4500
Wire Wire Line
5200 4250 5200 4500
Wire Wire Line
5200 3650 5200 3750
Wire Wire Line
5200 3650 5200 3550
Connection ~ 5200 3650
Connection ~ 5200 3550
Wire Wire Line
4700 3650 4700 3550
Connection ~ 4700 3650
Connection ~ 4700 3550
Connection ~ 4700 4250
Wire Wire Line
4700 4050 4700 4150
Connection ~ 4700 4150
Wire Wire Line
4700 4150 4700 4250
Connection ~ 5200 4250
Wire Wire Line
5200 4050 5200 4150
Connection ~ 5200 4150
Wire Wire Line
5200 4150 5200 4250
$Comp
L Connector_Generic:Conn_02x08_Odd_Even J?
U 1 1 62A2BA86
P 6300 3850
F 0 "J?" H 6350 4367 50 0000 C CNN
F 1 "Conn_02x08_Odd_Even" H 6350 4276 50 0000 C CNN
F 2 "" H 6300 3850 50 0001 C CNN
F 3 "~" H 6300 3850 50 0001 C CNN
1 6300 3850
1 0 0 -1
$EndComp
Wire Wire Line
6100 3650 6100 3750
Wire Wire Line
6100 4250 6100 4500
Wire Wire Line
6600 4250 6600 4500
Wire Wire Line
6600 3650 6600 3750
Wire Wire Line
6100 3650 6100 3550
Connection ~ 6100 3650
Connection ~ 6100 3550
Wire Wire Line
6600 3650 6600 3550
Connection ~ 6600 3650
Connection ~ 6600 3550
Wire Wire Line
6100 4250 6100 4150
Connection ~ 6100 4250
Connection ~ 6100 4150
Wire Wire Line
6100 4150 6100 4050
Wire Wire Line
6600 4250 6600 4150
Connection ~ 6600 4250
Connection ~ 6600 4150
Wire Wire Line
6600 4150 6600 4050
$Comp
L Device:LED D?
U 1 1 62A331FE
P 4200 4300
F 0 "D?" V 4239 4182 50 0000 R CNN
F 1 "LED" V 4148 4182 50 0000 R CNN
F 2 "" H 4200 4300 50 0001 C CNN
F 3 "~" H 4200 4300 50 0001 C CNN
1 4200 4300
0 -1 -1 0
$EndComp
$Comp
L Device:LED D?
U 1 1 62A33CB9
P 5600 4300
F 0 "D?" V 5639 4182 50 0000 R CNN
F 1 "LED" V 5548 4182 50 0000 R CNN
F 2 "" H 5600 4300 50 0001 C CNN
F 3 "~" H 5600 4300 50 0001 C CNN
1 5600 4300
0 -1 -1 0
$EndComp
Wire Wire Line
5200 3950 5600 3950
Wire Wire Line
5600 3950 5600 4150
Wire Wire Line
4700 3950 4200 3950
Wire Wire Line
4200 3950 4200 4150
$Comp
L power:GND #PWR?
U 1 1 62A37B88
P 4200 4500
F 0 "#PWR?" H 4200 4250 50 0001 C CNN
F 1 "GND" H 4205 4327 50 0000 C CNN
F 2 "" H 4200 4500 50 0001 C CNN
F 3 "" H 4200 4500 50 0001 C CNN
1 4200 4500
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 62A37E78
P 5600 4500
F 0 "#PWR?" H 5600 4250 50 0001 C CNN
F 1 "GND" H 5605 4327 50 0000 C CNN
F 2 "" H 5600 4500 50 0001 C CNN
F 3 "" H 5600 4500 50 0001 C CNN
1 5600 4500
1 0 0 -1
$EndComp
Wire Wire Line
4200 4500 4200 4450
Wire Wire Line
5600 4500 5600 4450
$EndSCHEMATC

1
brd/MainConBrd/fp-info-cache Normal file
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@ -0,0 +1 @@
0

4
brd/MotorModule/1.sch Normal file
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@ -0,0 +1,4 @@
EESchema Schematic File Version 2
EELAYER 25 0
EELAYER END
$EndSCHEMATC

3
brd/MotorModule/_Library_1.dcm Normal file
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@ -0,0 +1,3 @@
EESchema-DOCLIB Version 2.0
#
#End Doc Library

104
brd/MotorModule/_Library_1.lib Normal file
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@ -0,0 +1,104 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# IRL3672
#
DEF IRL3672 DA 0 40 Y Y 1 F N
F0 "DA" -100 675 50 H V C CNN
F1 "IRL3672" 0 -200 50 H V C CNN
F2 "" 0 -200 50 H I C CNN
F3 "" 0 -200 50 H I C CNN
DRAW
C 175 450 146 0 1 0 N
C 175 50 146 1 1 0 N
S -150 625 450 -125 0 1 0 f
P 2 0 1 0 200 450 300 450 N
P 3 0 1 0 -150 400 50 400 50 500 N
P 3 0 1 0 100 400 150 400 150 350 N
P 3 0 1 0 150 400 150 450 100 450 N
P 3 0 1 0 400 500 400 400 450 400 N
P 4 0 1 0 100 450 125 475 125 425 100 450 N
P 4 0 1 0 250 450 200 400 300 400 250 450 N
P 5 0 1 0 -150 500 -50 500 -50 350 250 350 250 450 N
P 6 0 1 0 100 500 250 500 250 550 400 550 400 500 450 500 N
P 2 1 1 0 200 50 300 50 N
P 3 1 1 0 -150 0 50 0 50 100 N
P 3 1 1 0 100 0 150 0 150 -50 N
P 3 1 1 0 150 0 150 50 100 50 N
P 3 1 1 0 400 100 400 0 450 0 N
P 4 1 1 0 100 50 125 75 125 25 100 50 N
P 4 1 1 0 250 50 200 0 300 0 250 50 N
P 5 1 1 0 -150 100 -50 100 -50 -50 250 -50 250 50 N
P 6 1 1 0 100 100 250 100 250 150 400 150 400 100 450 100 N
X S2 1 -250 500 100 R 50 50 1 1 W
X G2 2 -250 400 100 R 50 50 1 1 I
X S1 3 -250 100 100 R 50 50 1 1 W
X G1 4 -250 0 100 R 50 50 1 1 I
X D1 5 550 0 100 L 50 50 1 1 w
X D1 6 550 100 100 L 50 50 1 1 w
X D2 7 550 400 100 L 50 50 1 1 w
X D2 8 550 500 100 L 50 50 1 1 w
ENDDRAW
ENDDEF
#
# RF4426
#
DEF RF4426 U 0 40 Y Y 1 F N
F0 "U" -50 50 50 H V C CNN
F1 "RF4426" 50 -550 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -100 -500 500 0 0 1 0 f
X NC 1 -200 -100 100 R 50 50 1 1 N
X INA 2 -200 -200 100 R 50 50 1 1 I
X INB 3 -200 -300 100 R 50 50 1 1 I
X GND 4 -200 -400 100 R 50 50 1 1 W
X OUTB 5 600 -400 100 L 50 50 1 1 O
X Vs 6 600 -300 100 L 50 50 1 1 W
X OUT1 7 600 -200 100 L 50 50 1 1 O
X NC 8 600 -100 100 L 50 50 1 1 N
ENDDRAW
ENDDEF
#
# ir2136
#
DEF ir2136 DA 0 40 Y Y 1 F N
F0 "DA" -100 100 50 H V C CNN
F1 "ir2136" 0 -1500 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -150 50 800 -1450 0 1 0 f
X vcc 1 -250 -50 100 R 50 50 1 1 W
X EN 10 -250 -950 100 R 50 50 1 1 I
X RCIN 11 -250 -1050 100 R 50 50 1 1 O
X GND 12 -250 -1150 100 R 50 50 1 1 W
X COM 13 -250 -1250 100 R 50 50 1 1 O
X LO3 14 -250 -1350 100 R 50 50 1 1 I
X LO2 15 900 -1350 100 L 50 50 1 1 I
X LO1 16 900 -1250 100 L 50 50 1 1 I
X NC 17 900 -1150 100 L 50 50 1 1 N
X VS3 18 900 -1050 100 L 50 50 1 1 O
X HO3 19 900 -950 100 L 50 50 1 1 O
X HIN1 2 -250 -150 100 R 50 50 1 1 I I
X VB3 20 900 -850 100 L 50 50 1 1 O
X NC 21 900 -750 100 L 50 50 1 1 N
X VS2 22 900 -650 100 L 50 50 1 1 O
X HO2 23 900 -550 100 L 50 50 1 1 O
X VB2 24 900 -450 100 L 50 50 1 1 O
X NC 25 900 -350 100 L 50 50 1 1 N
X VS1 26 900 -250 100 L 50 50 1 1 O
X HO1 27 900 -150 100 L 50 50 1 1 O
X VB1 28 900 -50 100 L 50 50 1 1 O
X HIN2 3 -250 -250 100 R 50 50 1 1 I I
X HIN3 4 -250 -350 100 R 50 50 1 1 I I
X LIN1 5 -250 -450 100 R 50 50 1 1 I I
X LIN2 6 -250 -550 100 R 50 50 1 1 I I
X LIN3 7 -250 -650 100 R 50 50 1 1 I I
X FAULT 8 -250 -750 100 R 50 50 1 1 O I
X ITRIP 9 -250 -850 100 R 50 50 1 1 O
ENDDRAW
ENDDEF
#
#End Library

889
brd/MotorModule/motor_board_220520-cache.lib Normal file
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@ -0,0 +1,889 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Amplifier_Operational_MCP6004
#
DEF Amplifier_Operational_MCP6004 U 0 5 Y Y 5 L N
F0 "U" 0 200 50 H V L CNN
F1 "Amplifier_Operational_MCP6004" 0 -200 50 H V L CNN
F2 "" -50 100 50 H I C CNN
F3 "" 50 200 50 H I C CNN
ALIAS LM324 TLC274 TLC279 TL074 LM324A MCP6004 TL084 TL064 LMV324 LMC6484 MCP604 MC33079 MC33174 MC33179 OPA1604 OPA1679 OPA4134 OPA4340UA OPA4376 MCP6L94 TSV914 ADA4807-4 TSV994
$FPLIST
SOIC*3.9x8.7mm*P1.27mm*
DIP*W7.62mm*
TSSOP*4.4x5mm*P0.65mm*
SSOP*5.3x6.2mm*P0.65mm*
MSOP*3x3mm*P0.5mm*
$ENDFPLIST
DRAW
P 4 1 1 10 -200 200 200 0 -200 -200 -200 200 f
P 4 2 1 10 -200 200 200 0 -200 -200 -200 200 f
P 4 3 1 10 -200 200 200 0 -200 -200 -200 200 f
P 4 4 1 10 -200 200 200 0 -200 -200 -200 200 f
X ~ 1 300 0 100 L 50 50 1 1 O
X - 2 -300 -100 100 R 50 50 1 1 I
X + 3 -300 100 100 R 50 50 1 1 I
X + 5 -300 100 100 R 50 50 2 1 I
X - 6 -300 -100 100 R 50 50 2 1 I
X ~ 7 300 0 100 L 50 50 2 1 O
X + 10 -300 100 100 R 50 50 3 1 I
X ~ 8 300 0 100 L 50 50 3 1 O
X - 9 -300 -100 100 R 50 50 3 1 I
X + 12 -300 100 100 R 50 50 4 1 I
X - 13 -300 -100 100 R 50 50 4 1 I
X ~ 14 300 0 100 L 50 50 4 1 O
X V- 11 -100 -300 150 U 50 50 5 1 W
X V+ 4 -100 300 150 D 50 50 5 1 W
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_01x03
#
DEF Connector_Generic_Conn_01x03 J 0 40 Y N 1 F N
F0 "J" 0 200 50 H V C CNN
F1 "Connector_Generic_Conn_01x03" 0 -200 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 150 50 -150 1 1 10 f
X Pin_1 1 -200 100 150 R 50 50 1 1 P
X Pin_2 2 -200 0 150 R 50 50 1 1 P
X Pin_3 3 -200 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_02x08_Odd_Even
#
DEF Connector_Generic_Conn_02x08_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 400 50 H V C CNN
F1 "Connector_Generic_Conn_02x08_Odd_Even" 50 -500 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 350 150 -450 1 1 10 f
S 150 -395 100 -405 1 1 6 N
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
X Pin_1 1 -200 300 150 R 50 50 1 1 P
X Pin_10 10 300 -100 150 L 50 50 1 1 P
X Pin_11 11 -200 -200 150 R 50 50 1 1 P
X Pin_12 12 300 -200 150 L 50 50 1 1 P
X Pin_13 13 -200 -300 150 R 50 50 1 1 P
X Pin_14 14 300 -300 150 L 50 50 1 1 P
X Pin_15 15 -200 -400 150 R 50 50 1 1 P
X Pin_16 16 300 -400 150 L 50 50 1 1 P
X Pin_2 2 300 300 150 L 50 50 1 1 P
X Pin_3 3 -200 200 150 R 50 50 1 1 P
X Pin_4 4 300 200 150 L 50 50 1 1 P
X Pin_5 5 -200 100 150 R 50 50 1 1 P
X Pin_6 6 300 100 150 L 50 50 1 1 P
X Pin_7 7 -200 0 150 R 50 50 1 1 P
X Pin_8 8 300 0 150 L 50 50 1 1 P
X Pin_9 9 -200 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_02x12_Odd_Even
#
DEF Connector_Generic_Conn_02x12_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 600 50 H V C CNN
F1 "Connector_Generic_Conn_02x12_Odd_Even" 50 -700 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -595 0 -605 1 1 6 N
S -50 -495 0 -505 1 1 6 N
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 405 0 395 1 1 6 N
S -50 505 0 495 1 1 6 N
S -50 550 150 -650 1 1 10 f
S 150 -595 100 -605 1 1 6 N
S 150 -495 100 -505 1 1 6 N
S 150 -395 100 -405 1 1 6 N
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
S 150 405 100 395 1 1 6 N
S 150 505 100 495 1 1 6 N
X Pin_1 1 -200 500 150 R 50 50 1 1 P
X Pin_10 10 300 100 150 L 50 50 1 1 P
X Pin_11 11 -200 0 150 R 50 50 1 1 P
X Pin_12 12 300 0 150 L 50 50 1 1 P
X Pin_13 13 -200 -100 150 R 50 50 1 1 P
X Pin_14 14 300 -100 150 L 50 50 1 1 P
X Pin_15 15 -200 -200 150 R 50 50 1 1 P
X Pin_16 16 300 -200 150 L 50 50 1 1 P
X Pin_17 17 -200 -300 150 R 50 50 1 1 P
X Pin_18 18 300 -300 150 L 50 50 1 1 P
X Pin_19 19 -200 -400 150 R 50 50 1 1 P
X Pin_2 2 300 500 150 L 50 50 1 1 P
X Pin_20 20 300 -400 150 L 50 50 1 1 P
X Pin_21 21 -200 -500 150 R 50 50 1 1 P
X Pin_22 22 300 -500 150 L 50 50 1 1 P
X Pin_23 23 -200 -600 150 R 50 50 1 1 P
X Pin_24 24 300 -600 150 L 50 50 1 1 P
X Pin_3 3 -200 400 150 R 50 50 1 1 P
X Pin_4 4 300 400 150 L 50 50 1 1 P
X Pin_5 5 -200 300 150 R 50 50 1 1 P
X Pin_6 6 300 300 150 L 50 50 1 1 P
X Pin_7 7 -200 200 150 R 50 50 1 1 P
X Pin_8 8 300 200 150 L 50 50 1 1 P
X Pin_9 9 -200 100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_02x20_Odd_Even
#
DEF Connector_Generic_Conn_02x20_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 1000 50 H V C CNN
F1 "Connector_Generic_Conn_02x20_Odd_Even" 50 -1100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -995 0 -1005 1 1 6 N
S -50 -895 0 -905 1 1 6 N
S -50 -795 0 -805 1 1 6 N
S -50 -695 0 -705 1 1 6 N
S -50 -595 0 -605 1 1 6 N
S -50 -495 0 -505 1 1 6 N
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 405 0 395 1 1 6 N
S -50 505 0 495 1 1 6 N
S -50 605 0 595 1 1 6 N
S -50 705 0 695 1 1 6 N
S -50 805 0 795 1 1 6 N
S -50 905 0 895 1 1 6 N
S -50 950 150 -1050 1 1 10 f
S 150 -995 100 -1005 1 1 6 N
S 150 -895 100 -905 1 1 6 N
S 150 -795 100 -805 1 1 6 N
S 150 -695 100 -705 1 1 6 N
S 150 -595 100 -605 1 1 6 N
S 150 -495 100 -505 1 1 6 N
S 150 -395 100 -405 1 1 6 N
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
S 150 405 100 395 1 1 6 N
S 150 505 100 495 1 1 6 N
S 150 605 100 595 1 1 6 N
S 150 705 100 695 1 1 6 N
S 150 805 100 795 1 1 6 N
S 150 905 100 895 1 1 6 N
X Pin_1 1 -200 900 150 R 50 50 1 1 P
X Pin_10 10 300 500 150 L 50 50 1 1 P
X Pin_11 11 -200 400 150 R 50 50 1 1 P
X Pin_12 12 300 400 150 L 50 50 1 1 P
X Pin_13 13 -200 300 150 R 50 50 1 1 P
X Pin_14 14 300 300 150 L 50 50 1 1 P
X Pin_15 15 -200 200 150 R 50 50 1 1 P
X Pin_16 16 300 200 150 L 50 50 1 1 P
X Pin_17 17 -200 100 150 R 50 50 1 1 P
X Pin_18 18 300 100 150 L 50 50 1 1 P
X Pin_19 19 -200 0 150 R 50 50 1 1 P
X Pin_2 2 300 900 150 L 50 50 1 1 P
X Pin_20 20 300 0 150 L 50 50 1 1 P
X Pin_21 21 -200 -100 150 R 50 50 1 1 P
X Pin_22 22 300 -100 150 L 50 50 1 1 P
X Pin_23 23 -200 -200 150 R 50 50 1 1 P
X Pin_24 24 300 -200 150 L 50 50 1 1 P
X Pin_25 25 -200 -300 150 R 50 50 1 1 P
X Pin_26 26 300 -300 150 L 50 50 1 1 P
X Pin_27 27 -200 -400 150 R 50 50 1 1 P
X Pin_28 28 300 -400 150 L 50 50 1 1 P
X Pin_29 29 -200 -500 150 R 50 50 1 1 P
X Pin_3 3 -200 800 150 R 50 50 1 1 P
X Pin_30 30 300 -500 150 L 50 50 1 1 P
X Pin_31 31 -200 -600 150 R 50 50 1 1 P
X Pin_32 32 300 -600 150 L 50 50 1 1 P
X Pin_33 33 -200 -700 150 R 50 50 1 1 P
X Pin_34 34 300 -700 150 L 50 50 1 1 P
X Pin_35 35 -200 -800 150 R 50 50 1 1 P
X Pin_36 36 300 -800 150 L 50 50 1 1 P
X Pin_37 37 -200 -900 150 R 50 50 1 1 P
X Pin_38 38 300 -900 150 L 50 50 1 1 P
X Pin_39 39 -200 -1000 150 R 50 50 1 1 P
X Pin_4 4 300 800 150 L 50 50 1 1 P
X Pin_40 40 300 -1000 150 L 50 50 1 1 P
X Pin_5 5 -200 700 150 R 50 50 1 1 P
X Pin_6 6 300 700 150 L 50 50 1 1 P
X Pin_7 7 -200 600 150 R 50 50 1 1 P
X Pin_8 8 300 600 150 L 50 50 1 1 P
X Pin_9 9 -200 500 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_02x25_Odd_Even
#
DEF Connector_Generic_Conn_02x25_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 1300 50 H V C CNN
F1 "Connector_Generic_Conn_02x25_Odd_Even" 50 -1300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -1195 0 -1205 1 1 6 N
S -50 -1095 0 -1105 1 1 6 N
S -50 -995 0 -1005 1 1 6 N
S -50 -895 0 -905 1 1 6 N
S -50 -795 0 -805 1 1 6 N
S -50 -695 0 -705 1 1 6 N
S -50 -595 0 -605 1 1 6 N
S -50 -495 0 -505 1 1 6 N
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 405 0 395 1 1 6 N
S -50 505 0 495 1 1 6 N
S -50 605 0 595 1 1 6 N
S -50 705 0 695 1 1 6 N
S -50 805 0 795 1 1 6 N
S -50 905 0 895 1 1 6 N
S -50 1005 0 995 1 1 6 N
S -50 1105 0 1095 1 1 6 N
S -50 1205 0 1195 1 1 6 N
S -50 1250 150 -1250 1 1 10 f
S 150 -1195 100 -1205 1 1 6 N
S 150 -1095 100 -1105 1 1 6 N
S 150 -995 100 -1005 1 1 6 N
S 150 -895 100 -905 1 1 6 N
S 150 -795 100 -805 1 1 6 N
S 150 -695 100 -705 1 1 6 N
S 150 -595 100 -605 1 1 6 N
S 150 -495 100 -505 1 1 6 N
S 150 -395 100 -405 1 1 6 N
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
S 150 405 100 395 1 1 6 N
S 150 505 100 495 1 1 6 N
S 150 605 100 595 1 1 6 N
S 150 705 100 695 1 1 6 N
S 150 805 100 795 1 1 6 N
S 150 905 100 895 1 1 6 N
S 150 1005 100 995 1 1 6 N
S 150 1105 100 1095 1 1 6 N
S 150 1205 100 1195 1 1 6 N
X Pin_1 1 -200 1200 150 R 50 50 1 1 P
X Pin_10 10 300 800 150 L 50 50 1 1 P
X Pin_11 11 -200 700 150 R 50 50 1 1 P
X Pin_12 12 300 700 150 L 50 50 1 1 P
X Pin_13 13 -200 600 150 R 50 50 1 1 P
X Pin_14 14 300 600 150 L 50 50 1 1 P
X Pin_15 15 -200 500 150 R 50 50 1 1 P
X Pin_16 16 300 500 150 L 50 50 1 1 P
X Pin_17 17 -200 400 150 R 50 50 1 1 P
X Pin_18 18 300 400 150 L 50 50 1 1 P
X Pin_19 19 -200 300 150 R 50 50 1 1 P
X Pin_2 2 300 1200 150 L 50 50 1 1 P
X Pin_20 20 300 300 150 L 50 50 1 1 P
X Pin_21 21 -200 200 150 R 50 50 1 1 P
X Pin_22 22 300 200 150 L 50 50 1 1 P
X Pin_23 23 -200 100 150 R 50 50 1 1 P
X Pin_24 24 300 100 150 L 50 50 1 1 P
X Pin_25 25 -200 0 150 R 50 50 1 1 P
X Pin_26 26 300 0 150 L 50 50 1 1 P
X Pin_27 27 -200 -100 150 R 50 50 1 1 P
X Pin_28 28 300 -100 150 L 50 50 1 1 P
X Pin_29 29 -200 -200 150 R 50 50 1 1 P
X Pin_3 3 -200 1100 150 R 50 50 1 1 P
X Pin_30 30 300 -200 150 L 50 50 1 1 P
X Pin_31 31 -200 -300 150 R 50 50 1 1 P
X Pin_32 32 300 -300 150 L 50 50 1 1 P
X Pin_33 33 -200 -400 150 R 50 50 1 1 P
X Pin_34 34 300 -400 150 L 50 50 1 1 P
X Pin_35 35 -200 -500 150 R 50 50 1 1 P
X Pin_36 36 300 -500 150 L 50 50 1 1 P
X Pin_37 37 -200 -600 150 R 50 50 1 1 P
X Pin_38 38 300 -600 150 L 50 50 1 1 P
X Pin_39 39 -200 -700 150 R 50 50 1 1 P
X Pin_4 4 300 1100 150 L 50 50 1 1 P
X Pin_40 40 300 -700 150 L 50 50 1 1 P
X Pin_41 41 -200 -800 150 R 50 50 1 1 P
X Pin_42 42 300 -800 150 L 50 50 1 1 P
X Pin_43 43 -200 -900 150 R 50 50 1 1 P
X Pin_44 44 300 -900 150 L 50 50 1 1 P
X Pin_45 45 -200 -1000 150 R 50 50 1 1 P
X Pin_46 46 300 -1000 150 L 50 50 1 1 P
X Pin_47 47 -200 -1100 150 R 50 50 1 1 P
X Pin_48 48 300 -1100 150 L 50 50 1 1 P
X Pin_49 49 -200 -1200 150 R 50 50 1 1 P
X Pin_5 5 -200 1000 150 R 50 50 1 1 P
X Pin_50 50 300 -1200 150 L 50 50 1 1 P
X Pin_6 6 300 1000 150 L 50 50 1 1 P
X Pin_7 7 -200 900 150 R 50 50 1 1 P
X Pin_8 8 300 900 150 L 50 50 1 1 P
X Pin_9 9 -200 800 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_CP
#
DEF Device_CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_CP" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
CP_*
$ENDFPLIST
DRAW
S -90 20 90 40 0 1 0 N
S 90 -20 -90 -40 0 1 0 F
P 2 0 1 0 -70 90 -30 90 N
P 2 0 1 0 -50 110 -50 70 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_CP1
#
DEF Device_CP1 C 0 10 N N 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_CP1" 25 -100 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
CP_*
$ENDFPLIST
DRAW
A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50
P 2 0 1 20 -80 30 80 30 N
P 2 0 1 0 -70 90 -30 90 N
P 2 0 1 0 -50 70 -50 110 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 130 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C_Small
#
DEF Device_C_Small C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "Device_C_Small" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 13 -60 -20 60 -20 N
P 2 0 1 12 -60 20 60 20 N
X ~ 1 0 100 80 D 50 50 1 1 P
X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Crystal
#
DEF Device_Crystal Y 0 40 N N 1 F N
F0 "Y" 0 150 50 H V C CNN
F1 "Device_Crystal" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Crystal*
$ENDFPLIST
DRAW
S -45 100 45 -100 0 1 12 N
P 2 0 1 0 -100 0 -75 0 N
P 2 0 1 20 -75 -50 -75 50 N
P 2 0 1 20 75 -50 75 50 N
P 2 0 1 0 100 0 75 0 N
X 1 1 -150 0 50 R 50 50 1 1 P
X 2 2 150 0 50 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Crystal_GND2_Small
#
DEF Device_Crystal_GND2_Small Y 0 40 Y N 1 F N
F0 "Y" 0 200 50 H V C CNN
F1 "Device_Crystal_GND2_Small" 0 125 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Crystal*
$ENDFPLIST
DRAW
S -30 -60 30 60 0 1 0 N
P 2 0 1 15 -50 -30 -50 30 N
P 2 0 1 15 50 -30 50 30 N
P 4 0 1 0 -50 -50 -50 -75 50 -75 50 -50 N
X 1 1 -100 0 50 R 30 50 1 1 P
X 2 2 0 -100 25 U 30 50 1 1 P
X 3 3 100 0 50 L 30 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_D_Small
#
DEF Device_D_Small D 0 10 N N 1 F N
F0 "D" -50 80 50 H V L CNN
F1 "Device_D_Small" -150 -80 50 H V L CNN
F2 "" 0 0 50 V I C CNN
F3 "" 0 0 50 V I C CNN
$FPLIST
TO-???*
*_Diode_*
*SingleDiode*
D_*
$ENDFPLIST
DRAW
P 2 0 1 10 -30 -40 -30 40 N
P 2 0 1 0 -30 0 30 0 N
P 4 0 1 10 30 -40 -30 0 30 40 30 -40 N
X K 1 -100 0 70 R 50 50 1 1 P
X A 2 100 0 70 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_L
#
DEF Device_L L 0 40 N N 1 F N
F0 "L" -50 0 50 V V C CNN
F1 "Device_L" 75 0 50 V V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Choke_*
*Coil*
Inductor_*
L_*
$ENDFPLIST
DRAW
A 0 -75 25 -899 899 0 1 0 N 0 -100 0 -50
A 0 -25 25 -899 899 0 1 0 N 0 -50 0 0
A 0 25 25 -899 899 0 1 0 N 0 0 0 50
A 0 75 25 -899 899 0 1 0 N 0 50 0 100
X 1 1 0 150 50 D 50 50 1 1 P
X 2 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_LED
#
DEF Device_LED D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "Device_LED" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
LED*
LED_SMD:*
LED_THT:*
$ENDFPLIST
DRAW
P 2 0 1 10 -50 -50 -50 50 N
P 2 0 1 0 -50 0 50 0 N
P 4 0 1 10 50 -50 50 50 -50 0 50 -50 N
P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Interface_UART_MAX485E
#
DEF Interface_UART_MAX485E U 0 20 Y Y 1 F N
F0 "U" -240 450 50 H V C CNN
F1 "Interface_UART_MAX485E" 30 450 50 H V L CNN
F2 "" 0 -700 50 H I C CNN
F3 "" 0 50 50 H I C CNN
ALIAS MAX483E MAX485E MAX487E MAX1487E MAX3485 MAX3483 MAX3486
$FPLIST
DIP*W7.62mm*
SOIC*3.9x4.9mm*P1.27mm*
$ENDFPLIST
DRAW
C -12 -145 14 0 1 10 F
C -1 59 14 0 1 10 F
C 65 75 14 0 1 10 F
S -300 400 300 -500 0 1 10 f
S 50 125 50 125 0 1 0 N
P 2 0 1 10 -160 -200 -75 -200 N
P 2 0 1 10 -160 100 -50 100 N
P 2 0 1 10 -50 -126 -50 -136 N
P 2 0 1 10 -25 -200 210 -200 N
P 3 0 1 10 -160 -100 -50 -100 -50 -125 N
P 3 0 1 10 0 50 0 0 -160 0 N
P 3 0 1 10 50 125 150 125 150 -200 N
P 3 0 1 10 100 75 100 -150 0 -150 N
P 4 0 1 10 -75 -125 -75 -225 25 -175 -75 -125 N
P 4 0 1 10 -50 100 50 150 50 50 -50 100 N
P 4 0 1 10 75 75 175 75 175 100 210 100 N
X RO 1 -400 100 100 R 50 50 1 1 O
X ~RE 2 -400 0 100 R 50 50 1 1 I
X DE 3 -400 -100 100 R 50 50 1 1 I
X DI 4 -400 -200 100 R 50 50 1 1 I
X GND 5 0 -600 100 U 50 50 1 1 W
X A 6 400 -200 100 L 50 50 1 1 B
X B 7 400 100 100 L 50 50 1 1 B
X VCC 8 0 500 100 D 50 50 1 1 W
ENDDRAW
ENDDEF
#
# MCU_ST_STM32F4_STM32F446RETx
#
DEF MCU_ST_STM32F4_STM32F446RETx U 0 20 Y Y 1 F N
F0 "U" -600 1650 50 H V L CNN
F1 "MCU_ST_STM32F4_STM32F446RETx" 400 1650 50 H V L CNN
F2 "Package_QFP:LQFP-64_10x10mm_P0.5mm" -600 -1700 50 H I R CNN
F3 "" 0 0 50 H I C CNN
ALIAS STM32F446RETx
$FPLIST
LQFP*10x10mm*P0.5mm*
$ENDFPLIST
DRAW
S -600 -1700 600 1600 0 1 10 f
X VBAT 1 -200 1700 100 D 50 50 1 1 W
X PC2 10 -700 -300 100 R 50 50 1 1 B
X PC3 11 -700 -400 100 R 50 50 1 1 B
X VSSA 12 200 -1800 100 U 50 50 1 1 W
X VDDA 13 300 1700 100 D 50 50 1 1 W
X PA0 14 700 1500 100 L 50 50 1 1 B
X PA1 15 700 1400 100 L 50 50 1 1 B
X PA2 16 700 1300 100 L 50 50 1 1 B
X PA3 17 700 1200 100 L 50 50 1 1 B
X VSS 18 -200 -1800 100 U 50 50 1 1 W
X VDD 19 -100 1700 100 D 50 50 1 1 W
X PC13 2 -700 -1400 100 R 50 50 1 1 B
X PA4 20 700 1100 100 L 50 50 1 1 B
X PA5 21 700 1000 100 L 50 50 1 1 B
X PA6 22 700 900 100 L 50 50 1 1 B
X PA7 23 700 800 100 L 50 50 1 1 B
X PC4 24 -700 -500 100 R 50 50 1 1 B
X PC5 25 -700 -600 100 R 50 50 1 1 B
X PB0 26 700 -200 100 L 50 50 1 1 B
X PB1 27 700 -300 100 L 50 50 1 1 B
X PB2 28 700 -400 100 L 50 50 1 1 B
X PB10 29 700 -1200 100 L 50 50 1 1 B
X PC14 3 -700 -1500 100 R 50 50 1 1 B
X VCAP_1 30 -700 1100 100 R 50 50 1 1 W
X VSS 31 -100 -1800 100 U 50 50 1 1 W
X VDD 32 0 1700 100 D 50 50 1 1 W
X PB12 33 700 -1300 100 L 50 50 1 1 B
X PB13 34 700 -1400 100 L 50 50 1 1 B
X PB14 35 700 -1500 100 L 50 50 1 1 B
X PB15 36 700 -1600 100 L 50 50 1 1 B
X PC6 37 -700 -700 100 R 50 50 1 1 B
X PC7 38 -700 -800 100 R 50 50 1 1 B
X PC8 39 -700 -900 100 R 50 50 1 1 B
X PC15 4 -700 -1600 100 R 50 50 1 1 B
X PC9 40 -700 -1000 100 R 50 50 1 1 B
X PA8 41 700 700 100 L 50 50 1 1 B
X PA9 42 700 600 100 L 50 50 1 1 B
X PA10 43 700 500 100 L 50 50 1 1 B
X PA11 44 700 400 100 L 50 50 1 1 B
X PA12 45 700 300 100 L 50 50 1 1 B
X PA13 46 700 200 100 L 50 50 1 1 B
X VSS 47 0 -1800 100 U 50 50 1 1 W
X VDD 48 100 1700 100 D 50 50 1 1 W
X PA14 49 700 100 100 L 50 50 1 1 B
X PH0 5 -700 400 100 R 50 50 1 1 I
X PA15 50 700 0 100 L 50 50 1 1 B
X PC10 51 -700 -1100 100 R 50 50 1 1 B
X PC11 52 -700 -1200 100 R 50 50 1 1 B
X PC12 53 -700 -1300 100 R 50 50 1 1 B
X PD2 54 -700 100 100 R 50 50 1 1 B
X PB3 55 700 -500 100 L 50 50 1 1 B
X PB4 56 700 -600 100 L 50 50 1 1 B
X PB5 57 700 -700 100 L 50 50 1 1 B
X PB6 58 700 -800 100 L 50 50 1 1 B
X PB7 59 700 -900 100 L 50 50 1 1 B
X PH1 6 -700 300 100 R 50 50 1 1 I
X BOOT0 60 -700 1300 100 R 50 50 1 1 I
X PB8 61 700 -1000 100 L 50 50 1 1 B
X PB9 62 700 -1100 100 L 50 50 1 1 B
X VSS 63 100 -1800 100 U 50 50 1 1 W
X VDD 64 200 1700 100 D 50 50 1 1 W
X NRST 7 -700 1500 100 R 50 50 1 1 I
X PC0 8 -700 -100 100 R 50 50 1 1 B
X PC1 9 -700 -200 100 R 50 50 1 1 B
ENDDRAW
ENDDEF
#
# Regulator_Switching_LM2594HVM-3.3
#
DEF Regulator_Switching_LM2594HVM-3.3 U 0 20 Y Y 1 F N
F0 "U" -300 250 50 H V L CNN
F1 "Regulator_Switching_LM2594HVM-3.3" 0 250 50 H V L CNN
F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 200 -250 50 H I L CIN
F3 "" 0 100 50 H I C CNN
ALIAS LM2594M-5.0 LM2594M-12 LM2594M-ADJ LM2594HVM-3.3 LM2594HVM-5.0 LM2594HVM-12 LM2594HVM-ADJ
$FPLIST
SOIC*3.9x4.9mm*
$ENDFPLIST
DRAW
S -300 200 300 -200 0 1 10 f
X NC 1 -200 -300 100 U 50 50 1 1 P
X NC 2 -100 -300 100 U 50 50 1 1 P
X NC 3 0 -300 100 U 50 50 1 1 P
X FB 4 400 100 100 L 50 50 1 1 I
X ~ON~/OFF 5 -400 0 100 R 50 50 1 1 I
X GND 6 200 -300 100 U 50 50 1 1 W
X VIN 7 -400 100 100 R 50 50 1 1 W
X OUT 8 400 0 100 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# Sensor_Magnetic_AS5045B
#
DEF Sensor_Magnetic_AS5045B U 0 20 Y Y 1 F N
F0 "U" -400 450 50 H V L CNN
F1 "Sensor_Magnetic_AS5045B" 450 450 50 H V R CNN
F2 "Package_SO:SSOP-16_5.3x6.2mm_P0.65mm" 150 -450 50 H I L CNN
F3 "" -2150 1600 50 H I C CNN
$FPLIST
SSOP*5.3x6.2mm*P0.65mm*
$ENDFPLIST
DRAW
A 0 0 110 -1799 -1 0 1 10 N -110 0 110 0
C 0 0 80 0 1 10 N
S -400 400 400 -400 0 1 10 f
P 2 0 1 10 -110 0 -130 -20 N
P 2 0 1 10 -110 0 -90 -20 N
P 2 0 1 10 110 0 90 -20 N
P 2 0 1 10 110 0 130 -20 N
P 4 0 1 0 10 10 50 -30 30 -50 -10 -10 N
P 7 0 1 0 -30 50 10 10 -10 -10 -50 30 -40 40 -30 50 -25 45 F
X MagINCn 1 -500 -200 100 R 50 50 1 1 C
X CLK 10 500 100 100 L 50 50 1 1 I
X CSn 11 500 0 100 L 50 50 1 1 I
X PWM 12 500 -300 100 L 50 50 1 1 O
X NC 13 400 -200 100 L 50 50 1 1 N N
X NC 14 100 -400 100 U 50 50 1 1 N N
X VDD3V3 15 -100 500 100 D 50 50 1 1 W
X VDD5V 16 0 500 100 D 50 50 1 1 W
X MagDECn 2 -500 -300 100 R 50 50 1 1 C
X A 3 -500 300 100 R 50 50 1 1 O
X B 4 -500 200 100 R 50 50 1 1 O
X NC 5 400 -100 100 L 50 50 1 1 N N
X I 6 -500 100 100 R 50 50 1 1 O
X VSS 7 0 -500 100 U 50 50 1 1 W
X PDIO 8 500 300 100 L 50 50 1 1 I
X DO 9 500 200 100 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# _Library_1_drv8313
#
DEF _Library_1_drv8313 U 0 40 Y Y 1 F N
F0 "U" -300 50 50 H V C CNN
F1 "_Library_1_drv8313" 200 50 50 H V C CNN
F2 "" -700 0 50 H I C CNN
F3 "" -700 0 50 H I C CNN
DRAW
S -450 -50 350 -1550 0 1 0 f
X cpl 1 -550 -150 100 R 50 50 1 1 I
X pgnd3 10 -550 -1050 100 R 50 50 1 1 I
X vm 11 -550 -1150 100 R 50 50 1 1 I
X compp 12 -550 -1250 100 R 50 50 1 1 I
X compn 13 -550 -1350 100 R 50 50 1 1 I
X gnd 14 -550 -1450 100 R 50 50 1 1 W
X v3p3 15 450 -1450 100 L 50 50 1 1 w
X nReset 16 450 -1350 100 L 50 50 1 1 I
X nSleep 17 450 -1250 100 L 50 50 1 1 I
X nFault 18 450 -1150 100 L 50 50 1 1 O
X nCompo 19 450 -1050 100 L 50 50 1 1 I
X cph 2 -550 -250 100 R 50 50 1 1 I
X gnd 20 450 -950 100 L 50 50 1 1 W
X nc 21 450 -850 100 L 50 50 1 1 I
X en3 22 450 -750 100 L 50 50 1 1 I
X in3 23 450 -650 100 L 50 50 1 1 I
X en2 24 450 -550 100 L 50 50 1 1 I
X in2 25 450 -450 100 L 50 50 1 1 I
X en1 26 450 -350 100 L 50 50 1 1 I
X in1 27 450 -250 100 L 50 50 1 1 I
X gnd 28 450 -150 100 L 50 50 1 1 W
X vcp 3 -550 -350 100 R 50 50 1 1 I
X vm 4 -550 -450 100 R 50 50 1 1 I
X out1 5 -550 -550 100 R 50 50 1 1 O
X pgnd1 6 -550 -650 100 R 50 50 1 1 I
X pgnd2 7 -550 -750 100 R 50 50 1 1 I
X out2 8 -550 -850 100 R 50 50 1 1 O
X out3 9 -550 -950 100 R 50 50 1 1 O
ENDDRAW
ENDDEF
#
# kicad_Library_PROGRAMMATOR
#
DEF kicad_Library_PROGRAMMATOR xp 0 40 Y Y 1 F N
F0 "xp" -350 900 50 H V C CNN
F1 "kicad_Library_PROGRAMMATOR" -400 200 50 H V C CNN
F2 "Connector_IDC:IDC-Header_2x05_P2.54mm_Vertical" -350 900 50 H I C CNN
F3 "" -350 900 50 H I C CNN
DRAW
S -700 800 50 300 0 1 0 f
X GND 1 -800 750 100 R 50 50 1 1 P
X +5V 10 150 350 100 L 50 50 1 1 w
X +3V 2 150 750 100 L 50 50 1 1 w
X RESET 3 -800 650 100 R 50 50 1 1 I
X BOOT 4 150 650 100 L 50 50 1 1 I
X RX 5 -800 550 100 R 50 50 1 1 I
X TX 6 150 550 100 L 50 50 1 1 O
X SWDCLK 7 -800 450 100 R 50 50 1 1 I
X SWDDTA 8 150 450 100 L 50 50 1 1 B
X GND 9 -800 350 100 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_+24V
#
DEF power_+24V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+24V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +24V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+3.3V
#
DEF power_+3.3V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3.3V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+3.3VADC
#
DEF power_+3.3VADC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 150 -50 50 H I C CNN
F1 "power_+3.3VADC" 0 100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3.3VADC 1 0 0 0 U 50 50 0 0 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

739
brd/MotorModule/motor_controller_220520-cache.lib Normal file
View file

@ -0,0 +1,739 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_Generic_Conn_02x05_Counter_Clockwise
#
DEF Connector_Generic_Conn_02x05_Counter_Clockwise J 0 40 Y N 1 F N
F0 "J" 50 300 50 H V C CNN
F1 "Connector_Generic_Conn_02x05_Counter_Clockwise" 50 -300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 250 150 -250 1 1 10 f
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
X Pin_1 1 -200 200 150 R 50 50 1 1 P
X Pin_10 10 300 200 150 L 50 50 1 1 P
X Pin_2 2 -200 100 150 R 50 50 1 1 P
X Pin_3 3 -200 0 150 R 50 50 1 1 P
X Pin_4 4 -200 -100 150 R 50 50 1 1 P
X Pin_5 5 -200 -200 150 R 50 50 1 1 P
X Pin_6 6 300 -200 150 L 50 50 1 1 P
X Pin_7 7 300 -100 150 L 50 50 1 1 P
X Pin_8 8 300 0 150 L 50 50 1 1 P
X Pin_9 9 300 100 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_02x07_Odd_Even
#
DEF Connector_Generic_Conn_02x07_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 400 50 H V C CNN
F1 "Connector_Generic_Conn_02x07_Odd_Even" 50 -400 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 350 150 -350 1 1 10 f
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
X Pin_1 1 -200 300 150 R 50 50 1 1 P
X Pin_10 10 300 -100 150 L 50 50 1 1 P
X Pin_11 11 -200 -200 150 R 50 50 1 1 P
X Pin_12 12 300 -200 150 L 50 50 1 1 P
X Pin_13 13 -200 -300 150 R 50 50 1 1 P
X Pin_14 14 300 -300 150 L 50 50 1 1 P
X Pin_2 2 300 300 150 L 50 50 1 1 P
X Pin_3 3 -200 200 150 R 50 50 1 1 P
X Pin_4 4 300 200 150 L 50 50 1 1 P
X Pin_5 5 -200 100 150 R 50 50 1 1 P
X Pin_6 6 300 100 150 L 50 50 1 1 P
X Pin_7 7 -200 0 150 R 50 50 1 1 P
X Pin_8 8 300 0 150 L 50 50 1 1 P
X Pin_9 9 -200 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_CP
#
DEF Device_CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_CP" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
CP_*
$ENDFPLIST
DRAW
S -90 20 90 40 0 1 0 N
S 90 -20 -90 -40 0 1 0 F
P 2 0 1 0 -70 90 -30 90 N
P 2 0 1 0 -50 110 -50 70 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_CP1
#
DEF Device_CP1 C 0 10 N N 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_CP1" 25 -100 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
CP_*
$ENDFPLIST
DRAW
A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50
P 2 0 1 20 -80 30 80 30 N
P 2 0 1 0 -70 90 -30 90 N
P 2 0 1 0 -50 70 -50 110 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 130 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C_Small
#
DEF Device_C_Small C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "Device_C_Small" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 13 -60 -20 60 -20 N
P 2 0 1 12 -60 20 60 20 N
X ~ 1 0 100 80 D 50 50 1 1 P
X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Crystal
#
DEF Device_Crystal Y 0 40 N N 1 F N
F0 "Y" 0 150 50 H V C CNN
F1 "Device_Crystal" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Crystal*
$ENDFPLIST
DRAW
S -45 100 45 -100 0 1 12 N
P 2 0 1 0 -100 0 -75 0 N
P 2 0 1 20 -75 -50 -75 50 N
P 2 0 1 20 75 -50 75 50 N
P 2 0 1 0 100 0 75 0 N
X 1 1 -150 0 50 R 50 50 1 1 P
X 2 2 150 0 50 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_D
#
DEF Device_D D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "Device_D" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
TO-???*
*_Diode_*
*SingleDiode*
D_*
$ENDFPLIST
DRAW
P 2 0 1 10 -50 50 -50 -50 N
P 2 0 1 0 50 0 -50 0 N
P 4 0 1 10 50 50 50 -50 -50 0 50 50 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_D_Small
#
DEF Device_D_Small D 0 10 N N 1 F N
F0 "D" -50 80 50 H V L CNN
F1 "Device_D_Small" -150 -80 50 H V L CNN
F2 "" 0 0 50 V I C CNN
F3 "" 0 0 50 V I C CNN
$FPLIST
TO-???*
*_Diode_*
*SingleDiode*
D_*
$ENDFPLIST
DRAW
P 2 0 1 10 -30 -40 -30 40 N
P 2 0 1 0 -30 0 30 0 N
P 4 0 1 10 30 -40 -30 0 30 40 30 -40 N
X K 1 -100 0 70 R 50 50 1 1 P
X A 2 100 0 70 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_L
#
DEF Device_L L 0 40 N N 1 F N
F0 "L" -50 0 50 V V C CNN
F1 "Device_L" 75 0 50 V V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Choke_*
*Coil*
Inductor_*
L_*
$ENDFPLIST
DRAW
A 0 -75 25 -899 899 0 1 0 N 0 -100 0 -50
A 0 -25 25 -899 899 0 1 0 N 0 -50 0 0
A 0 25 25 -899 899 0 1 0 N 0 0 0 50
A 0 75 25 -899 899 0 1 0 N 0 50 0 100
X 1 1 0 150 50 D 50 50 1 1 P
X 2 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_LED
#
DEF Device_LED D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "Device_LED" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
LED*
LED_SMD:*
LED_THT:*
$ENDFPLIST
DRAW
P 2 0 1 10 -50 -50 -50 50 N
P 2 0 1 0 -50 0 50 0 N
P 4 0 1 10 50 -50 50 50 -50 0 50 -50 N
P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Interface_CAN_LIN_MCP2551-I-SN
#
DEF Interface_CAN_LIN_MCP2551-I-SN U 0 40 Y Y 1 F N
F0 "U" -400 350 50 H V L CNN
F1 "Interface_CAN_LIN_MCP2551-I-SN" 100 350 50 H V L CNN
F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 -500 50 H I C CIN
F3 "" 0 0 50 H I C CNN
$FPLIST
SOIC*3.9x4.9mm*P1.27mm*
$ENDFPLIST
DRAW
S -400 300 400 -300 0 1 10 f
X TXD 1 -500 200 100 R 50 50 1 1 I
X VSS 2 0 -400 100 U 50 50 1 1 W
X VDD 3 0 400 100 D 50 50 1 1 W
X RXD 4 -500 100 100 R 50 50 1 1 O
X Vref 5 -500 -100 100 R 50 50 1 1 w
X CANL 6 500 -100 100 L 50 50 1 1 B
X CANH 7 500 100 100 L 50 50 1 1 B
X Rs 8 -500 -200 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# MCU_ST_STM32F4_STM32F446RETx
#
DEF MCU_ST_STM32F4_STM32F446RETx U 0 20 Y Y 1 F N
F0 "U" -600 1650 50 H V L CNN
F1 "MCU_ST_STM32F4_STM32F446RETx" 400 1650 50 H V L CNN
F2 "Package_QFP:LQFP-64_10x10mm_P0.5mm" -600 -1700 50 H I R CNN
F3 "" 0 0 50 H I C CNN
ALIAS STM32F446RETx
$FPLIST
LQFP*10x10mm*P0.5mm*
$ENDFPLIST
DRAW
S -600 -1700 600 1600 0 1 10 f
X VBAT 1 -200 1700 100 D 50 50 1 1 W
X PC2 10 -700 -300 100 R 50 50 1 1 B
X PC3 11 -700 -400 100 R 50 50 1 1 B
X VSSA 12 200 -1800 100 U 50 50 1 1 W
X VDDA 13 300 1700 100 D 50 50 1 1 W
X PA0 14 700 1500 100 L 50 50 1 1 B
X PA1 15 700 1400 100 L 50 50 1 1 B
X PA2 16 700 1300 100 L 50 50 1 1 B
X PA3 17 700 1200 100 L 50 50 1 1 B
X VSS 18 -200 -1800 100 U 50 50 1 1 W
X VDD 19 -100 1700 100 D 50 50 1 1 W
X PC13 2 -700 -1400 100 R 50 50 1 1 B
X PA4 20 700 1100 100 L 50 50 1 1 B
X PA5 21 700 1000 100 L 50 50 1 1 B
X PA6 22 700 900 100 L 50 50 1 1 B
X PA7 23 700 800 100 L 50 50 1 1 B
X PC4 24 -700 -500 100 R 50 50 1 1 B
X PC5 25 -700 -600 100 R 50 50 1 1 B
X PB0 26 700 -200 100 L 50 50 1 1 B
X PB1 27 700 -300 100 L 50 50 1 1 B
X PB2 28 700 -400 100 L 50 50 1 1 B
X PB10 29 700 -1200 100 L 50 50 1 1 B
X PC14 3 -700 -1500 100 R 50 50 1 1 B
X VCAP_1 30 -700 1100 100 R 50 50 1 1 W
X VSS 31 -100 -1800 100 U 50 50 1 1 W
X VDD 32 0 1700 100 D 50 50 1 1 W
X PB12 33 700 -1300 100 L 50 50 1 1 B
X PB13 34 700 -1400 100 L 50 50 1 1 B
X PB14 35 700 -1500 100 L 50 50 1 1 B
X PB15 36 700 -1600 100 L 50 50 1 1 B
X PC6 37 -700 -700 100 R 50 50 1 1 B
X PC7 38 -700 -800 100 R 50 50 1 1 B
X PC8 39 -700 -900 100 R 50 50 1 1 B
X PC15 4 -700 -1600 100 R 50 50 1 1 B
X PC9 40 -700 -1000 100 R 50 50 1 1 B
X PA8 41 700 700 100 L 50 50 1 1 B
X PA9 42 700 600 100 L 50 50 1 1 B
X PA10 43 700 500 100 L 50 50 1 1 B
X PA11 44 700 400 100 L 50 50 1 1 B
X PA12 45 700 300 100 L 50 50 1 1 B
X PA13 46 700 200 100 L 50 50 1 1 B
X VSS 47 0 -1800 100 U 50 50 1 1 W
X VDD 48 100 1700 100 D 50 50 1 1 W
X PA14 49 700 100 100 L 50 50 1 1 B
X PH0 5 -700 400 100 R 50 50 1 1 I
X PA15 50 700 0 100 L 50 50 1 1 B
X PC10 51 -700 -1100 100 R 50 50 1 1 B
X PC11 52 -700 -1200 100 R 50 50 1 1 B
X PC12 53 -700 -1300 100 R 50 50 1 1 B
X PD2 54 -700 100 100 R 50 50 1 1 B
X PB3 55 700 -500 100 L 50 50 1 1 B
X PB4 56 700 -600 100 L 50 50 1 1 B
X PB5 57 700 -700 100 L 50 50 1 1 B
X PB6 58 700 -800 100 L 50 50 1 1 B
X PB7 59 700 -900 100 L 50 50 1 1 B
X PH1 6 -700 300 100 R 50 50 1 1 I
X BOOT0 60 -700 1300 100 R 50 50 1 1 I
X PB8 61 700 -1000 100 L 50 50 1 1 B
X PB9 62 700 -1100 100 L 50 50 1 1 B
X VSS 63 100 -1800 100 U 50 50 1 1 W
X VDD 64 200 1700 100 D 50 50 1 1 W
X NRST 7 -700 1500 100 R 50 50 1 1 I
X PC0 8 -700 -100 100 R 50 50 1 1 B
X PC1 9 -700 -200 100 R 50 50 1 1 B
ENDDRAW
ENDDEF
#
# Regulator_Linear_MIC5219-3.3YM5
#
DEF Regulator_Linear_MIC5219-3.3YM5 U 0 10 Y Y 1 F N
F0 "U" -150 225 50 H V C CNN
F1 "Regulator_Linear_MIC5219-3.3YM5" 0 225 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-23-5" 0 325 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS AP131-18 AP131-20 AP131-25 AP131-28 AP131-29 AP131-30 AP131-33 AP131-35 MIC5205-2.5YM5 MIC5205-2.7YM5 MIC5205-2.8YM5 MIC5205-2.85YM5 MIC5205-2.9YM5 MIC5205-3.0YM5 MIC5205-3.1YM5 MIC5205-3.2YM5 MIC5205-3.3YM5 MIC5205-3.6YM5 MIC5205-3.8YM5 MIC5205-4.0YM5 MIC5205-5.0YM5 MIC5219-2.5YM5 MIC5219-2.6YM5 MIC5219-2.7YM5 MIC5219-2.8YM5 MIC5219-2.85YM5 MIC5219-2.9YM5 MIC5219-3.0YM5 MIC5219-3.1YM5 MIC5219-3.3YM5 MIC5219-3.6YM5 MIC5219-5.0YM5 SPX3819M5-L-1-2 SPX3819M5-L-1-5 SPX3819M5-L-1-8 SPX3819M5-L-2-5 SPX3819M5-L-3-0 SPX3819M5-L-3-3 SPX3819M5-L-5-0
$FPLIST
SOT?23*
$ENDFPLIST
DRAW
S -200 175 200 -200 0 1 10 f
X IN 1 -300 100 100 R 50 50 1 1 W
X GND 2 0 -300 100 U 50 50 1 1 W
X EN 3 -300 0 100 R 50 50 1 1 I
X BP 4 300 0 100 L 50 50 1 1 I
X OUT 5 300 100 100 L 50 50 1 1 w
ENDDRAW
ENDDEF
#
# Sensor_Current_ACS712xLCTR-30A
#
DEF Sensor_Current_ACS712xLCTR-30A U 0 20 Y Y 1 F N
F0 "U" 100 450 50 H V L CNN
F1 "Sensor_Current_ACS712xLCTR-30A" 100 350 50 H V L CNN
F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 100 -350 50 H I L CIN
F3 "" 0 0 50 H I C CNN
ALIAS ACS712xLCTR-20A ACS712xLCTR-30A ACS713xLCTR-20A ACS713xLCTR-30A ACS714xLCTR-05B ACS714xLCTR-20A ACS714xLCTR-30A ACS714xLCTR-50A ACS715xLCTR-20A ACS715xLCTR-30A ACS724xLCTR-05AB ACS724xLCTR-10AB ACS724xLCTR-10AU ACS724xLCTR-20AB ACS724xLCTR-20AU ACS724xLCTR-30AB ACS724xLCTR-30AU ACS724xLCTR-50AB ACS725xLCTR-10AU ACS725xLCTR-20AB ACS725xLCTR-20AU ACS725xLCTR-30AB ACS725xLCTR-30AU ACS725xLCTR-40AB ACS725xLCTR-50AB
$FPLIST
SOIC*3.9x4.9m*P1.27mm*
$ENDFPLIST
DRAW
S -300 300 300 -300 0 1 10 f
X IP+ 1 -400 200 100 R 50 50 1 1 P
X IP+ 2 -400 200 100 R 50 50 1 1 P N
X IP- 3 -400 -200 100 R 50 50 1 1 P
X IP- 4 -400 -200 100 R 50 50 1 1 P N
X GND 5 0 -400 100 U 50 50 1 1 W
X FILTER 6 400 -100 100 L 50 50 1 1 P
X VIOUT 7 400 0 100 L 50 50 1 1 O
X VCC 8 0 400 100 D 50 50 1 1 W
ENDDRAW
ENDDEF
#
# Sensor_Magnetic_AS5045B
#
DEF Sensor_Magnetic_AS5045B U 0 20 Y Y 1 F N
F0 "U" -400 450 50 H V L CNN
F1 "Sensor_Magnetic_AS5045B" 450 450 50 H V R CNN
F2 "Package_SO:SSOP-16_5.3x6.2mm_P0.65mm" 150 -450 50 H I L CNN
F3 "" -2150 1600 50 H I C CNN
$FPLIST
SSOP*5.3x6.2mm*P0.65mm*
$ENDFPLIST
DRAW
A 0 0 110 -1799 -1 0 1 10 N -110 0 110 0
C 0 0 80 0 1 10 N
S -400 400 400 -400 0 1 10 f
P 2 0 1 10 -110 0 -130 -20 N
P 2 0 1 10 -110 0 -90 -20 N
P 2 0 1 10 110 0 90 -20 N
P 2 0 1 10 110 0 130 -20 N
P 4 0 1 0 10 10 50 -30 30 -50 -10 -10 N
P 7 0 1 0 -30 50 10 10 -10 -10 -50 30 -40 40 -30 50 -25 45 F
X MagINCn 1 -500 -200 100 R 50 50 1 1 C
X CLK 10 500 100 100 L 50 50 1 1 I
X CSn 11 500 0 100 L 50 50 1 1 I
X PWM 12 500 -300 100 L 50 50 1 1 O
X NC 13 400 -200 100 L 50 50 1 1 N N
X NC 14 100 -400 100 U 50 50 1 1 N N
X VDD3V3 15 -100 500 100 D 50 50 1 1 W
X VDD5V 16 0 500 100 D 50 50 1 1 W
X MagDECn 2 -500 -300 100 R 50 50 1 1 C
X A 3 -500 300 100 R 50 50 1 1 O
X B 4 -500 200 100 R 50 50 1 1 O
X NC 5 400 -100 100 L 50 50 1 1 N N
X I 6 -500 100 100 R 50 50 1 1 O
X VSS 7 0 -500 100 U 50 50 1 1 W
X PDIO 8 500 300 100 L 50 50 1 1 I
X DO 9 500 200 100 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# _Library_1_IRL3672
#
DEF _Library_1_IRL3672 DA 0 40 Y Y 1 F N
F0 "DA" -100 675 50 H V C CNN
F1 "_Library_1_IRL3672" 0 -200 50 H V C CNN
F2 "" 0 -200 50 H I C CNN
F3 "" 0 -200 50 H I C CNN
DRAW
C 175 450 146 0 1 0 N
C 175 50 146 1 1 0 N
S -150 625 450 -125 0 1 0 f
P 2 0 1 0 200 450 300 450 N
P 3 0 1 0 -150 400 50 400 50 500 N
P 3 0 1 0 100 400 150 400 150 350 N
P 3 0 1 0 150 400 150 450 100 450 N
P 3 0 1 0 400 500 400 400 450 400 N
P 4 0 1 0 100 450 125 475 125 425 100 450 N
P 4 0 1 0 250 450 200 400 300 400 250 450 N
P 5 0 1 0 -150 500 -50 500 -50 350 250 350 250 450 N
P 6 0 1 0 100 500 250 500 250 550 400 550 400 500 450 500 N
P 2 1 1 0 200 50 300 50 N
P 3 1 1 0 -150 0 50 0 50 100 N
P 3 1 1 0 100 0 150 0 150 -50 N
P 3 1 1 0 150 0 150 50 100 50 N
P 3 1 1 0 400 100 400 0 450 0 N
P 4 1 1 0 100 50 125 75 125 25 100 50 N
P 4 1 1 0 250 50 200 0 300 0 250 50 N
P 5 1 1 0 -150 100 -50 100 -50 -50 250 -50 250 50 N
P 6 1 1 0 100 100 250 100 250 150 400 150 400 100 450 100 N
X S2 1 -250 500 100 R 50 50 1 1 W
X G2 2 -250 400 100 R 50 50 1 1 I
X S1 3 -250 100 100 R 50 50 1 1 W
X G1 4 -250 0 100 R 50 50 1 1 I
X D1 5 550 0 100 L 50 50 1 1 w
X D1 6 550 100 100 L 50 50 1 1 w
X D2 7 550 400 100 L 50 50 1 1 w
X D2 8 550 500 100 L 50 50 1 1 w
ENDDRAW
ENDDEF
#
# _Library_1_ir2136
#
DEF _Library_1_ir2136 DA 0 40 Y Y 1 F N
F0 "DA" -100 100 50 H V C CNN
F1 "_Library_1_ir2136" 0 -1500 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -150 50 800 -1450 0 1 0 f
X vcc 1 -250 -50 100 R 50 50 1 1 W
X EN 10 -250 -950 100 R 50 50 1 1 I
X RCIN 11 -250 -1050 100 R 50 50 1 1 O
X GND 12 -250 -1150 100 R 50 50 1 1 W
X COM 13 -250 -1250 100 R 50 50 1 1 O
X LO3 14 -250 -1350 100 R 50 50 1 1 I
X LO2 15 900 -1350 100 L 50 50 1 1 I
X LO1 16 900 -1250 100 L 50 50 1 1 I
X NC 17 900 -1150 100 L 50 50 1 1 N
X VS3 18 900 -1050 100 L 50 50 1 1 O
X HO3 19 900 -950 100 L 50 50 1 1 O
X HIN1 2 -250 -150 100 R 50 50 1 1 I I
X VB3 20 900 -850 100 L 50 50 1 1 O
X NC 21 900 -750 100 L 50 50 1 1 N
X VS2 22 900 -650 100 L 50 50 1 1 O
X HO2 23 900 -550 100 L 50 50 1 1 O
X VB2 24 900 -450 100 L 50 50 1 1 O
X NC 25 900 -350 100 L 50 50 1 1 N
X VS1 26 900 -250 100 L 50 50 1 1 O
X HO1 27 900 -150 100 L 50 50 1 1 O
X VB1 28 900 -50 100 L 50 50 1 1 O
X HIN2 3 -250 -250 100 R 50 50 1 1 I I
X HIN3 4 -250 -350 100 R 50 50 1 1 I I
X LIN1 5 -250 -450 100 R 50 50 1 1 I I
X LIN2 6 -250 -550 100 R 50 50 1 1 I I
X LIN3 7 -250 -650 100 R 50 50 1 1 I I
X FAULT 8 -250 -750 100 R 50 50 1 1 O I
X ITRIP 9 -250 -850 100 R 50 50 1 1 O
ENDDRAW
ENDDEF
#
# kicad_Library_PROGRAMMATOR
#
DEF kicad_Library_PROGRAMMATOR xp 0 40 Y Y 1 F N
F0 "xp" -350 900 50 H V C CNN
F1 "kicad_Library_PROGRAMMATOR" -400 200 50 H V C CNN
F2 "Connector_IDC:IDC-Header_2x05_P2.54mm_Vertical" -350 900 50 H I C CNN
F3 "" -350 900 50 H I C CNN
DRAW
S -700 800 50 300 0 1 0 f
X GND 1 -800 750 100 R 50 50 1 1 P
X +5V 10 150 350 100 L 50 50 1 1 w
X +3V 2 150 750 100 L 50 50 1 1 w
X RESET 3 -800 650 100 R 50 50 1 1 I
X BOOT 4 150 650 100 L 50 50 1 1 I
X RX 5 -800 550 100 R 50 50 1 1 I
X TX 6 150 550 100 L 50 50 1 1 O
X SWDCLK 7 -800 450 100 R 50 50 1 1 I
X SWDDTA 8 150 450 100 L 50 50 1 1 B
X GND 9 -800 350 100 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# motor_controller_220520-cache_LM2594HVM-12
#
DEF motor_controller_220520-cache_LM2594HVM-12 U 0 20 Y Y 1 F N
F0 "U" -300 250 50 H V L CNN
F1 "motor_controller_220520-cache_LM2594HVM-12" 0 250 50 H V L CNN
F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 200 -250 50 H I L CIN
F3 "" 0 100 50 H I C CNN
$FPLIST
SOIC*3.9x4.9mm*
$ENDFPLIST
DRAW
S -300 200 300 -200 0 1 10 f
X NC 1 -200 -300 100 U 50 50 1 1 P
X NC 2 -100 -300 100 U 50 50 1 1 P
X NC 3 0 -300 100 U 50 50 1 1 P
X FB 4 400 100 100 L 50 50 1 1 I
X ~ON~/OFF 5 -400 0 100 R 50 50 1 1 I
X GND 6 200 -300 100 U 50 50 1 1 W
X VIN 7 -400 100 100 R 50 50 1 1 W
X OUT 8 400 0 100 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# motor_controller_220520-cache_LM2594HVM-5.0
#
DEF motor_controller_220520-cache_LM2594HVM-5.0 U 0 20 Y Y 1 F N
F0 "U" -300 250 50 H V L CNN
F1 "motor_controller_220520-cache_LM2594HVM-5.0" 0 250 50 H V L CNN
F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 200 -250 50 H I L CIN
F3 "" 0 100 50 H I C CNN
ALIAS LM2594M-5.0 LM2594M-12 LM2594M-ADJ LM2594HVM-3.3 LM2594HVM-5.0 LM2594HVM-12 LM2594HVM-ADJ
$FPLIST
SOIC*3.9x4.9mm*
$ENDFPLIST
DRAW
S -300 200 300 -200 0 1 10 f
X NC 1 -200 -300 100 U 50 50 1 1 P
X NC 2 -100 -300 100 U 50 50 1 1 P
X NC 3 0 -300 100 U 50 50 1 1 P
X FB 4 400 100 100 L 50 50 1 1 I
X ~ON~/OFF 5 -400 0 100 R 50 50 1 1 I
X GND 6 200 -300 100 U 50 50 1 1 W
X VIN 7 -400 100 100 R 50 50 1 1 W
X OUT 8 400 0 100 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# power_+12C
#
DEF power_+12C #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+12C" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +12C 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+24V
#
DEF power_+24V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+24V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +24V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+3.3V
#
DEF power_+3.3V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3.3V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+3.3VADC
#
DEF power_+3.3VADC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 150 -50 50 H I C CNN
F1 "power_+3.3VADC" 0 100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3.3VADC 1 0 0 0 U 50 50 0 0 W N
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_-24V
#
DEF power_-24V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 100 50 H I C CNN
F1 "power_-24V" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F
X -24V 1 0 0 0 U 50 50 0 0 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# pspice_DIODE
#
DEF pspice_DIODE D 0 40 Y N 1 F N
F0 "D" 0 150 50 H V C CNN
F1 "pspice_DIODE" 0 -175 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 75 100 75 -100 N
P 3 0 1 0 -75 100 -75 -100 75 0 F
X K 1 -200 0 150 R 50 50 1 1 I
X A 2 200 0 150 L 50 50 1 1 I
ENDDRAW
ENDDEF
#
#End Library

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(kicad_pcb (version 4) (host kicad "dummy file") )

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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_Generic_Conn_02x05_Counter_Clockwise
#
DEF Connector_Generic_Conn_02x05_Counter_Clockwise J 0 40 Y N 1 F N
F0 "J" 50 300 50 H V C CNN
F1 "Connector_Generic_Conn_02x05_Counter_Clockwise" 50 -300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 250 150 -250 1 1 10 f
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
X Pin_1 1 -200 200 150 R 50 50 1 1 P
X Pin_10 10 300 200 150 L 50 50 1 1 P
X Pin_2 2 -200 100 150 R 50 50 1 1 P
X Pin_3 3 -200 0 150 R 50 50 1 1 P
X Pin_4 4 -200 -100 150 R 50 50 1 1 P
X Pin_5 5 -200 -200 150 R 50 50 1 1 P
X Pin_6 6 300 -200 150 L 50 50 1 1 P
X Pin_7 7 300 -100 150 L 50 50 1 1 P
X Pin_8 8 300 0 150 L 50 50 1 1 P
X Pin_9 9 300 100 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_02x08_Odd_Even
#
DEF Connector_Generic_Conn_02x08_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 400 50 H V C CNN
F1 "Connector_Generic_Conn_02x08_Odd_Even" 50 -500 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 350 150 -450 1 1 10 f
S 150 -395 100 -405 1 1 6 N
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
X Pin_1 1 -200 300 150 R 50 50 1 1 P
X Pin_10 10 300 -100 150 L 50 50 1 1 P
X Pin_11 11 -200 -200 150 R 50 50 1 1 P
X Pin_12 12 300 -200 150 L 50 50 1 1 P
X Pin_13 13 -200 -300 150 R 50 50 1 1 P
X Pin_14 14 300 -300 150 L 50 50 1 1 P
X Pin_15 15 -200 -400 150 R 50 50 1 1 P
X Pin_16 16 300 -400 150 L 50 50 1 1 P
X Pin_2 2 300 300 150 L 50 50 1 1 P
X Pin_3 3 -200 200 150 R 50 50 1 1 P
X Pin_4 4 300 200 150 L 50 50 1 1 P
X Pin_5 5 -200 100 150 R 50 50 1 1 P
X Pin_6 6 300 100 150 L 50 50 1 1 P
X Pin_7 7 -200 0 150 R 50 50 1 1 P
X Pin_8 8 300 0 150 L 50 50 1 1 P
X Pin_9 9 -200 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C_Small
#
DEF Device_C_Small C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "Device_C_Small" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 13 -60 -20 60 -20 N
P 2 0 1 12 -60 20 60 20 N
X ~ 1 0 100 80 D 50 50 1 1 P
X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Crystal
#
DEF Device_Crystal Y 0 40 N N 1 F N
F0 "Y" 0 150 50 H V C CNN
F1 "Device_Crystal" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Crystal*
$ENDFPLIST
DRAW
S -45 100 45 -100 0 1 12 N
P 2 0 1 0 -100 0 -75 0 N
P 2 0 1 20 -75 -50 -75 50 N
P 2 0 1 20 75 -50 75 50 N
P 2 0 1 0 100 0 75 0 N
X 1 1 -150 0 50 R 50 50 1 1 P
X 2 2 150 0 50 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_L
#
DEF Device_L L 0 40 N N 1 F N
F0 "L" -50 0 50 V V C CNN
F1 "Device_L" 75 0 50 V V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Choke_*
*Coil*
Inductor_*
L_*
$ENDFPLIST
DRAW
A 0 -75 25 -899 899 0 1 0 N 0 -100 0 -50
A 0 -25 25 -899 899 0 1 0 N 0 -50 0 0
A 0 25 25 -899 899 0 1 0 N 0 0 0 50
A 0 75 25 -899 899 0 1 0 N 0 50 0 100
X 1 1 0 150 50 D 50 50 1 1 P
X 2 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_LED
#
DEF Device_LED D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "Device_LED" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
LED*
LED_SMD:*
LED_THT:*
$ENDFPLIST
DRAW
P 2 0 1 10 -50 -50 -50 50 N
P 2 0 1 0 -50 0 50 0 N
P 4 0 1 10 50 -50 50 50 -50 0 50 -50 N
P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Diode_1N5818
#
DEF Diode_1N5818 D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "Diode_1N5818" 0 -100 50 H V C CNN
F2 "Diode_THT:D_DO-41_SOD81_P10.16mm_Horizontal" 0 -175 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS SB130 SB140 SB150 SB160 1N5817 1N5818 1N5819
$FPLIST
D*DO?41*
$ENDFPLIST
DRAW
P 2 0 1 0 50 0 -50 0 N
P 4 0 1 10 50 50 50 -50 -50 0 50 50 N
P 6 0 1 10 -75 25 -75 50 -50 50 -50 -50 -25 -50 -25 -25 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Driver_FET_LM5109AMA
#
DEF Driver_FET_LM5109AMA U 0 20 Y Y 1 F N
F0 "U" 0 550 50 H V C CNN
F1 "Driver_FET_LM5109AMA" 0 450 50 H V C CNN
F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 -500 50 H I C CIN
F3 "" 0 0 50 H I C CNN
ALIAS LM5109AMA LM5109BMA
$FPLIST
SOIC*3.9x4.9mm*P1.27mm*
$ENDFPLIST
DRAW
S -200 -400 200 400 0 1 10 f
X VDD 1 -300 300 100 R 50 50 1 1 W
X HI 2 -300 -100 100 R 50 50 1 1 I
X LI 3 -300 -200 100 R 50 50 1 1 I
X VSS 4 -300 -300 100 R 50 50 1 1 W
X LO 5 300 -300 100 L 50 50 1 1 O
X HS 6 300 -200 100 L 50 50 1 1 P
X HO 7 300 -100 100 L 50 50 1 1 O
X HB 8 300 300 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Interface_CAN_LIN_MCP2551-I-SN
#
DEF Interface_CAN_LIN_MCP2551-I-SN U 0 40 Y Y 1 F N
F0 "U" -400 350 50 H V L CNN
F1 "Interface_CAN_LIN_MCP2551-I-SN" 100 350 50 H V L CNN
F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 0 -500 50 H I C CIN
F3 "" 0 0 50 H I C CNN
$FPLIST
SOIC*3.9x4.9mm*P1.27mm*
$ENDFPLIST
DRAW
S -400 300 400 -300 0 1 10 f
X TXD 1 -500 200 100 R 50 50 1 1 I
X VSS 2 0 -400 100 U 50 50 1 1 W
X VDD 3 0 400 100 D 50 50 1 1 W
X RXD 4 -500 100 100 R 50 50 1 1 O
X Vref 5 -500 -100 100 R 50 50 1 1 w
X CANL 6 500 -100 100 L 50 50 1 1 B
X CANH 7 500 100 100 L 50 50 1 1 B
X Rs 8 -500 -200 100 R 50 50 1 1 I
ENDDRAW
ENDDEF
#
# MCU_ST_STM32F4_STM32F446RETx
#
DEF MCU_ST_STM32F4_STM32F446RETx U 0 20 Y Y 1 F N
F0 "U" -600 1650 50 H V L CNN
F1 "MCU_ST_STM32F4_STM32F446RETx" 400 1650 50 H V L CNN
F2 "Package_QFP:LQFP-64_10x10mm_P0.5mm" -600 -1700 50 H I R CNN
F3 "" 0 0 50 H I C CNN
ALIAS STM32F446RETx
$FPLIST
LQFP*10x10mm*P0.5mm*
$ENDFPLIST
DRAW
S -600 -1700 600 1600 0 1 10 f
X VBAT 1 -200 1700 100 D 50 50 1 1 W
X PC2 10 -700 -300 100 R 50 50 1 1 B
X PC3 11 -700 -400 100 R 50 50 1 1 B
X VSSA 12 200 -1800 100 U 50 50 1 1 W
X VDDA 13 300 1700 100 D 50 50 1 1 W
X PA0 14 700 1500 100 L 50 50 1 1 B
X PA1 15 700 1400 100 L 50 50 1 1 B
X PA2 16 700 1300 100 L 50 50 1 1 B
X PA3 17 700 1200 100 L 50 50 1 1 B
X VSS 18 -200 -1800 100 U 50 50 1 1 W
X VDD 19 -100 1700 100 D 50 50 1 1 W
X PC13 2 -700 -1400 100 R 50 50 1 1 B
X PA4 20 700 1100 100 L 50 50 1 1 B
X PA5 21 700 1000 100 L 50 50 1 1 B
X PA6 22 700 900 100 L 50 50 1 1 B
X PA7 23 700 800 100 L 50 50 1 1 B
X PC4 24 -700 -500 100 R 50 50 1 1 B
X PC5 25 -700 -600 100 R 50 50 1 1 B
X PB0 26 700 -200 100 L 50 50 1 1 B
X PB1 27 700 -300 100 L 50 50 1 1 B
X PB2 28 700 -400 100 L 50 50 1 1 B
X PB10 29 700 -1200 100 L 50 50 1 1 B
X PC14 3 -700 -1500 100 R 50 50 1 1 B
X VCAP_1 30 -700 1100 100 R 50 50 1 1 W
X VSS 31 -100 -1800 100 U 50 50 1 1 W
X VDD 32 0 1700 100 D 50 50 1 1 W
X PB12 33 700 -1300 100 L 50 50 1 1 B
X PB13 34 700 -1400 100 L 50 50 1 1 B
X PB14 35 700 -1500 100 L 50 50 1 1 B
X PB15 36 700 -1600 100 L 50 50 1 1 B
X PC6 37 -700 -700 100 R 50 50 1 1 B
X PC7 38 -700 -800 100 R 50 50 1 1 B
X PC8 39 -700 -900 100 R 50 50 1 1 B
X PC15 4 -700 -1600 100 R 50 50 1 1 B
X PC9 40 -700 -1000 100 R 50 50 1 1 B
X PA8 41 700 700 100 L 50 50 1 1 B
X PA9 42 700 600 100 L 50 50 1 1 B
X PA10 43 700 500 100 L 50 50 1 1 B
X PA11 44 700 400 100 L 50 50 1 1 B
X PA12 45 700 300 100 L 50 50 1 1 B
X PA13 46 700 200 100 L 50 50 1 1 B
X VSS 47 0 -1800 100 U 50 50 1 1 W
X VDD 48 100 1700 100 D 50 50 1 1 W
X PA14 49 700 100 100 L 50 50 1 1 B
X PH0 5 -700 400 100 R 50 50 1 1 I
X PA15 50 700 0 100 L 50 50 1 1 B
X PC10 51 -700 -1100 100 R 50 50 1 1 B
X PC11 52 -700 -1200 100 R 50 50 1 1 B
X PC12 53 -700 -1300 100 R 50 50 1 1 B
X PD2 54 -700 100 100 R 50 50 1 1 B
X PB3 55 700 -500 100 L 50 50 1 1 B
X PB4 56 700 -600 100 L 50 50 1 1 B
X PB5 57 700 -700 100 L 50 50 1 1 B
X PB6 58 700 -800 100 L 50 50 1 1 B
X PB7 59 700 -900 100 L 50 50 1 1 B
X PH1 6 -700 300 100 R 50 50 1 1 I
X BOOT0 60 -700 1300 100 R 50 50 1 1 I
X PB8 61 700 -1000 100 L 50 50 1 1 B
X PB9 62 700 -1100 100 L 50 50 1 1 B
X VSS 63 100 -1800 100 U 50 50 1 1 W
X VDD 64 200 1700 100 D 50 50 1 1 W
X NRST 7 -700 1500 100 R 50 50 1 1 I
X PC0 8 -700 -100 100 R 50 50 1 1 B
X PC1 9 -700 -200 100 R 50 50 1 1 B
ENDDRAW
ENDDEF
#
# Regulator_Linear_MIC5219-3.3YM5
#
DEF Regulator_Linear_MIC5219-3.3YM5 U 0 10 Y Y 1 F N
F0 "U" -150 225 50 H V C CNN
F1 "Regulator_Linear_MIC5219-3.3YM5" 0 225 50 H V L CNN
F2 "Package_TO_SOT_SMD:SOT-23-5" 0 325 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS AP131-18 AP131-20 AP131-25 AP131-28 AP131-29 AP131-30 AP131-33 AP131-35 MIC5205-2.5YM5 MIC5205-2.7YM5 MIC5205-2.8YM5 MIC5205-2.85YM5 MIC5205-2.9YM5 MIC5205-3.0YM5 MIC5205-3.1YM5 MIC5205-3.2YM5 MIC5205-3.3YM5 MIC5205-3.6YM5 MIC5205-3.8YM5 MIC5205-4.0YM5 MIC5205-5.0YM5 MIC5219-2.5YM5 MIC5219-2.6YM5 MIC5219-2.7YM5 MIC5219-2.8YM5 MIC5219-2.85YM5 MIC5219-2.9YM5 MIC5219-3.0YM5 MIC5219-3.1YM5 MIC5219-3.3YM5 MIC5219-3.6YM5 MIC5219-5.0YM5 SPX3819M5-L-1-2 SPX3819M5-L-1-5 SPX3819M5-L-1-8 SPX3819M5-L-2-5 SPX3819M5-L-3-0 SPX3819M5-L-3-3 SPX3819M5-L-5-0
$FPLIST
SOT?23*
$ENDFPLIST
DRAW
S -200 175 200 -200 0 1 10 f
X IN 1 -300 100 100 R 50 50 1 1 W
X GND 2 0 -300 100 U 50 50 1 1 W
X EN 3 -300 0 100 R 50 50 1 1 I
X BP 4 300 0 100 L 50 50 1 1 I
X OUT 5 300 100 100 L 50 50 1 1 w
ENDDRAW
ENDDEF
#
# Sensor_Current_ACS712xLCTR-30A
#
DEF Sensor_Current_ACS712xLCTR-30A U 0 20 Y Y 1 F N
F0 "U" 100 450 50 H V L CNN
F1 "Sensor_Current_ACS712xLCTR-30A" 100 350 50 H V L CNN
F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 100 -350 50 H I L CIN
F3 "" 0 0 50 H I C CNN
ALIAS ACS712xLCTR-20A ACS712xLCTR-30A ACS713xLCTR-20A ACS713xLCTR-30A ACS714xLCTR-05B ACS714xLCTR-20A ACS714xLCTR-30A ACS714xLCTR-50A ACS715xLCTR-20A ACS715xLCTR-30A ACS724xLCTR-05AB ACS724xLCTR-10AB ACS724xLCTR-10AU ACS724xLCTR-20AB ACS724xLCTR-20AU ACS724xLCTR-30AB ACS724xLCTR-30AU ACS724xLCTR-50AB ACS725xLCTR-10AU ACS725xLCTR-20AB ACS725xLCTR-20AU ACS725xLCTR-30AB ACS725xLCTR-30AU ACS725xLCTR-40AB ACS725xLCTR-50AB
$FPLIST
SOIC*3.9x4.9m*P1.27mm*
$ENDFPLIST
DRAW
S -300 300 300 -300 0 1 10 f
X IP+ 1 -400 200 100 R 50 50 1 1 P
X IP+ 2 -400 200 100 R 50 50 1 1 P N
X IP- 3 -400 -200 100 R 50 50 1 1 P
X IP- 4 -400 -200 100 R 50 50 1 1 P N
X GND 5 0 -400 100 U 50 50 1 1 W
X FILTER 6 400 -100 100 L 50 50 1 1 P
X VIOUT 7 400 0 100 L 50 50 1 1 O
X VCC 8 0 400 100 D 50 50 1 1 W
ENDDRAW
ENDDEF
#
# Sensor_Magnetic_AS5045B
#
DEF Sensor_Magnetic_AS5045B U 0 20 Y Y 1 F N
F0 "U" -400 450 50 H V L CNN
F1 "Sensor_Magnetic_AS5045B" 450 450 50 H V R CNN
F2 "Package_SO:SSOP-16_5.3x6.2mm_P0.65mm" 150 -450 50 H I L CNN
F3 "" -2150 1600 50 H I C CNN
$FPLIST
SSOP*5.3x6.2mm*P0.65mm*
$ENDFPLIST
DRAW
A 0 0 110 -1799 -1 0 1 10 N -110 0 110 0
C 0 0 80 0 1 10 N
S -400 400 400 -400 0 1 10 f
P 2 0 1 10 -110 0 -130 -20 N
P 2 0 1 10 -110 0 -90 -20 N
P 2 0 1 10 110 0 90 -20 N
P 2 0 1 10 110 0 130 -20 N
P 4 0 1 0 10 10 50 -30 30 -50 -10 -10 N
P 7 0 1 0 -30 50 10 10 -10 -10 -50 30 -40 40 -30 50 -25 45 F
X MagINCn 1 -500 -200 100 R 50 50 1 1 C
X CLK 10 500 100 100 L 50 50 1 1 I
X CSn 11 500 0 100 L 50 50 1 1 I
X PWM 12 500 -300 100 L 50 50 1 1 O
X NC 13 400 -200 100 L 50 50 1 1 N N
X NC 14 100 -400 100 U 50 50 1 1 N N
X VDD3V3 15 -100 500 100 D 50 50 1 1 W
X VDD5V 16 0 500 100 D 50 50 1 1 W
X MagDECn 2 -500 -300 100 R 50 50 1 1 C
X A 3 -500 300 100 R 50 50 1 1 O
X B 4 -500 200 100 R 50 50 1 1 O
X NC 5 400 -100 100 L 50 50 1 1 N N
X I 6 -500 100 100 R 50 50 1 1 O
X VSS 7 0 -500 100 U 50 50 1 1 W
X PDIO 8 500 300 100 L 50 50 1 1 I
X DO 9 500 200 100 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# _Library_1_IRL3672
#
DEF _Library_1_IRL3672 DA 0 40 Y Y 1 F N
F0 "DA" -100 675 50 H V C CNN
F1 "_Library_1_IRL3672" 0 -200 50 H V C CNN
F2 "" 0 -200 50 H I C CNN
F3 "" 0 -200 50 H I C CNN
DRAW
C 175 450 146 0 1 0 N
C 175 50 146 1 1 0 N
S -150 625 450 -125 0 1 0 f
P 2 0 1 0 200 450 300 450 N
P 3 0 1 0 -150 400 50 400 50 500 N
P 3 0 1 0 100 400 150 400 150 350 N
P 3 0 1 0 150 400 150 450 100 450 N
P 3 0 1 0 400 500 400 400 450 400 N
P 4 0 1 0 100 450 125 475 125 425 100 450 N
P 4 0 1 0 250 450 200 400 300 400 250 450 N
P 5 0 1 0 -150 500 -50 500 -50 350 250 350 250 450 N
P 6 0 1 0 100 500 250 500 250 550 400 550 400 500 450 500 N
P 2 1 1 0 200 50 300 50 N
P 3 1 1 0 -150 0 50 0 50 100 N
P 3 1 1 0 100 0 150 0 150 -50 N
P 3 1 1 0 150 0 150 50 100 50 N
P 3 1 1 0 400 100 400 0 450 0 N
P 4 1 1 0 100 50 125 75 125 25 100 50 N
P 4 1 1 0 250 50 200 0 300 0 250 50 N
P 5 1 1 0 -150 100 -50 100 -50 -50 250 -50 250 50 N
P 6 1 1 0 100 100 250 100 250 150 400 150 400 100 450 100 N
X S2 1 -250 500 100 R 50 50 1 1 W
X G2 2 -250 400 100 R 50 50 1 1 I
X S1 3 -250 100 100 R 50 50 1 1 W
X G1 4 -250 0 100 R 50 50 1 1 I
X D1 5 550 0 100 L 50 50 1 1 w
X D1 6 550 100 100 L 50 50 1 1 w
X D2 7 550 400 100 L 50 50 1 1 w
X D2 8 550 500 100 L 50 50 1 1 w
ENDDRAW
ENDDEF
#
# kicad_Library_PROGRAMMATOR
#
DEF kicad_Library_PROGRAMMATOR xp 0 40 Y Y 1 F N
F0 "xp" -350 900 50 H V C CNN
F1 "kicad_Library_PROGRAMMATOR" -400 200 50 H V C CNN
F2 "Connector_IDC:IDC-Header_2x05_P2.54mm_Vertical" -350 900 50 H I C CNN
F3 "" -350 900 50 H I C CNN
DRAW
S -700 800 50 300 0 1 0 f
X GND 1 -800 750 100 R 50 50 1 1 P
X +5V 10 150 350 100 L 50 50 1 1 w
X +3V 2 150 750 100 L 50 50 1 1 w
X RESET 3 -800 650 100 R 50 50 1 1 I
X BOOT 4 150 650 100 L 50 50 1 1 I
X RX 5 -800 550 100 R 50 50 1 1 I
X TX 6 150 550 100 L 50 50 1 1 O
X SWDCLK 7 -800 450 100 R 50 50 1 1 I
X SWDDTA 8 150 450 100 L 50 50 1 1 B
X GND 9 -800 350 100 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# motor_controller_220520-cache_LM2594HVM-12
#
DEF motor_controller_220520-cache_LM2594HVM-12 U 0 20 Y Y 1 F N
F0 "U" -300 250 50 H V L CNN
F1 "motor_controller_220520-cache_LM2594HVM-12" 0 250 50 H V L CNN
F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 200 -250 50 H I L CIN
F3 "" 0 100 50 H I C CNN
$FPLIST
SOIC*3.9x4.9mm*
$ENDFPLIST
DRAW
S -300 200 300 -200 0 1 10 f
X NC 1 -200 -300 100 U 50 50 1 1 P
X NC 2 -100 -300 100 U 50 50 1 1 P
X NC 3 0 -300 100 U 50 50 1 1 P
X FB 4 400 100 100 L 50 50 1 1 I
X ~ON~/OFF 5 -400 0 100 R 50 50 1 1 I
X GND 6 200 -300 100 U 50 50 1 1 W
X VIN 7 -400 100 100 R 50 50 1 1 W
X OUT 8 400 0 100 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# motor_controller_220520-cache_LM2594HVM-5.0
#
DEF motor_controller_220520-cache_LM2594HVM-5.0 U 0 20 Y Y 1 F N
F0 "U" -300 250 50 H V L CNN
F1 "motor_controller_220520-cache_LM2594HVM-5.0" 0 250 50 H V L CNN
F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 200 -250 50 H I L CIN
F3 "" 0 100 50 H I C CNN
ALIAS LM2594M-5.0 LM2594M-12 LM2594M-ADJ LM2594HVM-3.3 LM2594HVM-5.0 LM2594HVM-12 LM2594HVM-ADJ
$FPLIST
SOIC*3.9x4.9mm*
$ENDFPLIST
DRAW
S -300 200 300 -200 0 1 10 f
X NC 1 -200 -300 100 U 50 50 1 1 P
X NC 2 -100 -300 100 U 50 50 1 1 P
X NC 3 0 -300 100 U 50 50 1 1 P
X FB 4 400 100 100 L 50 50 1 1 I
X ~ON~/OFF 5 -400 0 100 R 50 50 1 1 I
X GND 6 200 -300 100 U 50 50 1 1 W
X VIN 7 -400 100 100 R 50 50 1 1 W
X OUT 8 400 0 100 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# power_+12C
#
DEF power_+12C #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+12C" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +12C 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+24V
#
DEF power_+24V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+24V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +24V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+3.3V
#
DEF power_+3.3V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3.3V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_-24V
#
DEF power_-24V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 100 50 H I C CNN
F1 "power_-24V" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 50 30 50 0 100 -30 50 0 50 F
X -24V 1 0 0 0 U 50 50 0 0 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# pspice_DIODE
#
DEF pspice_DIODE D 0 40 Y N 1 F N
F0 "D" 0 150 50 H V C CNN
F1 "pspice_DIODE" 0 -175 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 75 100 75 -100 N
P 3 0 1 0 -75 100 -75 -100 75 0 F
X K 1 -200 0 150 R 50 50 1 1 I
X A 2 200 0 150 L 50 50 1 1 I
ENDDRAW
ENDDEF
#
#End Library

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brd/MotorModule/motor_controller_220527.pdf Normal file
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brd/MotorModule/motor_controller_220527.pro Normal file
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@ -0,0 +1,33 @@
update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]

4210
brd/MotorModule/motor_controller_220527.sch Normal file
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brd/MotorModule/motor_controller_220527.sch-bak Normal file
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924
brd/MotorModule/motor_module-cache.lib Normal file
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Amplifier_Operational_MCP6004
#
DEF Amplifier_Operational_MCP6004 U 0 5 Y Y 5 L N
F0 "U" 0 200 50 H V L CNN
F1 "Amplifier_Operational_MCP6004" 0 -200 50 H V L CNN
F2 "" -50 100 50 H I C CNN
F3 "" 50 200 50 H I C CNN
ALIAS LM324 TLC274 TLC279 TL074 LM324A MCP6004 TL084 TL064 LMV324 LMC6484 MCP604 MC33079 MC33174 MC33179 OPA1604 OPA1679 OPA4134 OPA4340UA OPA4376 MCP6L94 TSV914 ADA4807-4 TSV994
$FPLIST
SOIC*3.9x8.7mm*P1.27mm*
DIP*W7.62mm*
TSSOP*4.4x5mm*P0.65mm*
SSOP*5.3x6.2mm*P0.65mm*
MSOP*3x3mm*P0.5mm*
$ENDFPLIST
DRAW
P 4 1 1 10 -200 200 200 0 -200 -200 -200 200 f
P 4 2 1 10 -200 200 200 0 -200 -200 -200 200 f
P 4 3 1 10 -200 200 200 0 -200 -200 -200 200 f
P 4 4 1 10 -200 200 200 0 -200 -200 -200 200 f
X ~ 1 300 0 100 L 50 50 1 1 O
X - 2 -300 -100 100 R 50 50 1 1 I
X + 3 -300 100 100 R 50 50 1 1 I
X + 5 -300 100 100 R 50 50 2 1 I
X - 6 -300 -100 100 R 50 50 2 1 I
X ~ 7 300 0 100 L 50 50 2 1 O
X + 10 -300 100 100 R 50 50 3 1 I
X ~ 8 300 0 100 L 50 50 3 1 O
X - 9 -300 -100 100 R 50 50 3 1 I
X + 12 -300 100 100 R 50 50 4 1 I
X - 13 -300 -100 100 R 50 50 4 1 I
X ~ 14 300 0 100 L 50 50 4 1 O
X V- 11 -100 -300 150 U 50 50 5 1 W
X V+ 4 -100 300 150 D 50 50 5 1 W
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_01x03
#
DEF Connector_Generic_Conn_01x03 J 0 40 Y N 1 F N
F0 "J" 0 200 50 H V C CNN
F1 "Connector_Generic_Conn_01x03" 0 -200 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_1x??_*
$ENDFPLIST
DRAW
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 150 50 -150 1 1 10 f
X Pin_1 1 -200 100 150 R 50 50 1 1 P
X Pin_2 2 -200 0 150 R 50 50 1 1 P
X Pin_3 3 -200 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_02x05_Counter_Clockwise
#
DEF Connector_Generic_Conn_02x05_Counter_Clockwise J 0 40 Y N 1 F N
F0 "J" 50 300 50 H V C CNN
F1 "Connector_Generic_Conn_02x05_Counter_Clockwise" 50 -300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 250 150 -250 1 1 10 f
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
X Pin_1 1 -200 200 150 R 50 50 1 1 P
X Pin_10 10 300 200 150 L 50 50 1 1 P
X Pin_2 2 -200 100 150 R 50 50 1 1 P
X Pin_3 3 -200 0 150 R 50 50 1 1 P
X Pin_4 4 -200 -100 150 R 50 50 1 1 P
X Pin_5 5 -200 -200 150 R 50 50 1 1 P
X Pin_6 6 300 -200 150 L 50 50 1 1 P
X Pin_7 7 300 -100 150 L 50 50 1 1 P
X Pin_8 8 300 0 150 L 50 50 1 1 P
X Pin_9 9 300 100 150 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_02x08_Odd_Even
#
DEF Connector_Generic_Conn_02x08_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 400 50 H V C CNN
F1 "Connector_Generic_Conn_02x08_Odd_Even" 50 -500 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 350 150 -450 1 1 10 f
S 150 -395 100 -405 1 1 6 N
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
X Pin_1 1 -200 300 150 R 50 50 1 1 P
X Pin_10 10 300 -100 150 L 50 50 1 1 P
X Pin_11 11 -200 -200 150 R 50 50 1 1 P
X Pin_12 12 300 -200 150 L 50 50 1 1 P
X Pin_13 13 -200 -300 150 R 50 50 1 1 P
X Pin_14 14 300 -300 150 L 50 50 1 1 P
X Pin_15 15 -200 -400 150 R 50 50 1 1 P
X Pin_16 16 300 -400 150 L 50 50 1 1 P
X Pin_2 2 300 300 150 L 50 50 1 1 P
X Pin_3 3 -200 200 150 R 50 50 1 1 P
X Pin_4 4 300 200 150 L 50 50 1 1 P
X Pin_5 5 -200 100 150 R 50 50 1 1 P
X Pin_6 6 300 100 150 L 50 50 1 1 P
X Pin_7 7 -200 0 150 R 50 50 1 1 P
X Pin_8 8 300 0 150 L 50 50 1 1 P
X Pin_9 9 -200 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_02x12_Odd_Even
#
DEF Connector_Generic_Conn_02x12_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 600 50 H V C CNN
F1 "Connector_Generic_Conn_02x12_Odd_Even" 50 -700 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -595 0 -605 1 1 6 N
S -50 -495 0 -505 1 1 6 N
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 405 0 395 1 1 6 N
S -50 505 0 495 1 1 6 N
S -50 550 150 -650 1 1 10 f
S 150 -595 100 -605 1 1 6 N
S 150 -495 100 -505 1 1 6 N
S 150 -395 100 -405 1 1 6 N
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
S 150 405 100 395 1 1 6 N
S 150 505 100 495 1 1 6 N
X Pin_1 1 -200 500 150 R 50 50 1 1 P
X Pin_10 10 300 100 150 L 50 50 1 1 P
X Pin_11 11 -200 0 150 R 50 50 1 1 P
X Pin_12 12 300 0 150 L 50 50 1 1 P
X Pin_13 13 -200 -100 150 R 50 50 1 1 P
X Pin_14 14 300 -100 150 L 50 50 1 1 P
X Pin_15 15 -200 -200 150 R 50 50 1 1 P
X Pin_16 16 300 -200 150 L 50 50 1 1 P
X Pin_17 17 -200 -300 150 R 50 50 1 1 P
X Pin_18 18 300 -300 150 L 50 50 1 1 P
X Pin_19 19 -200 -400 150 R 50 50 1 1 P
X Pin_2 2 300 500 150 L 50 50 1 1 P
X Pin_20 20 300 -400 150 L 50 50 1 1 P
X Pin_21 21 -200 -500 150 R 50 50 1 1 P
X Pin_22 22 300 -500 150 L 50 50 1 1 P
X Pin_23 23 -200 -600 150 R 50 50 1 1 P
X Pin_24 24 300 -600 150 L 50 50 1 1 P
X Pin_3 3 -200 400 150 R 50 50 1 1 P
X Pin_4 4 300 400 150 L 50 50 1 1 P
X Pin_5 5 -200 300 150 R 50 50 1 1 P
X Pin_6 6 300 300 150 L 50 50 1 1 P
X Pin_7 7 -200 200 150 R 50 50 1 1 P
X Pin_8 8 300 200 150 L 50 50 1 1 P
X Pin_9 9 -200 100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_02x20_Odd_Even
#
DEF Connector_Generic_Conn_02x20_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 1000 50 H V C CNN
F1 "Connector_Generic_Conn_02x20_Odd_Even" 50 -1100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -995 0 -1005 1 1 6 N
S -50 -895 0 -905 1 1 6 N
S -50 -795 0 -805 1 1 6 N
S -50 -695 0 -705 1 1 6 N
S -50 -595 0 -605 1 1 6 N
S -50 -495 0 -505 1 1 6 N
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 405 0 395 1 1 6 N
S -50 505 0 495 1 1 6 N
S -50 605 0 595 1 1 6 N
S -50 705 0 695 1 1 6 N
S -50 805 0 795 1 1 6 N
S -50 905 0 895 1 1 6 N
S -50 950 150 -1050 1 1 10 f
S 150 -995 100 -1005 1 1 6 N
S 150 -895 100 -905 1 1 6 N
S 150 -795 100 -805 1 1 6 N
S 150 -695 100 -705 1 1 6 N
S 150 -595 100 -605 1 1 6 N
S 150 -495 100 -505 1 1 6 N
S 150 -395 100 -405 1 1 6 N
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
S 150 405 100 395 1 1 6 N
S 150 505 100 495 1 1 6 N
S 150 605 100 595 1 1 6 N
S 150 705 100 695 1 1 6 N
S 150 805 100 795 1 1 6 N
S 150 905 100 895 1 1 6 N
X Pin_1 1 -200 900 150 R 50 50 1 1 P
X Pin_10 10 300 500 150 L 50 50 1 1 P
X Pin_11 11 -200 400 150 R 50 50 1 1 P
X Pin_12 12 300 400 150 L 50 50 1 1 P
X Pin_13 13 -200 300 150 R 50 50 1 1 P
X Pin_14 14 300 300 150 L 50 50 1 1 P
X Pin_15 15 -200 200 150 R 50 50 1 1 P
X Pin_16 16 300 200 150 L 50 50 1 1 P
X Pin_17 17 -200 100 150 R 50 50 1 1 P
X Pin_18 18 300 100 150 L 50 50 1 1 P
X Pin_19 19 -200 0 150 R 50 50 1 1 P
X Pin_2 2 300 900 150 L 50 50 1 1 P
X Pin_20 20 300 0 150 L 50 50 1 1 P
X Pin_21 21 -200 -100 150 R 50 50 1 1 P
X Pin_22 22 300 -100 150 L 50 50 1 1 P
X Pin_23 23 -200 -200 150 R 50 50 1 1 P
X Pin_24 24 300 -200 150 L 50 50 1 1 P
X Pin_25 25 -200 -300 150 R 50 50 1 1 P
X Pin_26 26 300 -300 150 L 50 50 1 1 P
X Pin_27 27 -200 -400 150 R 50 50 1 1 P
X Pin_28 28 300 -400 150 L 50 50 1 1 P
X Pin_29 29 -200 -500 150 R 50 50 1 1 P
X Pin_3 3 -200 800 150 R 50 50 1 1 P
X Pin_30 30 300 -500 150 L 50 50 1 1 P
X Pin_31 31 -200 -600 150 R 50 50 1 1 P
X Pin_32 32 300 -600 150 L 50 50 1 1 P
X Pin_33 33 -200 -700 150 R 50 50 1 1 P
X Pin_34 34 300 -700 150 L 50 50 1 1 P
X Pin_35 35 -200 -800 150 R 50 50 1 1 P
X Pin_36 36 300 -800 150 L 50 50 1 1 P
X Pin_37 37 -200 -900 150 R 50 50 1 1 P
X Pin_38 38 300 -900 150 L 50 50 1 1 P
X Pin_39 39 -200 -1000 150 R 50 50 1 1 P
X Pin_4 4 300 800 150 L 50 50 1 1 P
X Pin_40 40 300 -1000 150 L 50 50 1 1 P
X Pin_5 5 -200 700 150 R 50 50 1 1 P
X Pin_6 6 300 700 150 L 50 50 1 1 P
X Pin_7 7 -200 600 150 R 50 50 1 1 P
X Pin_8 8 300 600 150 L 50 50 1 1 P
X Pin_9 9 -200 500 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_02x25_Odd_Even
#
DEF Connector_Generic_Conn_02x25_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 1300 50 H V C CNN
F1 "Connector_Generic_Conn_02x25_Odd_Even" 50 -1300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -1195 0 -1205 1 1 6 N
S -50 -1095 0 -1105 1 1 6 N
S -50 -995 0 -1005 1 1 6 N
S -50 -895 0 -905 1 1 6 N
S -50 -795 0 -805 1 1 6 N
S -50 -695 0 -705 1 1 6 N
S -50 -595 0 -605 1 1 6 N
S -50 -495 0 -505 1 1 6 N
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 405 0 395 1 1 6 N
S -50 505 0 495 1 1 6 N
S -50 605 0 595 1 1 6 N
S -50 705 0 695 1 1 6 N
S -50 805 0 795 1 1 6 N
S -50 905 0 895 1 1 6 N
S -50 1005 0 995 1 1 6 N
S -50 1105 0 1095 1 1 6 N
S -50 1205 0 1195 1 1 6 N
S -50 1250 150 -1250 1 1 10 f
S 150 -1195 100 -1205 1 1 6 N
S 150 -1095 100 -1105 1 1 6 N
S 150 -995 100 -1005 1 1 6 N
S 150 -895 100 -905 1 1 6 N
S 150 -795 100 -805 1 1 6 N
S 150 -695 100 -705 1 1 6 N
S 150 -595 100 -605 1 1 6 N
S 150 -495 100 -505 1 1 6 N
S 150 -395 100 -405 1 1 6 N
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
S 150 405 100 395 1 1 6 N
S 150 505 100 495 1 1 6 N
S 150 605 100 595 1 1 6 N
S 150 705 100 695 1 1 6 N
S 150 805 100 795 1 1 6 N
S 150 905 100 895 1 1 6 N
S 150 1005 100 995 1 1 6 N
S 150 1105 100 1095 1 1 6 N
S 150 1205 100 1195 1 1 6 N
X Pin_1 1 -200 1200 150 R 50 50 1 1 P
X Pin_10 10 300 800 150 L 50 50 1 1 P
X Pin_11 11 -200 700 150 R 50 50 1 1 P
X Pin_12 12 300 700 150 L 50 50 1 1 P
X Pin_13 13 -200 600 150 R 50 50 1 1 P
X Pin_14 14 300 600 150 L 50 50 1 1 P
X Pin_15 15 -200 500 150 R 50 50 1 1 P
X Pin_16 16 300 500 150 L 50 50 1 1 P
X Pin_17 17 -200 400 150 R 50 50 1 1 P
X Pin_18 18 300 400 150 L 50 50 1 1 P
X Pin_19 19 -200 300 150 R 50 50 1 1 P
X Pin_2 2 300 1200 150 L 50 50 1 1 P
X Pin_20 20 300 300 150 L 50 50 1 1 P
X Pin_21 21 -200 200 150 R 50 50 1 1 P
X Pin_22 22 300 200 150 L 50 50 1 1 P
X Pin_23 23 -200 100 150 R 50 50 1 1 P
X Pin_24 24 300 100 150 L 50 50 1 1 P
X Pin_25 25 -200 0 150 R 50 50 1 1 P
X Pin_26 26 300 0 150 L 50 50 1 1 P
X Pin_27 27 -200 -100 150 R 50 50 1 1 P
X Pin_28 28 300 -100 150 L 50 50 1 1 P
X Pin_29 29 -200 -200 150 R 50 50 1 1 P
X Pin_3 3 -200 1100 150 R 50 50 1 1 P
X Pin_30 30 300 -200 150 L 50 50 1 1 P
X Pin_31 31 -200 -300 150 R 50 50 1 1 P
X Pin_32 32 300 -300 150 L 50 50 1 1 P
X Pin_33 33 -200 -400 150 R 50 50 1 1 P
X Pin_34 34 300 -400 150 L 50 50 1 1 P
X Pin_35 35 -200 -500 150 R 50 50 1 1 P
X Pin_36 36 300 -500 150 L 50 50 1 1 P
X Pin_37 37 -200 -600 150 R 50 50 1 1 P
X Pin_38 38 300 -600 150 L 50 50 1 1 P
X Pin_39 39 -200 -700 150 R 50 50 1 1 P
X Pin_4 4 300 1100 150 L 50 50 1 1 P
X Pin_40 40 300 -700 150 L 50 50 1 1 P
X Pin_41 41 -200 -800 150 R 50 50 1 1 P
X Pin_42 42 300 -800 150 L 50 50 1 1 P
X Pin_43 43 -200 -900 150 R 50 50 1 1 P
X Pin_44 44 300 -900 150 L 50 50 1 1 P
X Pin_45 45 -200 -1000 150 R 50 50 1 1 P
X Pin_46 46 300 -1000 150 L 50 50 1 1 P
X Pin_47 47 -200 -1100 150 R 50 50 1 1 P
X Pin_48 48 300 -1100 150 L 50 50 1 1 P
X Pin_49 49 -200 -1200 150 R 50 50 1 1 P
X Pin_5 5 -200 1000 150 R 50 50 1 1 P
X Pin_50 50 300 -1200 150 L 50 50 1 1 P
X Pin_6 6 300 1000 150 L 50 50 1 1 P
X Pin_7 7 -200 900 150 R 50 50 1 1 P
X Pin_8 8 300 900 150 L 50 50 1 1 P
X Pin_9 9 -200 800 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_CP
#
DEF Device_CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_CP" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
CP_*
$ENDFPLIST
DRAW
S -90 20 90 40 0 1 0 N
S 90 -20 -90 -40 0 1 0 F
P 2 0 1 0 -70 90 -30 90 N
P 2 0 1 0 -50 110 -50 70 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_CP1
#
DEF Device_CP1 C 0 10 N N 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_CP1" 25 -100 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
CP_*
$ENDFPLIST
DRAW
A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50
P 2 0 1 20 -80 30 80 30 N
P 2 0 1 0 -70 90 -30 90 N
P 2 0 1 0 -50 70 -50 110 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 130 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C_Small
#
DEF Device_C_Small C 0 10 N N 1 F N
F0 "C" 10 70 50 H V L CNN
F1 "Device_C_Small" 10 -80 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 13 -60 -20 60 -20 N
P 2 0 1 12 -60 20 60 20 N
X ~ 1 0 100 80 D 50 50 1 1 P
X ~ 2 0 -100 80 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Crystal
#
DEF Device_Crystal Y 0 40 N N 1 F N
F0 "Y" 0 150 50 H V C CNN
F1 "Device_Crystal" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Crystal*
$ENDFPLIST
DRAW
S -45 100 45 -100 0 1 12 N
P 2 0 1 0 -100 0 -75 0 N
P 2 0 1 20 -75 -50 -75 50 N
P 2 0 1 20 75 -50 75 50 N
P 2 0 1 0 100 0 75 0 N
X 1 1 -150 0 50 R 50 50 1 1 P
X 2 2 150 0 50 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Crystal_GND2_Small
#
DEF Device_Crystal_GND2_Small Y 0 40 Y N 1 F N
F0 "Y" 0 200 50 H V C CNN
F1 "Device_Crystal_GND2_Small" 0 125 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Crystal*
$ENDFPLIST
DRAW
S -30 -60 30 60 0 1 0 N
P 2 0 1 15 -50 -30 -50 30 N
P 2 0 1 15 50 -30 50 30 N
P 4 0 1 0 -50 -50 -50 -75 50 -75 50 -50 N
X 1 1 -100 0 50 R 30 50 1 1 P
X 2 2 0 -100 25 U 30 50 1 1 P
X 3 3 100 0 50 L 30 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_D_Small
#
DEF Device_D_Small D 0 10 N N 1 F N
F0 "D" -50 80 50 H V L CNN
F1 "Device_D_Small" -150 -80 50 H V L CNN
F2 "" 0 0 50 V I C CNN
F3 "" 0 0 50 V I C CNN
$FPLIST
TO-???*
*_Diode_*
*SingleDiode*
D_*
$ENDFPLIST
DRAW
P 2 0 1 10 -30 -40 -30 40 N
P 2 0 1 0 -30 0 30 0 N
P 4 0 1 10 30 -40 -30 0 30 40 30 -40 N
X K 1 -100 0 70 R 50 50 1 1 P
X A 2 100 0 70 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_L
#
DEF Device_L L 0 40 N N 1 F N
F0 "L" -50 0 50 V V C CNN
F1 "Device_L" 75 0 50 V V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Choke_*
*Coil*
Inductor_*
L_*
$ENDFPLIST
DRAW
A 0 -75 25 -899 899 0 1 0 N 0 -100 0 -50
A 0 -25 25 -899 899 0 1 0 N 0 -50 0 0
A 0 25 25 -899 899 0 1 0 N 0 0 0 50
A 0 75 25 -899 899 0 1 0 N 0 50 0 100
X 1 1 0 150 50 D 50 50 1 1 P
X 2 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_LED
#
DEF Device_LED D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "Device_LED" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
LED*
LED_SMD:*
LED_THT:*
$ENDFPLIST
DRAW
P 2 0 1 10 -50 -50 -50 50 N
P 2 0 1 0 -50 0 50 0 N
P 4 0 1 10 50 -50 50 50 -50 0 50 -50 N
P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Interface_UART_MAX485E
#
DEF Interface_UART_MAX485E U 0 20 Y Y 1 F N
F0 "U" -240 450 50 H V C CNN
F1 "Interface_UART_MAX485E" 30 450 50 H V L CNN
F2 "" 0 -700 50 H I C CNN
F3 "" 0 50 50 H I C CNN
ALIAS MAX483E MAX485E MAX487E MAX1487E MAX3485 MAX3483 MAX3486
$FPLIST
DIP*W7.62mm*
SOIC*3.9x4.9mm*P1.27mm*
$ENDFPLIST
DRAW
C -12 -145 14 0 1 10 F
C -1 59 14 0 1 10 F
C 65 75 14 0 1 10 F
S -300 400 300 -500 0 1 10 f
S 50 125 50 125 0 1 0 N
P 2 0 1 10 -160 -200 -75 -200 N
P 2 0 1 10 -160 100 -50 100 N
P 2 0 1 10 -50 -126 -50 -136 N
P 2 0 1 10 -25 -200 210 -200 N
P 3 0 1 10 -160 -100 -50 -100 -50 -125 N
P 3 0 1 10 0 50 0 0 -160 0 N
P 3 0 1 10 50 125 150 125 150 -200 N
P 3 0 1 10 100 75 100 -150 0 -150 N
P 4 0 1 10 -75 -125 -75 -225 25 -175 -75 -125 N
P 4 0 1 10 -50 100 50 150 50 50 -50 100 N
P 4 0 1 10 75 75 175 75 175 100 210 100 N
X RO 1 -400 100 100 R 50 50 1 1 O
X ~RE 2 -400 0 100 R 50 50 1 1 I
X DE 3 -400 -100 100 R 50 50 1 1 I
X DI 4 -400 -200 100 R 50 50 1 1 I
X GND 5 0 -600 100 U 50 50 1 1 W
X A 6 400 -200 100 L 50 50 1 1 B
X B 7 400 100 100 L 50 50 1 1 B
X VCC 8 0 500 100 D 50 50 1 1 W
ENDDRAW
ENDDEF
#
# MCU_ST_STM32F4_STM32F446RETx
#
DEF MCU_ST_STM32F4_STM32F446RETx U 0 20 Y Y 1 F N
F0 "U" -600 1650 50 H V L CNN
F1 "MCU_ST_STM32F4_STM32F446RETx" 400 1650 50 H V L CNN
F2 "Package_QFP:LQFP-64_10x10mm_P0.5mm" -600 -1700 50 H I R CNN
F3 "" 0 0 50 H I C CNN
ALIAS STM32F446RETx
$FPLIST
LQFP*10x10mm*P0.5mm*
$ENDFPLIST
DRAW
S -600 -1700 600 1600 0 1 10 f
X VBAT 1 -200 1700 100 D 50 50 1 1 W
X PC2 10 -700 -300 100 R 50 50 1 1 B
X PC3 11 -700 -400 100 R 50 50 1 1 B
X VSSA 12 200 -1800 100 U 50 50 1 1 W
X VDDA 13 300 1700 100 D 50 50 1 1 W
X PA0 14 700 1500 100 L 50 50 1 1 B
X PA1 15 700 1400 100 L 50 50 1 1 B
X PA2 16 700 1300 100 L 50 50 1 1 B
X PA3 17 700 1200 100 L 50 50 1 1 B
X VSS 18 -200 -1800 100 U 50 50 1 1 W
X VDD 19 -100 1700 100 D 50 50 1 1 W
X PC13 2 -700 -1400 100 R 50 50 1 1 B
X PA4 20 700 1100 100 L 50 50 1 1 B
X PA5 21 700 1000 100 L 50 50 1 1 B
X PA6 22 700 900 100 L 50 50 1 1 B
X PA7 23 700 800 100 L 50 50 1 1 B
X PC4 24 -700 -500 100 R 50 50 1 1 B
X PC5 25 -700 -600 100 R 50 50 1 1 B
X PB0 26 700 -200 100 L 50 50 1 1 B
X PB1 27 700 -300 100 L 50 50 1 1 B
X PB2 28 700 -400 100 L 50 50 1 1 B
X PB10 29 700 -1200 100 L 50 50 1 1 B
X PC14 3 -700 -1500 100 R 50 50 1 1 B
X VCAP_1 30 -700 1100 100 R 50 50 1 1 W
X VSS 31 -100 -1800 100 U 50 50 1 1 W
X VDD 32 0 1700 100 D 50 50 1 1 W
X PB12 33 700 -1300 100 L 50 50 1 1 B
X PB13 34 700 -1400 100 L 50 50 1 1 B
X PB14 35 700 -1500 100 L 50 50 1 1 B
X PB15 36 700 -1600 100 L 50 50 1 1 B
X PC6 37 -700 -700 100 R 50 50 1 1 B
X PC7 38 -700 -800 100 R 50 50 1 1 B
X PC8 39 -700 -900 100 R 50 50 1 1 B
X PC15 4 -700 -1600 100 R 50 50 1 1 B
X PC9 40 -700 -1000 100 R 50 50 1 1 B
X PA8 41 700 700 100 L 50 50 1 1 B
X PA9 42 700 600 100 L 50 50 1 1 B
X PA10 43 700 500 100 L 50 50 1 1 B
X PA11 44 700 400 100 L 50 50 1 1 B
X PA12 45 700 300 100 L 50 50 1 1 B
X PA13 46 700 200 100 L 50 50 1 1 B
X VSS 47 0 -1800 100 U 50 50 1 1 W
X VDD 48 100 1700 100 D 50 50 1 1 W
X PA14 49 700 100 100 L 50 50 1 1 B
X PH0 5 -700 400 100 R 50 50 1 1 I
X PA15 50 700 0 100 L 50 50 1 1 B
X PC10 51 -700 -1100 100 R 50 50 1 1 B
X PC11 52 -700 -1200 100 R 50 50 1 1 B
X PC12 53 -700 -1300 100 R 50 50 1 1 B
X PD2 54 -700 100 100 R 50 50 1 1 B
X PB3 55 700 -500 100 L 50 50 1 1 B
X PB4 56 700 -600 100 L 50 50 1 1 B
X PB5 57 700 -700 100 L 50 50 1 1 B
X PB6 58 700 -800 100 L 50 50 1 1 B
X PB7 59 700 -900 100 L 50 50 1 1 B
X PH1 6 -700 300 100 R 50 50 1 1 I
X BOOT0 60 -700 1300 100 R 50 50 1 1 I
X PB8 61 700 -1000 100 L 50 50 1 1 B
X PB9 62 700 -1100 100 L 50 50 1 1 B
X VSS 63 100 -1800 100 U 50 50 1 1 W
X VDD 64 200 1700 100 D 50 50 1 1 W
X NRST 7 -700 1500 100 R 50 50 1 1 I
X PC0 8 -700 -100 100 R 50 50 1 1 B
X PC1 9 -700 -200 100 R 50 50 1 1 B
ENDDRAW
ENDDEF
#
# Regulator_Switching_LM2594HVM-3.3
#
DEF Regulator_Switching_LM2594HVM-3.3 U 0 20 Y Y 1 F N
F0 "U" -300 250 50 H V L CNN
F1 "Regulator_Switching_LM2594HVM-3.3" 0 250 50 H V L CNN
F2 "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm" 200 -250 50 H I L CIN
F3 "" 0 100 50 H I C CNN
ALIAS LM2594M-5.0 LM2594M-12 LM2594M-ADJ LM2594HVM-3.3 LM2594HVM-5.0 LM2594HVM-12 LM2594HVM-ADJ
$FPLIST
SOIC*3.9x4.9mm*
$ENDFPLIST
DRAW
S -300 200 300 -200 0 1 10 f
X NC 1 -200 -300 100 U 50 50 1 1 P
X NC 2 -100 -300 100 U 50 50 1 1 P
X NC 3 0 -300 100 U 50 50 1 1 P
X FB 4 400 100 100 L 50 50 1 1 I
X ~ON~/OFF 5 -400 0 100 R 50 50 1 1 I
X GND 6 200 -300 100 U 50 50 1 1 W
X VIN 7 -400 100 100 R 50 50 1 1 W
X OUT 8 400 0 100 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# Sensor_Magnetic_AS5045B
#
DEF Sensor_Magnetic_AS5045B U 0 20 Y Y 1 F N
F0 "U" -400 450 50 H V L CNN
F1 "Sensor_Magnetic_AS5045B" 450 450 50 H V R CNN
F2 "Package_SO:SSOP-16_5.3x6.2mm_P0.65mm" 150 -450 50 H I L CNN
F3 "" -2150 1600 50 H I C CNN
$FPLIST
SSOP*5.3x6.2mm*P0.65mm*
$ENDFPLIST
DRAW
A 0 0 110 -1799 -1 0 1 10 N -110 0 110 0
C 0 0 80 0 1 10 N
S -400 400 400 -400 0 1 10 f
P 2 0 1 10 -110 0 -130 -20 N
P 2 0 1 10 -110 0 -90 -20 N
P 2 0 1 10 110 0 90 -20 N
P 2 0 1 10 110 0 130 -20 N
P 4 0 1 0 10 10 50 -30 30 -50 -10 -10 N
P 7 0 1 0 -30 50 10 10 -10 -10 -50 30 -40 40 -30 50 -25 45 F
X MagINCn 1 -500 -200 100 R 50 50 1 1 C
X CLK 10 500 100 100 L 50 50 1 1 I
X CSn 11 500 0 100 L 50 50 1 1 I
X PWM 12 500 -300 100 L 50 50 1 1 O
X NC 13 400 -200 100 L 50 50 1 1 N N
X NC 14 100 -400 100 U 50 50 1 1 N N
X VDD3V3 15 -100 500 100 D 50 50 1 1 W
X VDD5V 16 0 500 100 D 50 50 1 1 W
X MagDECn 2 -500 -300 100 R 50 50 1 1 C
X A 3 -500 300 100 R 50 50 1 1 O
X B 4 -500 200 100 R 50 50 1 1 O
X NC 5 400 -100 100 L 50 50 1 1 N N
X I 6 -500 100 100 R 50 50 1 1 O
X VSS 7 0 -500 100 U 50 50 1 1 W
X PDIO 8 500 300 100 L 50 50 1 1 I
X DO 9 500 200 100 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# _Library_1_drv8313
#
DEF _Library_1_drv8313 U 0 40 Y Y 1 F N
F0 "U" -300 50 50 H V C CNN
F1 "_Library_1_drv8313" 200 50 50 H V C CNN
F2 "" -700 0 50 H I C CNN
F3 "" -700 0 50 H I C CNN
DRAW
S -450 -50 350 -1550 0 1 0 f
X cpl 1 -550 -150 100 R 50 50 1 1 I
X pgnd3 10 -550 -1050 100 R 50 50 1 1 I
X vm 11 -550 -1150 100 R 50 50 1 1 I
X compp 12 -550 -1250 100 R 50 50 1 1 I
X compn 13 -550 -1350 100 R 50 50 1 1 I
X gnd 14 -550 -1450 100 R 50 50 1 1 W
X v3p3 15 450 -1450 100 L 50 50 1 1 w
X nReset 16 450 -1350 100 L 50 50 1 1 I
X nSleep 17 450 -1250 100 L 50 50 1 1 I
X nFault 18 450 -1150 100 L 50 50 1 1 O
X nCompo 19 450 -1050 100 L 50 50 1 1 I
X cph 2 -550 -250 100 R 50 50 1 1 I
X gnd 20 450 -950 100 L 50 50 1 1 W
X nc 21 450 -850 100 L 50 50 1 1 I
X en3 22 450 -750 100 L 50 50 1 1 I
X in3 23 450 -650 100 L 50 50 1 1 I
X en2 24 450 -550 100 L 50 50 1 1 I
X in2 25 450 -450 100 L 50 50 1 1 I
X en1 26 450 -350 100 L 50 50 1 1 I
X in1 27 450 -250 100 L 50 50 1 1 I
X gnd 28 450 -150 100 L 50 50 1 1 W
X vcp 3 -550 -350 100 R 50 50 1 1 I
X vm 4 -550 -450 100 R 50 50 1 1 I
X out1 5 -550 -550 100 R 50 50 1 1 O
X pgnd1 6 -550 -650 100 R 50 50 1 1 I
X pgnd2 7 -550 -750 100 R 50 50 1 1 I
X out2 8 -550 -850 100 R 50 50 1 1 O
X out3 9 -550 -950 100 R 50 50 1 1 O
ENDDRAW
ENDDEF
#
# kicad_Library_PROGRAMMATOR
#
DEF kicad_Library_PROGRAMMATOR xp 0 40 Y Y 1 F N
F0 "xp" -350 900 50 H V C CNN
F1 "kicad_Library_PROGRAMMATOR" -400 200 50 H V C CNN
F2 "Connector_IDC:IDC-Header_2x05_P2.54mm_Vertical" -350 900 50 H I C CNN
F3 "" -350 900 50 H I C CNN
DRAW
S -700 800 50 300 0 1 0 f
X GND 1 -800 750 100 R 50 50 1 1 P
X +5V 10 150 350 100 L 50 50 1 1 w
X +3V 2 150 750 100 L 50 50 1 1 w
X RESET 3 -800 650 100 R 50 50 1 1 I
X BOOT 4 150 650 100 L 50 50 1 1 I
X RX 5 -800 550 100 R 50 50 1 1 I
X TX 6 150 550 100 L 50 50 1 1 O
X SWDCLK 7 -800 450 100 R 50 50 1 1 I
X SWDDTA 8 150 450 100 L 50 50 1 1 B
X GND 9 -800 350 100 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_+24V
#
DEF power_+24V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+24V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +24V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+3.3V
#
DEF power_+3.3V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3.3V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_+3.3VADC
#
DEF power_+3.3VADC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 150 -50 50 H I C CNN
F1 "power_+3.3VADC" 0 100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3.3VADC 1 0 0 0 U 50 50 0 0 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

252
brd/ScaleBrd/ScaleBrd-cache.lib Normal file
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@ -0,0 +1,252 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# 74xGxx_74AHC1G04
#
DEF 74xGxx_74AHC1G04 U 0 40 Y Y 1 F N
F0 "U" -100 150 50 H V C CNN
F1 "74xGxx_74AHC1G04" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 74LVC1GU04 74AHC1G04 74AHCT1G04 74AUC1G04 74AUP1G04 74AHC1GU04 74AHCT1GU04 74AUC1GU04 74AUP1GU04
$FPLIST
SOT*
SG-*
$ENDFPLIST
DRAW
P 4 0 1 10 -150 100 -150 -100 100 0 -150 100 N
X ~ 2 -300 0 150 R 40 40 1 1 I
X GND 3 0 -100 0 D 40 40 1 1 W N
X ~ 4 250 0 150 L 40 40 1 1 O I
X VCC 5 0 100 0 U 40 40 1 1 W N
ENDDRAW
ENDDEF
#
# Connector_Generic_Conn_02x05_Odd_Even
#
DEF Connector_Generic_Conn_02x05_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 300 50 H V C CNN
F1 "Connector_Generic_Conn_02x05_Odd_Even" 50 -300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 250 150 -250 1 1 10 f
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
X Pin_1 1 -200 200 150 R 50 50 1 1 P
X Pin_10 10 300 -200 150 L 50 50 1 1 P
X Pin_2 2 300 200 150 L 50 50 1 1 P
X Pin_3 3 -200 100 150 R 50 50 1 1 P
X Pin_4 4 300 100 150 L 50 50 1 1 P
X Pin_5 5 -200 0 150 R 50 50 1 1 P
X Pin_6 6 300 0 150 L 50 50 1 1 P
X Pin_7 7 -200 -100 150 R 50 50 1 1 P
X Pin_8 8 300 -100 150 L 50 50 1 1 P
X Pin_9 9 -200 -200 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_CP
#
DEF Device_CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_CP" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
CP_*
$ENDFPLIST
DRAW
S -90 20 90 40 0 1 0 N
S 90 -20 -90 -40 0 1 0 F
P 2 0 1 0 -70 90 -30 90 N
P 2 0 1 0 -50 110 -50 70 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_LED
#
DEF Device_LED D 0 40 N N 1 F N
F0 "D" 0 100 50 H V C CNN
F1 "Device_LED" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
LED*
LED_SMD:*
LED_THT:*
$ENDFPLIST
DRAW
P 2 0 1 10 -50 -50 -50 50 N
P 2 0 1 0 -50 0 50 0 N
P 4 0 1 10 50 -50 50 50 -50 0 50 -50 N
P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# MCU_ST_STM32F0_STM32F030K6Tx
#
DEF MCU_ST_STM32F0_STM32F030K6Tx U 0 20 Y Y 1 F N
F0 "U" -500 850 50 H V L CNN
F1 "MCU_ST_STM32F0_STM32F030K6Tx" 200 850 50 H V L CNN
F2 "Package_QFP:LQFP-32_7x7mm_P0.8mm" -500 -900 50 H I R CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
LQFP*7x7mm*P0.8mm*
$ENDFPLIST
DRAW
S -500 -900 400 800 0 1 10 f
X VDD 1 -100 900 100 D 50 50 1 1 W
X PA4 10 500 300 100 L 50 50 1 1 B
X PA5 11 500 200 100 L 50 50 1 1 B
X PA6 12 500 100 100 L 50 50 1 1 B
X PA7 13 500 0 100 L 50 50 1 1 B
X PB0 14 -600 -200 100 R 50 50 1 1 B
X PB1 15 -600 -300 100 R 50 50 1 1 B
X VSS 16 -100 -1000 100 U 50 50 1 1 W
X VDD 17 0 900 100 D 50 50 1 1 W
X PA8 18 500 -100 100 L 50 50 1 1 B
X PA9 19 500 -200 100 L 50 50 1 1 B
X PF0 2 -600 100 100 R 50 50 1 1 I
X PA10 20 500 -300 100 L 50 50 1 1 B
X PA11 21 500 -400 100 L 50 50 1 1 B
X PA12 22 500 -500 100 L 50 50 1 1 B
X PA13 23 500 -600 100 L 50 50 1 1 B
X PA14 24 500 -700 100 L 50 50 1 1 B
X PA15 25 500 -800 100 L 50 50 1 1 B
X PB3 26 -600 -400 100 R 50 50 1 1 B
X PB4 27 -600 -500 100 R 50 50 1 1 B
X PB5 28 -600 -600 100 R 50 50 1 1 B
X PB6 29 -600 -700 100 R 50 50 1 1 B
X PF1 3 -600 0 100 R 50 50 1 1 I
X PB7 30 -600 -800 100 R 50 50 1 1 B
X BOOT0 31 -600 500 100 R 50 50 1 1 I
X VSS 32 0 -1000 100 U 50 50 1 1 W
X NRST 4 -600 700 100 R 50 50 1 1 I
X VDDA 5 100 900 100 D 50 50 1 1 W
X PA0 6 500 700 100 L 50 50 1 1 B
X PA1 7 500 600 100 L 50 50 1 1 B
X PA2 8 500 500 100 L 50 50 1 1 B
X PA3 9 500 400 100 L 50 50 1 1 B
ENDDRAW
ENDDEF
#
# Mechanical_MountingHole_Pad
#
DEF Mechanical_MountingHole_Pad H 0 40 N N 1 F N
F0 "H" 0 250 50 H V C CNN
F1 "Mechanical_MountingHole_Pad" 0 175 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
MountingHole*Pad*
$ENDFPLIST
DRAW
C 0 50 50 0 1 50 N
X 1 1 0 -100 100 U 50 50 1 1 I
ENDDRAW
ENDDEF
#
# kicad_Library_PROGRAMMATOR
#
DEF kicad_Library_PROGRAMMATOR xp 0 40 Y Y 1 F N
F0 "xp" -350 900 50 H V C CNN
F1 "kicad_Library_PROGRAMMATOR" -400 200 50 H V C CNN
F2 "Connector_IDC:IDC-Header_2x05_P2.54mm_Vertical" -350 900 50 H I C CNN
F3 "" -350 900 50 H I C CNN
DRAW
S -700 800 50 300 0 1 0 f
X GND 1 -800 750 100 R 50 50 1 1 P
X +5V 10 150 350 100 L 50 50 1 1 w
X +3V 2 150 750 100 L 50 50 1 1 w
X RESET 3 -800 650 100 R 50 50 1 1 I
X BOOT 4 150 650 100 L 50 50 1 1 I
X RX 5 -800 550 100 R 50 50 1 1 I
X TX 6 150 550 100 L 50 50 1 1 O
X SWDCLK 7 -800 450 100 R 50 50 1 1 I
X SWDDTA 8 150 450 100 L 50 50 1 1 B
X GND 9 -800 350 100 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_+3.3V
#
DEF power_+3.3V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+3.3V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS +3.3V
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +3V3 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

1
brd/ScaleBrd/ScaleBrd.kicad_pcb Normal file
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(kicad_pcb (version 4) (host kicad "dummy file") )

33
brd/ScaleBrd/ScaleBrd.pro Normal file
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update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]

1100
brd/ScaleBrd/ScaleBrd.sch Normal file
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File diff suppressed because it is too large Load diff

1046
brd/ScaleBrd/ScaleBrd.sch-bak Normal file
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File diff suppressed because it is too large Load diff

39
brd/SensConBrd/sensconbrd/sensconbrd-cache.lib Normal file
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@ -0,0 +1,39 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_Generic_Conn_02x05_Odd_Even
#
DEF Connector_Generic_Conn_02x05_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 300 50 H V C CNN
F1 "Connector_Generic_Conn_02x05_Odd_Even" 50 -300 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 250 150 -250 1 1 10 f
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
X Pin_1 1 -200 200 150 R 50 50 1 1 P
X Pin_10 10 300 -200 150 L 50 50 1 1 P
X Pin_2 2 300 200 150 L 50 50 1 1 P
X Pin_3 3 -200 100 150 R 50 50 1 1 P
X Pin_4 4 300 100 150 L 50 50 1 1 P
X Pin_5 5 -200 0 150 R 50 50 1 1 P
X Pin_6 6 300 0 150 L 50 50 1 1 P
X Pin_7 7 -200 -100 150 R 50 50 1 1 P
X Pin_8 8 300 -100 150 L 50 50 1 1 P
X Pin_9 9 -200 -200 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library

1
brd/SensConBrd/sensconbrd/sensconbrd.kicad_pcb Normal file
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@ -0,0 +1 @@
(kicad_pcb (version 4) (host kicad "dummy file") )

33
brd/SensConBrd/sensconbrd/sensconbrd.pro Normal file
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update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]

86
brd/SensConBrd/sensconbrd/sensconbrd.sch Normal file
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@ -0,0 +1,86 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector_Generic:Conn_02x05_Odd_Even J?
U 1 1 6E58D2DE
P 2650 1650
F 0 "J?" H 2700 2067 50 0000 C CNN
F 1 "Conn_02x05_Odd_Even" H 2700 1976 50 0000 C CNN
F 2 "Connector_IDC:IDC-Header_2x05_P2.54mm_Vertical" H 2650 1650 50 0001 C CNN
F 3 "~" H 2650 1650 50 0001 C CNN
1 2650 1650
1 0 0 -1
$EndComp
$Comp
L Connector_Generic:Conn_02x05_Odd_Even J?
U 1 1 6E58DC78
P 5000 1650
F 0 "J?" H 5050 2067 50 0000 C CNN
F 1 "Conn_02x05_Odd_Even" H 5050 1976 50 0000 C CNN
F 2 "Connector_IDC:IDC-Header_2x05_P2.54mm_Vertical" H 5000 1650 50 0001 C CNN
F 3 "~" H 5000 1650 50 0001 C CNN
1 5000 1650
1 0 0 -1
$EndComp
Wire Wire Line
2450 1450 2950 1450
Connection ~ 2950 1450
Wire Wire Line
4800 1450 5300 1450
Connection ~ 4800 1450
Wire Wire Line
2950 1550 2950 1450
Wire Wire Line
2950 1450 4800 1450
Wire Wire Line
4800 1550 4800 1450
Wire Wire Line
5300 1550 5300 1450
Connection ~ 5300 1450
Wire Wire Line
2450 1550 2450 1450
Connection ~ 2450 1450
Wire Wire Line
2450 1750 2450 1850
Wire Wire Line
2950 1850 2950 1750
Wire Wire Line
2950 1750 4800 1750
Connection ~ 2950 1750
Wire Wire Line
4800 1750 4800 1850
Connection ~ 4800 1750
Wire Wire Line
2950 1750 2450 1750
Connection ~ 2450 1750
Wire Wire Line
5300 1850 5300 1750
Wire Wire Line
5300 1750 4800 1750
Connection ~ 5300 1750
Wire Wire Line
5300 1650 5300 1600
Wire Wire Line
5300 1600 2950 1600
Wire Wire Line
2950 1600 2950 1650
Wire Wire Line
4800 1650 4800 1700
Wire Wire Line
4800 1700 2450 1700
Wire Wire Line
2450 1700 2450 1650
$EndSCHEMATC

4
brd/SensConBrd/sensconbrd/sensconbrd.sch-bak Normal file
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@ -0,0 +1,4 @@
EESchema Schematic File Version 2
EELAYER 25 0
EELAYER END
$EndSCHEMATC

47
brd/SlideBrd1/SlideBrd1-cache.lib Normal file
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@ -0,0 +1,47 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_Generic_Conn_02x07_Odd_Even
#
DEF Connector_Generic_Conn_02x07_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 400 50 H V C CNN
F1 "Connector_Generic_Conn_02x07_Odd_Even" 50 -400 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 350 150 -350 1 1 10 f
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
X Pin_1 1 -200 300 150 R 50 50 1 1 P
X Pin_10 10 300 -100 150 L 50 50 1 1 P
X Pin_11 11 -200 -200 150 R 50 50 1 1 P
X Pin_12 12 300 -200 150 L 50 50 1 1 P
X Pin_13 13 -200 -300 150 R 50 50 1 1 P
X Pin_14 14 300 -300 150 L 50 50 1 1 P
X Pin_2 2 300 300 150 L 50 50 1 1 P
X Pin_3 3 -200 200 150 R 50 50 1 1 P
X Pin_4 4 300 200 150 L 50 50 1 1 P
X Pin_5 5 -200 100 150 R 50 50 1 1 P
X Pin_6 6 300 100 150 L 50 50 1 1 P
X Pin_7 7 -200 0 150 R 50 50 1 1 P
X Pin_8 8 300 0 150 L 50 50 1 1 P
X Pin_9 9 -200 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
#End Library

1
brd/SlideBrd1/SlideBrd1.kicad_pcb Normal file
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@ -0,0 +1 @@
(kicad_pcb (version 4) (host kicad "dummy file") )

33
brd/SlideBrd1/SlideBrd1.pro Normal file
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@ -0,0 +1,33 @@
update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]

85
brd/SlideBrd1/SlideBrd1.sch Normal file
View file

@ -0,0 +1,85 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector_Generic:Conn_02x07_Odd_Even J?
U 1 1 6E5D11A1
P 4950 3250
F 0 "J?" H 5000 3767 50 0000 C CNN
F 1 "Conn_02x07_Odd_Even" H 5000 3676 50 0000 C CNN
F 2 "" H 4950 3250 50 0001 C CNN
F 3 "~" H 4950 3250 50 0001 C CNN
1 4950 3250
1 0 0 -1
$EndComp
Wire Wire Line
4750 3150 4750 3050
Connection ~ 4750 2950
Wire Wire Line
4750 2950 4750 2550
Connection ~ 4750 3050
Wire Wire Line
4750 3050 4750 2950
Wire Wire Line
5250 3150 5250 3050
Wire Wire Line
5250 2550 4750 2550
Connection ~ 5250 2950
Wire Wire Line
5250 2950 5250 2550
Connection ~ 5250 3050
Wire Wire Line
5250 3050 5250 2950
Wire Wire Line
5250 3350 5250 3450
Connection ~ 5250 3450
Wire Wire Line
5250 3450 5250 3550
Connection ~ 5250 3550
Wire Wire Line
5250 3550 5250 3900
Wire Wire Line
5250 3900 4750 3900
Wire Wire Line
4750 3900 4750 3550
Connection ~ 4750 3450
Wire Wire Line
4750 3450 4750 3350
Connection ~ 4750 3550
Wire Wire Line
4750 3550 4750 3450
Wire Wire Line
4750 3250 4200 3250
Wire Wire Line
3650 3250 3650 2350
Wire Wire Line
3650 2350 4200 2350
Wire Wire Line
4200 2350 4200 3250
Connection ~ 4200 3250
Wire Wire Line
4200 3250 3650 3250
Wire Wire Line
5250 3250 5700 3250
Wire Wire Line
6250 3250 6250 2350
Wire Wire Line
6250 2350 5700 2350
Wire Wire Line
5700 2350 5700 3250
Connection ~ 5700 3250
Wire Wire Line
5700 3250 6250 3250
$EndSCHEMATC

4
brd/SlideBrd1/SlideBrd1.sch-bak Normal file
View file

@ -0,0 +1,4 @@
EESchema Schematic File Version 2
EELAYER 25 0
EELAYER END
$EndSCHEMATC

63
brd/SlideBrd2/SlideBrd2-cache.lib Normal file
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@ -0,0 +1,63 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_Generic_Conn_02x07_Odd_Even
#
DEF Connector_Generic_Conn_02x07_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 400 50 H V C CNN
F1 "Connector_Generic_Conn_02x07_Odd_Even" 50 -400 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 350 150 -350 1 1 10 f
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
X Pin_1 1 -200 300 150 R 50 50 1 1 P
X Pin_10 10 300 -100 150 L 50 50 1 1 P
X Pin_11 11 -200 -200 150 R 50 50 1 1 P
X Pin_12 12 300 -200 150 L 50 50 1 1 P
X Pin_13 13 -200 -300 150 R 50 50 1 1 P
X Pin_14 14 300 -300 150 L 50 50 1 1 P
X Pin_2 2 300 300 150 L 50 50 1 1 P
X Pin_3 3 -200 200 150 R 50 50 1 1 P
X Pin_4 4 300 200 150 L 50 50 1 1 P
X Pin_5 5 -200 100 150 R 50 50 1 1 P
X Pin_6 6 300 100 150 L 50 50 1 1 P
X Pin_7 7 -200 0 150 R 50 50 1 1 P
X Pin_8 8 300 0 150 L 50 50 1 1 P
X Pin_9 9 -200 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Mechanical_MountingHole_Pad
#
DEF Mechanical_MountingHole_Pad H 0 40 N N 1 F N
F0 "H" 0 250 50 H V C CNN
F1 "Mechanical_MountingHole_Pad" 0 175 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
MountingHole*Pad*
$ENDFPLIST
DRAW
C 0 50 50 0 1 50 N
X 1 1 0 -100 100 U 50 50 1 1 I
ENDDRAW
ENDDEF
#
#End Library

1
brd/SlideBrd2/SlideBrd2.kicad_pcb Normal file
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@ -0,0 +1 @@
(kicad_pcb (version 4) (host kicad "dummy file") )

33
brd/SlideBrd2/SlideBrd2.pro Normal file
View file

@ -0,0 +1,33 @@
update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]

233
brd/SlideBrd2/SlideBrd2.sch Normal file
View file

@ -0,0 +1,233 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector_Generic:Conn_02x07_Odd_Even J?
U 1 1 6E5D370E
P 5450 3150
F 0 "J?" H 5500 3667 50 0000 C CNN
F 1 "Conn_02x07_Odd_Even" H 5500 3576 50 0000 C CNN
F 2 "" H 5450 3150 50 0001 C CNN
F 3 "~" H 5450 3150 50 0001 C CNN
1 5450 3150
1 0 0 -1
$EndComp
Wire Wire Line
5750 3050 5750 2950
Connection ~ 5750 2850
Wire Wire Line
5750 2850 5750 2450
Connection ~ 5750 2950
Wire Wire Line
5750 2950 5750 2850
Wire Wire Line
5250 3050 5250 2950
Connection ~ 5250 2850
Connection ~ 5250 2950
Wire Wire Line
5250 2950 5250 2850
Wire Wire Line
5250 3250 5250 3350
Connection ~ 5250 3350
Wire Wire Line
5250 3350 5250 3450
Connection ~ 5250 3450
Wire Wire Line
5250 3450 5250 3750
Wire Wire Line
5750 3250 5750 3350
Connection ~ 5750 3350
Wire Wire Line
5750 3350 5750 3450
Connection ~ 5750 3450
Wire Wire Line
5250 3150 4850 3150
Wire Wire Line
5750 3150 6100 3150
$Comp
L Mechanical:MountingHole_Pad H?
U 1 1 6E5D5709
P 6100 3050
F 0 "H?" H 6200 3099 50 0000 L CNN
F 1 "MountingHole_Pad" H 6200 3008 50 0000 L CNN
F 2 "" H 6100 3050 50 0001 C CNN
F 3 "~" H 6100 3050 50 0001 C CNN
1 6100 3050
1 0 0 -1
$EndComp
$Comp
L Mechanical:MountingHole_Pad H?
U 1 1 6E5D5C53
P 6500 3050
F 0 "H?" H 6600 3099 50 0000 L CNN
F 1 "MountingHole_Pad" H 6600 3008 50 0000 L CNN
F 2 "" H 6500 3050 50 0001 C CNN
F 3 "~" H 6500 3050 50 0001 C CNN
1 6500 3050
1 0 0 -1
$EndComp
$Comp
L Mechanical:MountingHole_Pad H?
U 1 1 6E5D5F30
P 6850 3050
F 0 "H?" H 6950 3099 50 0000 L CNN
F 1 "MountingHole_Pad" H 6950 3008 50 0000 L CNN
F 2 "" H 6850 3050 50 0001 C CNN
F 3 "~" H 6850 3050 50 0001 C CNN
1 6850 3050
1 0 0 -1
$EndComp
$Comp
L Mechanical:MountingHole_Pad H?
U 1 1 6E5D62C6
P 4850 3050
F 0 "H?" H 4950 3099 50 0000 L CNN
F 1 "MountingHole_Pad" H 4950 3008 50 0000 L CNN
F 2 "" H 4850 3050 50 0001 C CNN
F 3 "~" H 4850 3050 50 0001 C CNN
1 4850 3050
1 0 0 -1
$EndComp
$Comp
L Mechanical:MountingHole_Pad H?
U 1 1 6E5D679D
P 4500 3050
F 0 "H?" H 4600 3099 50 0000 L CNN
F 1 "MountingHole_Pad" H 4600 3008 50 0000 L CNN
F 2 "" H 4500 3050 50 0001 C CNN
F 3 "~" H 4500 3050 50 0001 C CNN
1 4500 3050
1 0 0 -1
$EndComp
$Comp
L Mechanical:MountingHole_Pad H?
U 1 1 6E5D69FE
P 4100 3050
F 0 "H?" H 4200 3099 50 0000 L CNN
F 1 "MountingHole_Pad" H 4200 3008 50 0000 L CNN
F 2 "" H 4100 3050 50 0001 C CNN
F 3 "~" H 4100 3050 50 0001 C CNN
1 4100 3050
1 0 0 -1
$EndComp
$Comp
L Mechanical:MountingHole_Pad H?
U 1 1 6E5D6CC9
P 5250 2200
F 0 "H?" H 5350 2249 50 0000 L CNN
F 1 "MountingHole_Pad" H 5350 2158 50 0000 L CNN
F 2 "" H 5250 2200 50 0001 C CNN
F 3 "~" H 5250 2200 50 0001 C CNN
1 5250 2200
1 0 0 -1
$EndComp
$Comp
L Mechanical:MountingHole_Pad H?
U 1 1 6E5D70F8
P 5500 1950
F 0 "H?" H 5600 1999 50 0000 L CNN
F 1 "MountingHole_Pad" H 5600 1908 50 0000 L CNN
F 2 "" H 5500 1950 50 0001 C CNN
F 3 "~" H 5500 1950 50 0001 C CNN
1 5500 1950
1 0 0 -1
$EndComp
$Comp
L Mechanical:MountingHole_Pad H?
U 1 1 6E5D752F
P 5750 2200
F 0 "H?" H 5850 2249 50 0000 L CNN
F 1 "MountingHole_Pad" H 5850 2158 50 0000 L CNN
F 2 "" H 5750 2200 50 0001 C CNN
F 3 "~" H 5750 2200 50 0001 C CNN
1 5750 2200
1 0 0 -1
$EndComp
$Comp
L Mechanical:MountingHole_Pad H?
U 1 1 6E5D7875
P 5750 4050
F 0 "H?" H 5650 4007 50 0000 R CNN
F 1 "MountingHole_Pad" H 5650 4098 50 0000 R CNN
F 2 "" H 5750 4050 50 0001 C CNN
F 3 "~" H 5750 4050 50 0001 C CNN
1 5750 4050
-1 0 0 1
$EndComp
$Comp
L Mechanical:MountingHole_Pad H?
U 1 1 6E5D7DA7
P 5500 3900
F 0 "H?" H 5400 3857 50 0000 R CNN
F 1 "MountingHole_Pad" H 5400 3948 50 0000 R CNN
F 2 "" H 5500 3900 50 0001 C CNN
F 3 "~" H 5500 3900 50 0001 C CNN
1 5500 3900
-1 0 0 1
$EndComp
$Comp
L Mechanical:MountingHole_Pad H?
U 1 1 6E5D8098
P 5250 4100
F 0 "H?" H 5150 4057 50 0000 R CNN
F 1 "MountingHole_Pad" H 5150 4148 50 0000 R CNN
F 2 "" H 5250 4100 50 0001 C CNN
F 3 "~" H 5250 4100 50 0001 C CNN
1 5250 4100
-1 0 0 1
$EndComp
Wire Wire Line
5250 2300 5250 2450
Wire Wire Line
5500 2050 5500 2450
Wire Wire Line
5500 2450 5250 2450
Connection ~ 5250 2450
Wire Wire Line
5250 2450 5250 2850
Wire Wire Line
5500 2450 5750 2450
Connection ~ 5500 2450
Wire Wire Line
5750 2450 5750 2300
Connection ~ 5750 2450
Wire Wire Line
5750 3450 5750 3750
Wire Wire Line
5750 3750 5500 3750
Connection ~ 5750 3750
Wire Wire Line
5750 3750 5750 3950
Wire Wire Line
5500 3800 5500 3750
Connection ~ 5500 3750
Wire Wire Line
5500 3750 5250 3750
Wire Wire Line
5250 4000 5250 3750
Connection ~ 5250 3750
Wire Wire Line
4850 3150 4500 3150
Connection ~ 4850 3150
Connection ~ 4500 3150
Wire Wire Line
4500 3150 4100 3150
Wire Wire Line
6100 3150 6500 3150
Connection ~ 6100 3150
Connection ~ 6500 3150
Wire Wire Line
6500 3150 6850 3150
$EndSCHEMATC

4
brd/SlideBrd2/SlideBrd2.sch-bak Normal file
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@ -0,0 +1,4 @@
EESchema Schematic File Version 2
EELAYER 25 0
EELAYER END
$EndSCHEMATC

95
brd/Stack1MainBrd/Stack1MainBrd-cache.lib Normal file
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@ -0,0 +1,95 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Connector_Generic_Conn_02x07_Odd_Even
#
DEF Connector_Generic_Conn_02x07_Odd_Even J 0 40 Y N 1 F N
F0 "J" 50 400 50 H V C CNN
F1 "Connector_Generic_Conn_02x07_Odd_Even" 50 -400 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_2x??_*
$ENDFPLIST
DRAW
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 350 150 -350 1 1 10 f
S 150 -295 100 -305 1 1 6 N
S 150 -195 100 -205 1 1 6 N
S 150 -95 100 -105 1 1 6 N
S 150 5 100 -5 1 1 6 N
S 150 105 100 95 1 1 6 N
S 150 205 100 195 1 1 6 N
S 150 305 100 295 1 1 6 N
X Pin_1 1 -200 300 150 R 50 50 1 1 P
X Pin_10 10 300 -100 150 L 50 50 1 1 P
X Pin_11 11 -200 -200 150 R 50 50 1 1 P
X Pin_12 12 300 -200 150 L 50 50 1 1 P
X Pin_13 13 -200 -300 150 R 50 50 1 1 P
X Pin_14 14 300 -300 150 L 50 50 1 1 P
X Pin_2 2 300 300 150 L 50 50 1 1 P
X Pin_3 3 -200 200 150 R 50 50 1 1 P
X Pin_4 4 300 200 150 L 50 50 1 1 P
X Pin_5 5 -200 100 150 R 50 50 1 1 P
X Pin_6 6 300 100 150 L 50 50 1 1 P
X Pin_7 7 -200 0 150 R 50 50 1 1 P
X Pin_8 8 300 0 150 L 50 50 1 1 P
X Pin_9 9 -200 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_CP
#
DEF Device_CP C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_CP" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
CP_*
$ENDFPLIST
DRAW
S -90 20 90 40 0 1 0 N
S 90 -20 -90 -40 0 1 0 F
P 2 0 1 0 -70 90 -30 90 N
P 2 0 1 0 -50 110 -50 70 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# power_+24V
#
DEF power_+24V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+24V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +24V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

1
brd/Stack1MainBrd/Stack1MainBrd.kicad_pcb Normal file
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(kicad_pcb (version 4) (host kicad "dummy file") )

33
brd/Stack1MainBrd/Stack1MainBrd.pro Normal file
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update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]

439
brd/Stack1MainBrd/Stack1MainBrd.sch Normal file
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@ -0,0 +1,439 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector_Generic:Conn_02x07_Odd_Even J?
U 1 1 6E59A9F7
P 3250 3850
F 0 "J?" H 3300 4367 50 0000 C CNN
F 1 "Conn_02x07_Odd_Even" H 3300 4276 50 0000 C CNN
F 2 "" H 3250 3850 50 0001 C CNN
F 3 "~" H 3250 3850 50 0001 C CNN
1 3250 3850
1 0 0 -1
$EndComp
$Comp
L Connector_Generic:Conn_02x07_Odd_Even J?
U 1 1 6E59B935
P 6800 3850
F 0 "J?" H 6850 4367 50 0000 C CNN
F 1 "Conn_02x07_Odd_Even" H 6850 4276 50 0000 C CNN
F 2 "" H 6800 3850 50 0001 C CNN
F 3 "~" H 6800 3850 50 0001 C CNN
1 6800 3850
1 0 0 -1
$EndComp
Wire Wire Line
3550 3850 3550 3900
Wire Wire Line
7200 3850 7100 3850
Wire Wire Line
2950 3800 2950 3850
Wire Wire Line
2950 3850 3050 3850
Wire Wire Line
3550 3750 3550 3650
Connection ~ 3550 3550
Wire Wire Line
3550 3550 3550 3200
Connection ~ 3550 3650
Wire Wire Line
3550 3650 3550 3550
Wire Wire Line
3050 3750 3050 3650
Connection ~ 3050 3550
Wire Wire Line
3050 3550 3050 3200
Connection ~ 3050 3650
Wire Wire Line
3050 3650 3050 3550
Wire Wire Line
3050 3950 3050 4050
Connection ~ 3050 4050
Wire Wire Line
3050 4050 3050 4150
Connection ~ 3050 4150
Wire Wire Line
3050 4150 3050 4400
Wire Wire Line
3550 3950 3550 4050
Connection ~ 3550 4050
Wire Wire Line
3550 4050 3550 4150
Connection ~ 3550 4150
Wire Wire Line
3550 4150 3550 4400
$Comp
L power:GND #PWR?
U 1 1 6E5A568F
P 3550 4400
F 0 "#PWR?" H 3550 4150 50 0001 C CNN
F 1 "GND" H 3555 4227 50 0000 C CNN
F 2 "" H 3550 4400 50 0001 C CNN
F 3 "" H 3550 4400 50 0001 C CNN
1 3550 4400
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5A5B89
P 3050 4400
F 0 "#PWR?" H 3050 4150 50 0001 C CNN
F 1 "GND" H 3055 4227 50 0000 C CNN
F 2 "" H 3050 4400 50 0001 C CNN
F 3 "" H 3050 4400 50 0001 C CNN
1 3050 4400
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5A5EB1
P 3550 3200
F 0 "#PWR?" H 3550 3050 50 0001 C CNN
F 1 "+24V" H 3565 3373 50 0000 C CNN
F 2 "" H 3550 3200 50 0001 C CNN
F 3 "" H 3550 3200 50 0001 C CNN
1 3550 3200
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5A6291
P 3050 3200
F 0 "#PWR?" H 3050 3050 50 0001 C CNN
F 1 "+24V" H 3065 3373 50 0000 C CNN
F 2 "" H 3050 3200 50 0001 C CNN
F 3 "" H 3050 3200 50 0001 C CNN
1 3050 3200
1 0 0 -1
$EndComp
Text Label 3850 3800 0 50 ~ 0
canh
Text Label 3850 3900 0 50 ~ 0
canl
$Comp
L Connector_Generic:Conn_02x07_Odd_Even J?
U 1 1 6E5A6F7D
P 4900 3850
F 0 "J?" H 4950 4367 50 0000 C CNN
F 1 "Conn_02x07_Odd_Even" H 4950 4276 50 0000 C CNN
F 2 "" H 4900 3850 50 0001 C CNN
F 3 "~" H 4900 3850 50 0001 C CNN
1 4900 3850
1 0 0 -1
$EndComp
Wire Wire Line
4700 3800 4700 3850
Wire Wire Line
5200 3900 5200 3850
Connection ~ 4700 3800
Connection ~ 5200 3900
Wire Wire Line
6600 3800 6600 3850
Wire Wire Line
7200 3900 7200 3850
Wire Wire Line
4700 3950 4700 4050
Connection ~ 4700 4050
Wire Wire Line
4700 4050 4700 4150
Connection ~ 4700 4150
Wire Wire Line
4700 4150 4700 4400
Wire Wire Line
5200 3950 5200 4050
Connection ~ 5200 4050
Wire Wire Line
5200 4050 5200 4150
Connection ~ 5200 4150
Wire Wire Line
5200 4150 5200 4400
Wire Wire Line
6600 3950 6600 4050
Connection ~ 6600 4050
Wire Wire Line
6600 4050 6600 4150
Connection ~ 6600 4150
Wire Wire Line
6600 4150 6600 4400
Wire Wire Line
7100 3950 7100 4050
Connection ~ 7100 4050
Wire Wire Line
7100 4050 7100 4150
Connection ~ 7100 4150
Wire Wire Line
7100 4150 7100 4400
Wire Wire Line
4700 3750 4700 3650
Connection ~ 4700 3550
Wire Wire Line
4700 3550 4700 3200
Connection ~ 4700 3650
Wire Wire Line
4700 3650 4700 3550
Wire Wire Line
5200 3750 5200 3650
Connection ~ 5200 3550
Wire Wire Line
5200 3550 5200 3200
Connection ~ 5200 3650
Wire Wire Line
5200 3650 5200 3550
Wire Wire Line
6600 3750 6600 3650
Connection ~ 6600 3550
Wire Wire Line
6600 3550 6600 3200
Connection ~ 6600 3650
Wire Wire Line
6600 3650 6600 3550
Wire Wire Line
7100 3750 7100 3650
Connection ~ 7100 3550
Wire Wire Line
7100 3550 7100 3200
Connection ~ 7100 3650
Wire Wire Line
7100 3650 7100 3550
$Comp
L power:+24V #PWR?
U 1 1 6E5B5261
P 4700 3200
F 0 "#PWR?" H 4700 3050 50 0001 C CNN
F 1 "+24V" H 4715 3373 50 0000 C CNN
F 2 "" H 4700 3200 50 0001 C CNN
F 3 "" H 4700 3200 50 0001 C CNN
1 4700 3200
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5B56B3
P 5200 3200
F 0 "#PWR?" H 5200 3050 50 0001 C CNN
F 1 "+24V" H 5215 3373 50 0000 C CNN
F 2 "" H 5200 3200 50 0001 C CNN
F 3 "" H 5200 3200 50 0001 C CNN
1 5200 3200
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5B6183
P 6600 3200
F 0 "#PWR?" H 6600 3050 50 0001 C CNN
F 1 "+24V" H 6615 3373 50 0000 C CNN
F 2 "" H 6600 3200 50 0001 C CNN
F 3 "" H 6600 3200 50 0001 C CNN
1 6600 3200
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5B6625
P 7100 3200
F 0 "#PWR?" H 7100 3050 50 0001 C CNN
F 1 "+24V" H 7115 3373 50 0000 C CNN
F 2 "" H 7100 3200 50 0001 C CNN
F 3 "" H 7100 3200 50 0001 C CNN
1 7100 3200
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5B6A30
P 4700 4400
F 0 "#PWR?" H 4700 4150 50 0001 C CNN
F 1 "GND" H 4705 4227 50 0000 C CNN
F 2 "" H 4700 4400 50 0001 C CNN
F 3 "" H 4700 4400 50 0001 C CNN
1 4700 4400
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5B6D86
P 5200 4400
F 0 "#PWR?" H 5200 4150 50 0001 C CNN
F 1 "GND" H 5205 4227 50 0000 C CNN
F 2 "" H 5200 4400 50 0001 C CNN
F 3 "" H 5200 4400 50 0001 C CNN
1 5200 4400
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5B7677
P 6600 4400
F 0 "#PWR?" H 6600 4150 50 0001 C CNN
F 1 "GND" H 6605 4227 50 0000 C CNN
F 2 "" H 6600 4400 50 0001 C CNN
F 3 "" H 6600 4400 50 0001 C CNN
1 6600 4400
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5B7E36
P 7100 4400
F 0 "#PWR?" H 7100 4150 50 0001 C CNN
F 1 "GND" H 7105 4227 50 0000 C CNN
F 2 "" H 7100 4400 50 0001 C CNN
F 3 "" H 7100 4400 50 0001 C CNN
1 7100 4400
1 0 0 -1
$EndComp
$Comp
L Device:CP C?
U 1 1 6E5C4915
P 3850 2750
F 0 "C?" H 3968 2796 50 0000 L CNN
F 1 "270uF" H 3968 2705 50 0000 L CNN
F 2 "Capacitor_THT:CP_Radial_D10.0mm_P5.00mm" H 3888 2600 50 0001 C CNN
F 3 "~" H 3850 2750 50 0001 C CNN
1 3850 2750
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5C5160
P 3850 2600
F 0 "#PWR?" H 3850 2450 50 0001 C CNN
F 1 "+24V" H 3865 2773 50 0000 C CNN
F 2 "" H 3850 2600 50 0001 C CNN
F 3 "" H 3850 2600 50 0001 C CNN
1 3850 2600
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5C557B
P 3850 2900
F 0 "#PWR?" H 3850 2650 50 0001 C CNN
F 1 "GND" H 3855 2727 50 0000 C CNN
F 2 "" H 3850 2900 50 0001 C CNN
F 3 "" H 3850 2900 50 0001 C CNN
1 3850 2900
1 0 0 -1
$EndComp
$Comp
L Device:CP C?
U 1 1 6E5C5BF2
P 4300 2750
F 0 "C?" H 4418 2796 50 0000 L CNN
F 1 "270uF" H 4418 2705 50 0000 L CNN
F 2 "Capacitor_THT:CP_Radial_D10.0mm_P5.00mm" H 4338 2600 50 0001 C CNN
F 3 "~" H 4300 2750 50 0001 C CNN
1 4300 2750
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5C5BF8
P 4300 2600
F 0 "#PWR?" H 4300 2450 50 0001 C CNN
F 1 "+24V" H 4315 2773 50 0000 C CNN
F 2 "" H 4300 2600 50 0001 C CNN
F 3 "" H 4300 2600 50 0001 C CNN
1 4300 2600
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5C5BFE
P 4300 2900
F 0 "#PWR?" H 4300 2650 50 0001 C CNN
F 1 "GND" H 4305 2727 50 0000 C CNN
F 2 "" H 4300 2900 50 0001 C CNN
F 3 "" H 4300 2900 50 0001 C CNN
1 4300 2900
1 0 0 -1
$EndComp
$Comp
L Device:CP C?
U 1 1 6E5C769E
P 5900 2800
F 0 "C?" H 6018 2846 50 0000 L CNN
F 1 "270uF" H 6018 2755 50 0000 L CNN
F 2 "Capacitor_THT:CP_Radial_D10.0mm_P5.00mm" H 5938 2650 50 0001 C CNN
F 3 "~" H 5900 2800 50 0001 C CNN
1 5900 2800
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5C76A4
P 5900 2650
F 0 "#PWR?" H 5900 2500 50 0001 C CNN
F 1 "+24V" H 5915 2823 50 0000 C CNN
F 2 "" H 5900 2650 50 0001 C CNN
F 3 "" H 5900 2650 50 0001 C CNN
1 5900 2650
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5C76AA
P 5900 2950
F 0 "#PWR?" H 5900 2700 50 0001 C CNN
F 1 "GND" H 5905 2777 50 0000 C CNN
F 2 "" H 5900 2950 50 0001 C CNN
F 3 "" H 5900 2950 50 0001 C CNN
1 5900 2950
1 0 0 -1
$EndComp
$Comp
L Device:CP C?
U 1 1 6E5C923D
P 6250 2800
F 0 "C?" H 6368 2846 50 0000 L CNN
F 1 "270uF" H 6368 2755 50 0000 L CNN
F 2 "Capacitor_THT:CP_Radial_D10.0mm_P5.00mm" H 6288 2650 50 0001 C CNN
F 3 "~" H 6250 2800 50 0001 C CNN
1 6250 2800
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5C9243
P 6250 2650
F 0 "#PWR?" H 6250 2500 50 0001 C CNN
F 1 "+24V" H 6265 2823 50 0000 C CNN
F 2 "" H 6250 2650 50 0001 C CNN
F 3 "" H 6250 2650 50 0001 C CNN
1 6250 2650
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5C9249
P 6250 2950
F 0 "#PWR?" H 6250 2700 50 0001 C CNN
F 1 "GND" H 6255 2777 50 0000 C CNN
F 2 "" H 6250 2950 50 0001 C CNN
F 3 "" H 6250 2950 50 0001 C CNN
1 6250 2950
1 0 0 -1
$EndComp
Wire Wire Line
4700 3800 6600 3800
Wire Wire Line
5200 3900 7200 3900
Wire Wire Line
2950 3800 4700 3800
Wire Wire Line
3550 3900 5200 3900
$EndSCHEMATC

439
brd/Stack1MainBrd/Stack1MainBrd.sch-bak Normal file
View file

@ -0,0 +1,439 @@
EESchema Schematic File Version 4
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L Connector_Generic:Conn_02x07_Odd_Even J?
U 1 1 6E59A9F7
P 3250 3850
F 0 "J?" H 3300 4367 50 0000 C CNN
F 1 "Conn_02x07_Odd_Even" H 3300 4276 50 0000 C CNN
F 2 "" H 3250 3850 50 0001 C CNN
F 3 "~" H 3250 3850 50 0001 C CNN
1 3250 3850
1 0 0 -1
$EndComp
$Comp
L Connector_Generic:Conn_02x07_Odd_Even J?
U 1 1 6E59B935
P 8250 3850
F 0 "J?" H 8300 4367 50 0000 C CNN
F 1 "Conn_02x07_Odd_Even" H 8300 4276 50 0000 C CNN
F 2 "" H 8250 3850 50 0001 C CNN
F 3 "~" H 8250 3850 50 0001 C CNN
1 8250 3850
1 0 0 -1
$EndComp
Wire Wire Line
3550 3850 3550 3900
Wire Wire Line
8650 3850 8550 3850
Wire Wire Line
2950 3800 2950 3850
Wire Wire Line
2950 3850 3050 3850
Wire Wire Line
3550 3750 3550 3650
Connection ~ 3550 3550
Wire Wire Line
3550 3550 3550 3200
Connection ~ 3550 3650
Wire Wire Line
3550 3650 3550 3550
Wire Wire Line
3050 3750 3050 3650
Connection ~ 3050 3550
Wire Wire Line
3050 3550 3050 3200
Connection ~ 3050 3650
Wire Wire Line
3050 3650 3050 3550
Wire Wire Line
3050 3950 3050 4050
Connection ~ 3050 4050
Wire Wire Line
3050 4050 3050 4150
Connection ~ 3050 4150
Wire Wire Line
3050 4150 3050 4400
Wire Wire Line
3550 3950 3550 4050
Connection ~ 3550 4050
Wire Wire Line
3550 4050 3550 4150
Connection ~ 3550 4150
Wire Wire Line
3550 4150 3550 4400
$Comp
L power:GND #PWR?
U 1 1 6E5A568F
P 3550 4400
F 0 "#PWR?" H 3550 4150 50 0001 C CNN
F 1 "GND" H 3555 4227 50 0000 C CNN
F 2 "" H 3550 4400 50 0001 C CNN
F 3 "" H 3550 4400 50 0001 C CNN
1 3550 4400
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 6E5A5B89
P 3050 4400
F 0 "#PWR?" H 3050 4150 50 0001 C CNN
F 1 "GND" H 3055 4227 50 0000 C CNN
F 2 "" H 3050 4400 50 0001 C CNN
F 3 "" H 3050 4400 50 0001 C CNN
1 3050 4400
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5A5EB1
P 3550 3200
F 0 "#PWR?" H 3550 3050 50 0001 C CNN
F 1 "+24V" H 3565 3373 50 0000 C CNN
F 2 "" H 3550 3200 50 0001 C CNN
F 3 "" H 3550 3200 50 0001 C CNN
1 3550 3200
1 0 0 -1
$EndComp
$Comp
L power:+24V #PWR?
U 1 1 6E5A6291
P 3050 3200
F 0 "#PWR?" H 3050 3050 50 0001 C CNN
F 1 "+24V" H 3065 3373 50 0000 C CNN
F 2 "" H 3050 3200 50 0001 C CNN
F 3 "" H 3050 3200 50 0001 C CNN
1 3050 3200
1 0 0 -1
$EndComp
Text Label 3850 3800 0 50 ~ 0
canh
Text Label 3850 3900 0 50 ~ 0
canl
$Comp
L Connector_Generic:Conn_02x07_Odd_Even J?
U 1 1 6E5A6F7D
P 4900 3850
F 0 "J?" H 4950 4367 50 0000 C CNN
F 1 "Conn_02x07_Odd_Even" H 4950 4276 50 0000 C CNN
F 2 "" H 4900 3850 50 0001 C CNN
F 3 "~" H 4900 3850 50 0001 C CNN
1 4900 3850
1 0 0 -1
$EndComp
Wire Wire Line
2950 3800 4700 3800
Wire Wire Line
4700 3800 4700 3850
Wire Wire Line
3550 3900 5200 3900
Wire Wire Line
5200 3900 5200 3850
Connection ~ 4700 3800
Connection ~ 5200 3900
Wire Wire Line
8050 3800 8050 3850
Wire Wire Line
8650 3900 8650 3850
Wire Wire Line
4700 3950 4700 4050
Connection ~ 4700 4050
Wire Wire Line
4700 4050 4700 4150
Connection ~ 4700 4150
Wire Wire Line
4700 4150 4700 4400
Wire Wire Line
5200 3950 5200 4050
Connection ~ 5200 4050
Wire Wire Line
5200 4050 5200 4150
Connection ~ 5200 4150
Wire Wire Line
5200 4150 5200 4400
Wire Wire Line
8050 3950 8050 4050
Connection ~ 8050 4050
Wire Wire Line
8050 4050 8050 4150
Connection ~ 8050 4150
Wire Wire Line
8050 4150 8050 4400
Wire Wire Line
8550 3950 8550 4050
Connection ~ 8550 4050
Wire Wire Line
8550 4050 8550 4150
Connection ~ 8550 4150
Wire Wire Line
8550 4150 8550 4400
Wire Wire Line
4700 3750 4700 3650
Connection ~ 4700 3550
Wire Wire Line
4700 3550 4700 3200
Connection ~ 4700 3650
Wire Wire Line
4700 3650 4700 3550
Wire Wire Line
5200 3750 5200 3650
Connection ~ 5200 3550
Wire Wire Line
5200 3550 5200 3200
Connection ~ 5200 3650
Wire Wire Line
5200 3650 5200 3550
Wire Wire Line
8050 3750 8050 3650
Connection ~ 8050 3550
Wire Wire Line
8050 3550 8050 3200
Connection ~ 8050 3650
Wire Wire Line
8050 3650 8050 3550
Wire Wire Line
8550 3750 8550 3650
Connection ~ 8550 3550
Wire Wire Line
8550 3550 8550 3200
Connection ~ 8550 3650
Wire Wire Line
8550 3650 8550 3550
$Comp
L power:+24V #PWR?
U 1 1 6E5B5261
P 4700 3200
F 0 "#PWR?" H 4700 3050 50 0001 C CNN
F 1 "+24V" H 4715 3373 50 0000 C CNN
F 2 "" H 4700 3200 50 0001 C CNN
F 3 "" H 4700 3200 50 0001 C CNN
1 4700 3200
1 0 0 -1
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update=22/05/2015 07:44:53
version=1
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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
#define __ARM_ARCH_6M__ 1
#endif
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
#define __ARM_ARCH_7M__ 1
#endif
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
#define __ARM_ARCH_7EM__ 1
#endif
/* __ARM_ARCH_8M_BASE__ not applicable */
/* __ARM_ARCH_8M_MAIN__ not applicable */
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION __packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __enable_irq(); */
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1U);
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value != 0U; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return result;
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.7
* @date 19. June 2018
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2018 IAR Systems
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
/* Macros already defined */
#else
#if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
#if __ARM_ARCH == 6
#define __ARM_ARCH_6M__ 1
#elif __ARM_ARCH == 7
#if __ARM_FEATURE_DSP
#define __ARM_ARCH_7EM__ 1
#else
#define __ARM_ARCH_7M__ 1
#endif
#endif /* __ARM_ARCH */
#endif /* __ARM_ARCH_PROFILE == 'M' */
#endif
/* Alternativ core deduction for older ICCARM's */
#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
!defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
#if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
#define __ARM_ARCH_6M__ 1
#elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
#define __ARM_ARCH_7M__ 1
#elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
#define __ARM_ARCH_7EM__ 1
#elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
#define __ARM_ARCH_8M_BASE__ 1
#elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
#define __ARM_ARCH_8M_MAIN__ 1
#else
#error "Unknown target."
#endif
#endif
#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
#define __IAR_M0_FAMILY 1
#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
#define __IAR_M0_FAMILY 1
#else
#define __IAR_M0_FAMILY 0
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
/* Needs IAR language extensions */
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __enable_irq __iar_builtin_enable_interrupt
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#define __get_APSR() (__arm_rsr("APSR"))
#define __get_BASEPRI() (__arm_rsr("BASEPRI"))
#define __get_CONTROL() (__arm_rsr("CONTROL"))
#define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
#else
#define __get_FPSCR() ( 0 )
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#define __get_IPSR() (__arm_rsr("IPSR"))
#define __get_MSP() (__arm_rsr("MSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __get_MSPLIM() (0U)
#else
#define __get_MSPLIM() (__arm_rsr("MSPLIM"))
#endif
#define __get_PRIMASK() (__arm_rsr("PRIMASK"))
#define __get_PSP() (__arm_rsr("PSP"))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __get_PSPLIM() (0U)
#else
#define __get_PSPLIM() (__arm_rsr("PSPLIM"))
#endif
#define __get_xPSR() (__arm_rsr("xPSR"))
#define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
#define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
#define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
#define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
#define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
#define __set_MSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
#endif
#define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
#define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __set_PSPLIM(VALUE) ((void)(VALUE))
#else
#define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
#endif
#define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
#define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
#define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
#define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
#define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
#define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
#define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
#define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
#define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
#define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
#define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
#define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
#define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
#define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
#define __TZ_get_PSPLIM_NS() (0U)
#define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
#else
#define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
#define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
#endif
#define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
#define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#if !__IAR_M0_FAMILY
#define __SSAT __iar_builtin_SSAT
#endif
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#if !__IAR_M0_FAMILY
#define __USAT __iar_builtin_USAT
#endif
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#if __ARM_MEDIA__
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#endif
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz_not_active
#define __SSAT __cmsis_iar_ssat_not_active
#define __USAT __cmsis_iar_usat_not_active
#define __RBIT __cmsis_iar_rbit_not_active
#define __get_APSR __cmsis_iar_get_APSR_not_active
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#define __set_FPSCR __cmsis_iar_set_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if __IAR_M0_FAMILY
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#undef __CLZ
#undef __SSAT
#undef __USAT
#undef __RBIT
#undef __get_APSR
__STATIC_INLINE uint8_t __CLZ(uint32_t data)
{
if (data == 0U) { return 32U; }
uint32_t count = 0U;
uint32_t mask = 0x80000000U;
while ((data & mask) == 0U)
{
count += 1U;
mask = mask >> 1U;
}
return count;
}
__STATIC_INLINE uint32_t __RBIT(uint32_t v)
{
uint8_t sc = 31U;
uint32_t r = v;
for (v >>= 1U; v; v >>= 1U)
{
r <<= 1U;
r |= v & 1U;
sc--;
}
return (r << sc);
}
__STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t res;
__asm("MRS %0,APSR" : "=r" (res));
return res;
}
#endif
#if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
#undef __get_FPSCR
#undef __set_FPSCR
#define __get_FPSCR() (0)
#define __set_FPSCR(VALUE) ((void)VALUE)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#define __get_xPSR __get_PSR
#if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
#endif
/* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__CORTEX_M >= 0x03)
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT void __set_BASEPRI_MAX(uint32_t value)
{
__asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
}
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* (__CORTEX_M >= 0x03) */
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint32_t __get_MSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,MSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_MSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure MSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR MSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __get_PSPLIM(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM" : "=r" (res));
#endif
return res;
}
__IAR_FT void __set_PSPLIM(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
{
__asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PSP_NS(uint32_t value)
{
__asm volatile("MSR PSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_MSP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSP_NS(uint32_t value)
{
__asm volatile("MSR MSP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_SP_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,SP_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_SP_NS(uint32_t value)
{
__asm volatile("MSR SP_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
{
__asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
{
__asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
{
__asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
}
__IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
{
uint32_t res;
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
res = 0U;
#else
__asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
#endif
return res;
}
__IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
{
#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
// without main extensions, the non-secure PSPLIM is RAZ/WI
(void)value;
#else
__asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
#endif
}
__IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
{
uint32_t res;
__asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
return res;
}
__IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
{
__asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
#if __IAR_M0_FAMILY
__STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
{
if ((sat >= 1U) && (sat <= 32U))
{
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
const int32_t min = -1 - max ;
if (val > max)
{
return max;
}
else if (val < min)
{
return min;
}
}
return val;
}
__STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
{
if (sat <= 31U)
{
const uint32_t max = ((1U << sat) - 1U);
if (val > (int32_t)max)
{
return max;
}
else if (val < 0)
{
return 0U;
}
}
return (uint32_t)val;
}
#endif
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
__IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
{
uint32_t res;
__ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
{
uint32_t res;
__ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
{
uint32_t res;
__ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
return res;
}
__IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
{
__ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
{
__ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
}
__IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
{
__ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
__IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
{
__ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
{
__ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
{
__ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
}
__IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint8_t)res);
}
__IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return ((uint16_t)res);
}
__IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
__IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
{
uint32_t res;
__ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
return res;
}
#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
#undef __IAR_FT
#undef __IAR_M0_FAMILY
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif

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/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V5.0.5
* @date 28. May 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M0
@{
*/
#include "cmsis_version.h"
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (0U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000U
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M0 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/**************************************************************************//**
* @file core_cm1.h
* @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File
* @version V1.0.0
* @date 23. July 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CM1_H_GENERIC
#define __CORE_CM1_H_GENERIC
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
CMSIS violates the following MISRA-C:2004 rules:
\li Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
\li Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/**
\ingroup Cortex_M1
@{
*/
#include "cmsis_version.h"
/* CMSIS CM1 definitions */
#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
__CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
#define __CORTEX_M (1U) /*!< Cortex-M Core */
/** __FPU_USED indicates whether an FPU is used or not.
This core does not support an FPU at all
*/
#define __FPU_USED 0U
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#if defined __ARM_PCS_VFP
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TI_ARM__ )
#if defined __TI_VFP_SUPPORT__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
#if defined __FPU_VFP__
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __CSMC__ )
#if ( __CSMC__ & 0x400U)
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#endif
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM1_H_DEPENDANT
#define __CORE_CM1_H_DEPENDANT
#ifdef __cplusplus
extern "C" {
#endif
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM1_REV
#define __CM1_REV 0x0100U
#warning "__CM1_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2U
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0U
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
/**
\defgroup CMSIS_glob_defs CMSIS Global Defines
<strong>IO Type Qualifiers</strong> are used
\li to specify the access to peripheral variables.
\li for automatic generation of peripheral register debug information.
*/
#ifdef __cplusplus
#define __I volatile /*!< Defines 'read only' permissions */
#else
#define __I volatile const /*!< Defines 'read only' permissions */
#endif
#define __O volatile /*!< Defines 'write only' permissions */
#define __IO volatile /*!< Defines 'read / write' permissions */
/* following defines should be used for structure members */
#define __IM volatile const /*! Defines 'read only' structure member permissions */
#define __OM volatile /*! Defines 'write only' structure member permissions */
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
/*@} end of group Cortex_M1 */
/*******************************************************************************
* Register Abstraction
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
******************************************************************************/
/**
\defgroup CMSIS_core_register Defines and Type Definitions
\brief Type definitions and defines for Cortex-M processor based devices.
*/
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CORE Status and Control Registers
\brief Core Register type definitions.
@{
*/
/**
\brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/* APSR Register Definitions */
#define APSR_N_Pos 31U /*!< APSR: N Position */
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
#define APSR_C_Pos 29U /*!< APSR: C Position */
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
#define APSR_V_Pos 28U /*!< APSR: V Position */
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
/**
\brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/* IPSR Register Definitions */
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
/**
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/* xPSR Register Definitions */
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
/**
\brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/* CONTROL Register Definitions */
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
/*@} end of group CMSIS_CORE */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
\brief Type definitions for the NVIC Registers
@{
*/
/**
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31U];
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31U];
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31U];
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31U];
uint32_t RESERVED4[64U];
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCB System Control Block (SCB)
\brief Type definitions for the System Control Block Registers
@{
*/
/**
\brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
\brief Type definitions for the System Control and ID Register not in the SCB
@{
*/
/**
\brief Structure type to access the System Control and ID Register not in the SCB.
*/
typedef struct
{
uint32_t RESERVED0[2U];
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
} SCnSCB_Type;
/* Auxiliary Control Register Definitions */
#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */
#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */
#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */
#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */
/*@} end of group CMSIS_SCnotSCB */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
\brief Type definitions for the System Timer Registers.
@{
*/
/**
\brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
\brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
Therefore they are not covered by the Cortex-M1 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_bitfield Core register bit field macros
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
@{
*/
/**
\brief Mask and shift a bit field value for use in a register bit range.
\param[in] field Name of the register bit field.
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
\return Masked and shifted value.
*/
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
/**
\brief Mask and shift a register value to extract a bit filed value.
\param[in] field Name of the register bit field.
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
\return Masked and shifted bit field value.
*/
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
/*@} end of group CMSIS_core_bitfield */
/**
\ingroup CMSIS_core_register
\defgroup CMSIS_core_base Core Definitions
\brief Definitions for base addresses, unions, and structures.
@{
*/
/* Memory mapping of Core Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
******************************************************************************/
/**
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
*/
/* ########################## NVIC functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
\brief Functions that manage interrupts and exceptions via the NVIC.
@{
*/
#ifdef CMSIS_NVIC_VIRTUAL
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
#endif
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
#define NVIC_EnableIRQ __NVIC_EnableIRQ
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
#define NVIC_DisableIRQ __NVIC_DisableIRQ
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
#define NVIC_SetPriority __NVIC_SetPriority
#define NVIC_GetPriority __NVIC_GetPriority
#define NVIC_SystemReset __NVIC_SystemReset
#endif /* CMSIS_NVIC_VIRTUAL */
#ifdef CMSIS_VECTAB_VIRTUAL
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
#endif
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
#define NVIC_SetVector __NVIC_SetVector
#define NVIC_GetVector __NVIC_GetVector
#endif /* (CMSIS_VECTAB_VIRTUAL) */
#define NVIC_USER_IRQ_OFFSET 16
/* The following EXC_RETURN values are saved the LR on exception entry */
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
/* Interrupt Priorities are WORD accessible only under Armv6-M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
#define __NVIC_SetPriorityGrouping(X) (void)(X)
#define __NVIC_GetPriorityGrouping() (0U)
/**
\brief Enable Interrupt
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Get Interrupt Enable status
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt is not enabled.
\return 1 Interrupt is enabled.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Disable Interrupt
\details Disables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
__DSB();
__ISB();
}
}
/**
\brief Get Pending Interrupt
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
\param [in] IRQn Device specific interrupt number.
\return 0 Interrupt status is not pending.
\return 1 Interrupt status is pending.
\note IRQn must not be negative.
*/
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
}
else
{
return(0U);
}
}
/**
\brief Set Pending Interrupt
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Clear Pending Interrupt
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
}
}
/**
\brief Set Interrupt Priority
\details Sets the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if ((int32_t)(IRQn) >= 0)
{
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
else
{
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
}
}
/**
\brief Get Interrupt Priority
\details Reads the priority of a device specific interrupt or a processor exception.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Interrupt Priority.
Value is aligned automatically to the implemented priority bits of the microcontroller.
*/
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{
if ((int32_t)(IRQn) >= 0)
{
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
else
{
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
}
}
/**
\brief Encode Priority
\details Encodes the priority for an interrupt with the given priority group,
preemptive priority value, and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Used priority group.
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
);
}
/**
\brief Decode Priority
\details Decodes an interrupt priority value with a given priority group to
preemptive priority value and subpriority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
\param [in] PriorityGroup Used priority group.
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
\param [out] pSubPriority Subpriority value (starting from 0).
*/
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
/**
\brief Set Interrupt Vector
\details Sets an interrupt vector in SRAM based interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
Address 0 must be mapped to SRAM.
\param [in] IRQn Interrupt number
\param [in] vector Address of interrupt handler function
*/
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
uint32_t *vectors = (uint32_t *)0x0U;
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
/**
\brief Get Interrupt Vector
\details Reads an interrupt vector from interrupt vector table.
The interrupt number can be positive to specify a device specific interrupt,
or negative to specify a processor exception.
\param [in] IRQn Interrupt number.
\return Address of interrupt handler function
*/
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t *vectors = (uint32_t *)0x0U;
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
}
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
}
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ########################## FPU functions #################################### */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_FpuFunctions FPU Functions
\brief Function that provides FPU type.
@{
*/
/**
\brief get FPU type
\details returns the FPU type
\returns
- \b 0: No FPU
- \b 1: Single precision FPU
- \b 2: Double + Single precision FPU
*/
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
{
return 0U; /* No FPU */
}
/*@} end of CMSIS_Core_FpuFunctions */
/* ################################## SysTick function ############################################ */
/**
\ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
\brief Functions that configure the System.
@{
*/
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
/**
\brief System Tick Configuration
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
Counter is in free running mode to generate periodic interrupts.
\param [in] ticks Number of ticks between two interrupts.
\return 0 Function succeeded.
\return 1 Function failed.
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
{
return (1UL); /* Reload value impossible */
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CM1_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */

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/******************************************************************************
* @file mpu_armv7.h
* @brief CMSIS MPU API for Armv7-M MPU
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV7_H
#define ARM_MPU_ARMV7_H
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
/** MPU Region Base Address Register Value
*
* \param Region The region to be configured, number 0 to 15.
* \param BaseAddress The base address for the region.
*/
#define ARM_MPU_RBAR(Region, BaseAddress) \
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
((Region) & MPU_RBAR_REGION_Msk) | \
(MPU_RBAR_VALID_Msk))
/**
* MPU Memory Access Attributes
*
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
*/
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
(((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
(((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
(((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
(((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk)))
/**
* MPU Region Attribute and Size Register Value
*
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
* \param IsShareable Region is shareable between multiple bus masters.
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
* \param SubRegionDisable Sub-region disable field.
* \param Size Region size of the region to be configured, for example 4K, 8K.
*/
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
/**
* MPU Memory Access Attribute for strongly ordered memory.
* - TEX: 000b
* - Shareable
* - Non-cacheable
* - Non-bufferable
*/
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
/**
* MPU Memory Access Attribute for device memory.
* - TEX: 000b (if non-shareable) or 010b (if shareable)
* - Shareable or non-shareable
* - Non-cacheable
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
*
* \param IsShareable Configures the device memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
/**
* MPU Memory Access Attribute for normal memory.
* - TEX: 1BBb (reflecting outer cacheability rules)
* - Shareable or non-shareable
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
*
* \param OuterCp Configures the outer cache policy.
* \param InnerCp Configures the inner cache policy.
* \param IsShareable Configures the memory as shareable or non-shareable.
*/
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
/**
* MPU Memory Access Attribute non-cacheable policy.
*/
#define ARM_MPU_CACHEP_NOCACHE 0U
/**
* MPU Memory Access Attribute write-back, write and read allocate policy.
*/
#define ARM_MPU_CACHEP_WB_WRA 1U
/**
* MPU Memory Access Attribute write-through, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WT_NWA 2U
/**
* MPU Memory Access Attribute write-back, no write allocate policy.
*/
#define ARM_MPU_CACHEP_WB_NWA 3U
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; //!< The region base address register value (RBAR)
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
MPU->RNR = rnr;
MPU->RASR = 0U;
}
/** Configure an MPU region.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rsar Value for RSAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
MPU->RNR = rnr;
MPU->RBAR = rbar;
MPU->RASR = rasr;
}
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
while (cnt > MPU_TYPE_RALIASES) {
orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
table += MPU_TYPE_RALIASES;
cnt -= MPU_TYPE_RALIASES;
}
orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
}
#endif

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/******************************************************************************
* @file mpu_armv8.h
* @brief CMSIS MPU API for Armv8-M MPU
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef ARM_MPU_ARMV8_H
#define ARM_MPU_ARMV8_H
/** \brief Attribute for device memory (outer only) */
#define ARM_MPU_ATTR_DEVICE ( 0U )
/** \brief Attribute for non-cacheable, normal memory */
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
/** \brief Attribute for normal memory (outer and inner)
* \param NT Non-Transient: Set to 1 for non-transient data.
* \param WB Write-Back: Set to 1 to use write-back update policy.
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
*/
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
/** \brief Memory Attribute
* \param O Outer memory attributes
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
*/
#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
/** \brief Normal memory non-shareable */
#define ARM_MPU_SH_NON (0U)
/** \brief Normal memory outer shareable */
#define ARM_MPU_SH_OUTER (2U)
/** \brief Normal memory inner shareable */
#define ARM_MPU_SH_INNER (3U)
/** \brief Memory access permissions
* \param RO Read-Only: Set to 1 for read-only memory.
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
*/
#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
/** \brief Region Base Address Register value
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
* \param SH Defines the Shareability domain for this memory region.
* \param RO Read-Only: Set to 1 for a read-only memory region.
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
*/
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
((BASE & MPU_RBAR_BASE_Msk) | \
((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
/** \brief Region Limit Address Register value
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
* \param IDX The attribute index to be associated with this memory region.
*/
#define ARM_MPU_RLAR(LIMIT, IDX) \
((LIMIT & MPU_RLAR_LIMIT_Msk) | \
((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
(MPU_RLAR_EN_Msk))
/**
* Struct for a single MPU Region
*/
typedef struct {
uint32_t RBAR; /*!< Region Base Address Register value */
uint32_t RLAR; /*!< Region Limit Address Register value */
} ARM_MPU_Region_t;
/** Enable the MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#ifdef MPU_NS
/** Enable the Non-secure MPU.
* \param MPU_Control Default access permissions for unconfigured regions.
*/
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
{
__DSB();
__ISB();
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}
/** Disable the Non-secure MPU.
*/
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
{
__DSB();
__ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
}
#endif
/** Set the memory attribute encoding to the given MPU.
* \param mpu Pointer to the MPU to be configured.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
{
const uint8_t reg = idx / 4U;
const uint32_t pos = ((idx % 4U) * 8U);
const uint32_t mask = 0xFFU << pos;
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
return; // invalid index
}
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}
/** Set the memory attribute encoding.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}
#ifdef MPU_NS
/** Set the memory attribute encoding to the Non-secure MPU.
* \param idx The attribute index to be set [0-7]
* \param attr The attribute value to be set.
*/
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
{
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
}
#endif
/** Clear and disable the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
{
mpu->RNR = rnr;
mpu->RLAR = 0U;
}
/** Clear and disable the given MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU, rnr);
}
#ifdef MPU_NS
/** Clear and disable the given Non-secure MPU region.
* \param rnr Region number to be cleared.
*/
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
{
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
}
#endif
/** Configure the given MPU region of the given MPU.
* \param mpu Pointer to MPU to be used.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
mpu->RNR = rnr;
mpu->RBAR = rbar;
mpu->RLAR = rlar;
}
/** Configure the given MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}
#ifdef MPU_NS
/** Configure the given Non-secure MPU region.
* \param rnr Region number to be configured.
* \param rbar Value for RBAR register.
* \param rlar Value for RLAR register.
*/
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
{
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
}
#endif
/** Memcopy with strictly ordered memory access, e.g. for register targets.
* \param dst Destination data is copied to.
* \param src Source data is copied from.
* \param len Amount of data words to be copied.
*/
__STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
{
uint32_t i;
for (i = 0U; i < len; ++i)
{
dst[i] = src[i];
}
}
/** Load the given number of MPU regions from a table to the given MPU.
* \param mpu Pointer to the MPU registers to be used.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
if (cnt == 1U) {
mpu->RNR = rnr;
orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
} else {
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
table += c;
cnt -= c;
rnrOffset = 0U;
rnrBase += MPU_TYPE_RALIASES;
mpu->RNR = rnrBase;
}
orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
}
}
/** Load the given number of MPU regions from a table.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}
#ifdef MPU_NS
/** Load the given number of MPU regions from a table to the Non-secure MPU.
* \param rnr First region number to be configured.
* \param table Pointer to the MPU configuration table.
* \param cnt Amount of regions to be configured.
*/
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
{
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
}
#endif
#endif

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/******************************************************************************
* @file tz_context.h
* @brief Context Management for Armv8-M TrustZone
* @version V1.0.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2017-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef TZ_CONTEXT_H
#define TZ_CONTEXT_H
#include <stdint.h>
#ifndef TZ_MODULEID_T
#define TZ_MODULEID_T
/// \details Data type that identifies secure software modules called by a process.
typedef uint32_t TZ_ModuleId_t;
#endif
/// \details TZ Memory ID identifies an allocated memory slot.
typedef uint32_t TZ_MemoryId_t;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
uint32_t TZ_InitContextSystem_S (void);
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
#endif // TZ_CONTEXT_H

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/******************************************************************************
* @file main_s.c
* @brief Code template for secure main function
* @version V1.1.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2013-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Use CMSE intrinsics */
#include <arm_cmse.h>
#include "RTE_Components.h"
#include CMSIS_device_header
/* TZ_START_NS: Start address of non-secure application */
#ifndef TZ_START_NS
#define TZ_START_NS (0x200000U)
#endif
/* typedef for non-secure callback functions */
typedef void (*funcptr_void) (void) __attribute__((cmse_nonsecure_call));
/* Secure main() */
int main(void) {
funcptr_void NonSecure_ResetHandler;
/* Add user setup code for secure part here*/
/* Set non-secure main stack (MSP_NS) */
__TZ_set_MSP_NS(*((uint32_t *)(TZ_START_NS)));
/* Get non-secure reset handler */
NonSecure_ResetHandler = (funcptr_void)(*((uint32_t *)((TZ_START_NS) + 4U)));
/* Start non-secure state software application */
NonSecure_ResetHandler();
/* Non-secure software does not return, this code is not executed */
while (1) {
__NOP();
}
}

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/******************************************************************************
* @file tz_context.c
* @brief Context Management for Armv8-M TrustZone - Sample implementation
* @version V1.1.1
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2016-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "RTE_Components.h"
#include CMSIS_device_header
#include "tz_context.h"
/// Number of process slots (threads may call secure library code)
#ifndef TZ_PROCESS_STACK_SLOTS
#define TZ_PROCESS_STACK_SLOTS 8U
#endif
/// Stack size of the secure library code
#ifndef TZ_PROCESS_STACK_SIZE
#define TZ_PROCESS_STACK_SIZE 256U
#endif
typedef struct {
uint32_t sp_top; // stack space top
uint32_t sp_limit; // stack space limit
uint32_t sp; // current stack pointer
} stack_info_t;
static stack_info_t ProcessStackInfo [TZ_PROCESS_STACK_SLOTS];
static uint64_t ProcessStackMemory[TZ_PROCESS_STACK_SLOTS][TZ_PROCESS_STACK_SIZE/8U];
static uint32_t ProcessStackFreeSlot = 0xFFFFFFFFU;
/// Initialize secure context memory system
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_InitContextSystem_S (void) {
uint32_t n;
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
for (n = 0U; n < TZ_PROCESS_STACK_SLOTS; n++) {
ProcessStackInfo[n].sp = 0U;
ProcessStackInfo[n].sp_limit = (uint32_t)&ProcessStackMemory[n];
ProcessStackInfo[n].sp_top = (uint32_t)&ProcessStackMemory[n] + TZ_PROCESS_STACK_SIZE;
*((uint32_t *)ProcessStackMemory[n]) = n + 1U;
}
*((uint32_t *)ProcessStackMemory[--n]) = 0xFFFFFFFFU;
ProcessStackFreeSlot = 0U;
// Default process stack pointer and stack limit
__set_PSPLIM((uint32_t)ProcessStackMemory);
__set_PSP ((uint32_t)ProcessStackMemory);
// Privileged Thread Mode using PSP
__set_CONTROL(0x02U);
return 1U; // Success
}
/// Allocate context memory for calling secure software modules in TrustZone
/// \param[in] module identifies software modules called from non-secure mode
/// \return value != 0 id TrustZone memory slot identifier
/// \return value 0 no memory available or internal error
__attribute__((cmse_nonsecure_entry))
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module) {
uint32_t slot;
(void)module; // Ignore (fixed Stack size)
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
if (ProcessStackFreeSlot == 0xFFFFFFFFU) {
return 0U; // No slot available
}
slot = ProcessStackFreeSlot;
ProcessStackFreeSlot = *((uint32_t *)ProcessStackMemory[slot]);
ProcessStackInfo[slot].sp = ProcessStackInfo[slot].sp_top;
return (slot + 1U);
}
/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id) {
uint32_t slot;
if (__get_IPSR() == 0U) {
return 0U; // Thread Mode
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
ProcessStackInfo[slot].sp = 0U;
*((uint32_t *)ProcessStackMemory[slot]) = ProcessStackFreeSlot;
ProcessStackFreeSlot = slot;
return 1U; // Success
}
/// Load secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id) {
uint32_t slot;
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
return 0U; // Thread Mode or using Main Stack for threads
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
// Setup process stack pointer and stack limit
__set_PSPLIM(ProcessStackInfo[slot].sp_limit);
__set_PSP (ProcessStackInfo[slot].sp);
return 1U; // Success
}
/// Store secure context (called on RTOS thread context switch)
/// \param[in] id TrustZone memory slot identifier
/// \return execution status (1: success, 0: error)
__attribute__((cmse_nonsecure_entry))
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id) {
uint32_t slot;
uint32_t sp;
if ((__get_IPSR() == 0U) || ((__get_CONTROL() & 2U) == 0U)) {
return 0U; // Thread Mode or using Main Stack for threads
}
if ((id == 0U) || (id > TZ_PROCESS_STACK_SLOTS)) {
return 0U; // Invalid ID
}
slot = id - 1U;
if (ProcessStackInfo[slot].sp == 0U) {
return 0U; // Inactive slot
}
sp = __get_PSP();
if ((sp < ProcessStackInfo[slot].sp_limit) ||
(sp > ProcessStackInfo[slot].sp_top)) {
return 0U; // SP out of range
}
ProcessStackInfo[slot].sp = sp;
// Default process stack pointer and stack limit
__set_PSPLIM((uint32_t)ProcessStackMemory);
__set_PSP ((uint32_t)ProcessStackMemory);
return 1U; // Success
}

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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.0.2
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
#endif
/* CMSIS compiler control architecture macros */
#if (defined (__TARGET_ARCH_7_A ) && (__TARGET_ARCH_7_A == 1))
#define __ARM_ARCH_7A__ 1
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE __forceinline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE static __forceinline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __declspec(noreturn)
#endif
#ifndef CMSIS_DEPRECATED
#define CMSIS_DEPRECATED __attribute__((deprecated))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT __packed struct
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
/* ########################## Core Instruction Access ######################### */
/**
\brief No Operation
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
*/
#define __WFI __wfi
/**
\brief Wait For Event
*/
#define __WFE __wfe
/**
\brief Send Event
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/**
\brief Count leading zeros
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/* ########################### Core Function Access ########################### */
/**
\brief Get FPSCR (Floating Point Status/Control)
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR (Floating Point Status/Control)
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#else
(void)fpscr;
#endif
}
/** \brief Get CPSR (Current Program Status Register)
\return CPSR Register value
*/
__STATIC_INLINE uint32_t __get_CPSR(void)
{
register uint32_t __regCPSR __ASM("cpsr");
return(__regCPSR);
}
/** \brief Set CPSR (Current Program Status Register)
\param [in] cpsr CPSR value to set
*/
__STATIC_INLINE void __set_CPSR(uint32_t cpsr)
{
register uint32_t __regCPSR __ASM("cpsr");
__regCPSR = cpsr;
}
/** \brief Get Mode
\return Processor Mode
*/
__STATIC_INLINE uint32_t __get_mode(void)
{
return (__get_CPSR() & 0x1FU);
}
/** \brief Set Mode
\param [in] mode Mode value to set
*/
__STATIC_INLINE __ASM void __set_mode(uint32_t mode)
{
MOV r1, lr
MSR CPSR_C, r0
BX r1
}
/** \brief Get Stack Pointer
\return Stack Pointer
*/
__STATIC_INLINE __ASM uint32_t __get_SP(void)
{
MOV r0, sp
BX lr
}
/** \brief Set Stack Pointer
\param [in] stack Stack Pointer value to set
*/
__STATIC_INLINE __ASM void __set_SP(uint32_t stack)
{
MOV sp, r0
BX lr
}
/** \brief Get USR/SYS Stack Pointer
\return USR/SYSStack Pointer
*/
__STATIC_INLINE __ASM uint32_t __get_SP_usr(void)
{
ARM
PRESERVE8
MRS R1, CPSR
CPS #0x1F ;no effect in USR mode
MOV R0, SP
MSR CPSR_c, R1 ;no effect in USR mode
ISB
BX LR
}
/** \brief Set USR/SYS Stack Pointer
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
__STATIC_INLINE __ASM void __set_SP_usr(uint32_t topOfProcStack)
{
ARM
PRESERVE8
MRS R1, CPSR
CPS #0x1F ;no effect in USR mode
MOV SP, R0
MSR CPSR_c, R1 ;no effect in USR mode
ISB
BX LR
}
/** \brief Get FPEXC (Floating Point Exception Control Register)
\return Floating Point Exception Control Register value
*/
__STATIC_INLINE uint32_t __get_FPEXC(void)
{
#if (__FPU_PRESENT == 1)
register uint32_t __regfpexc __ASM("fpexc");
return(__regfpexc);
#else
return(0);
#endif
}
/** \brief Set FPEXC (Floating Point Exception Control Register)
\param [in] fpexc Floating Point Exception Control value to set
*/
__STATIC_INLINE void __set_FPEXC(uint32_t fpexc)
{
#if (__FPU_PRESENT == 1)
register uint32_t __regfpexc __ASM("fpexc");
__regfpexc = (fpexc);
#endif
}
/*
* Include common core functions to access Coprocessor 15 registers
*/
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); (Rt) = tmp; } while(0)
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) do { register volatile uint32_t tmp __ASM("cp" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2); tmp = (Rt); } while(0)
#define __get_CP64(cp, op1, Rt, CRm) \
do { \
uint32_t ltmp, htmp; \
__ASM volatile("MRRC p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
(Rt) = ((((uint64_t)htmp) << 32U) | ((uint64_t)ltmp)); \
} while(0)
#define __set_CP64(cp, op1, Rt, CRm) \
do { \
const uint64_t tmp = (Rt); \
const uint32_t ltmp = (uint32_t)(tmp); \
const uint32_t htmp = (uint32_t)(tmp >> 32U); \
__ASM volatile("MCRR p" # cp ", " # op1 ", ltmp, htmp, c" # CRm); \
} while(0)
#include "cmsis_cp15.h"
/** \brief Enable Floating Point Unit
Critical section, called from undef handler, so systick is disabled
*/
__STATIC_INLINE __ASM void __FPU_Enable(void)
{
ARM
//Permit access to VFP/NEON, registers by modifying CPACR
MRC p15,0,R1,c1,c0,2
ORR R1,R1,#0x00F00000
MCR p15,0,R1,c1,c0,2
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
ISB
//Enable VFP/NEON
VMRS R1,FPEXC
ORR R1,R1,#0x40000000
VMSR FPEXC,R1
//Initialise VFP/NEON registers to 0
MOV R2,#0
//Initialise D16 registers to 0
VMOV D0, R2,R2
VMOV D1, R2,R2
VMOV D2, R2,R2
VMOV D3, R2,R2
VMOV D4, R2,R2
VMOV D5, R2,R2
VMOV D6, R2,R2
VMOV D7, R2,R2
VMOV D8, R2,R2
VMOV D9, R2,R2
VMOV D10,R2,R2
VMOV D11,R2,R2
VMOV D12,R2,R2
VMOV D13,R2,R2
VMOV D14,R2,R2
VMOV D15,R2,R2
IF {TARGET_FEATURE_EXTENSION_REGISTER_COUNT} == 32
//Initialise D32 registers to 0
VMOV D16,R2,R2
VMOV D17,R2,R2
VMOV D18,R2,R2
VMOV D19,R2,R2
VMOV D20,R2,R2
VMOV D21,R2,R2
VMOV D22,R2,R2
VMOV D23,R2,R2
VMOV D24,R2,R2
VMOV D25,R2,R2
VMOV D26,R2,R2
VMOV D27,R2,R2
VMOV D28,R2,R2
VMOV D29,R2,R2
VMOV D30,R2,R2
VMOV D31,R2,R2
ENDIF
//Initialise FPSCR to a known state
VMRS R2,FPSCR
LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
AND R2,R2,R3
VMSR FPSCR,R2
BX LR
}
#endif /* __CMSIS_ARMCC_H */

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/**************************************************************************//**
* @file cmsis_armclang.h
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.0.2
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_ARMCLANG_H
#define __CMSIS_ARMCLANG_H
#pragma clang system_header /* treat file as system include file */
#ifndef __ARM_COMPAT_H
#include <arm_compat.h> /* Compatibility header for Arm Compiler 5 intrinsics */
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE __inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE __attribute__((always_inline))
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static __inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__))
#endif
#ifndef CMSIS_DEPRECATED
#define CMSIS_DEPRECATED __attribute__((deprecated))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#pragma clang diagnostic pop
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
/* ########################## Core Instruction Access ######################### */
/**
\brief No Operation
*/
#define __NOP __builtin_arm_nop
/**
\brief Wait For Interrupt
*/
#define __WFI __builtin_arm_wfi
/**
\brief Wait For Event
*/
#define __WFE __builtin_arm_wfe
/**
\brief Send Event
*/
#define __SEV __builtin_arm_sev
/**
\brief Instruction Synchronization Barrier
*/
#define __ISB() do {\
__schedule_barrier();\
__builtin_arm_isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
*/
#define __DSB() do {\
__schedule_barrier();\
__builtin_arm_dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
*/
#define __DMB() do {\
__schedule_barrier();\
__builtin_arm_dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV(value) __builtin_bswap32(value)
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV16(value) __ROR(__REV(value), 16)
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REVSH(value) (int16_t)__builtin_bswap16(value)
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
op2 %= 32U;
if (op2 == 0U)
{
return op1;
}
return (op1 >> op2) | (op1 << (32U - op2));
}
/**
\brief Breakpoint
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
/**
\brief Reverse bit order of value
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __builtin_arm_rbit
/**
\brief Count leading zeros
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ (uint8_t)__builtin_clz
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB (uint8_t)__builtin_arm_ldrex
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH (uint16_t)__builtin_arm_ldrex
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW (uint32_t)__builtin_arm_ldrex
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB (uint32_t)__builtin_arm_strex
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH (uint32_t)__builtin_arm_strex
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW (uint32_t)__builtin_arm_strex
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __builtin_arm_clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __builtin_arm_ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __builtin_arm_usat
/* ########################### Core Function Access ########################### */
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
#define __get_FPSCR __builtin_arm_get_fpscr
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
#define __set_FPSCR __builtin_arm_set_fpscr
/** \brief Get CPSR Register
\return CPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, cpsr" : "=r" (result) );
return(result);
}
/** \brief Set CPSR Register
\param [in] cpsr CPSR value to set
*/
__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
{
__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
}
/** \brief Get Mode
\return Processor Mode
*/
__STATIC_FORCEINLINE uint32_t __get_mode(void)
{
return (__get_CPSR() & 0x1FU);
}
/** \brief Set Mode
\param [in] mode Mode value to set
*/
__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
{
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
}
/** \brief Get Stack Pointer
\return Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP()
{
uint32_t result;
__ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
return result;
}
/** \brief Set Stack Pointer
\param [in] stack Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
{
__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
}
/** \brief Get USR/SYS Stack Pointer
\return USR/SYS Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP_usr()
{
uint32_t cpsr;
uint32_t result;
__ASM volatile(
"MRS %0, cpsr \n"
"CPS #0x1F \n" // no effect in USR mode
"MOV %1, sp \n"
"MSR cpsr_c, %2 \n" // no effect in USR mode
"ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
);
return result;
}
/** \brief Set USR/SYS Stack Pointer
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
{
uint32_t cpsr;
__ASM volatile(
"MRS %0, cpsr \n"
"CPS #0x1F \n" // no effect in USR mode
"MOV sp, %1 \n"
"MSR cpsr_c, %2 \n" // no effect in USR mode
"ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
);
}
/** \brief Get FPEXC
\return Floating Point Exception Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
{
#if (__FPU_PRESENT == 1)
uint32_t result;
__ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPEXC
\param [in] fpexc Floating Point Exception Control value to set
*/
__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
{
#if (__FPU_PRESENT == 1)
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
#endif
}
/*
* Include common core functions to access Coprocessor 15 registers
*/
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
#include "cmsis_cp15.h"
/** \brief Enable Floating Point Unit
Critical section, called from undef handler, so systick is disabled
*/
__STATIC_INLINE void __FPU_Enable(void)
{
__ASM volatile(
//Permit access to VFP/NEON, registers by modifying CPACR
" MRC p15,0,R1,c1,c0,2 \n"
" ORR R1,R1,#0x00F00000 \n"
" MCR p15,0,R1,c1,c0,2 \n"
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
" ISB \n"
//Enable VFP/NEON
" VMRS R1,FPEXC \n"
" ORR R1,R1,#0x40000000 \n"
" VMSR FPEXC,R1 \n"
//Initialise VFP/NEON registers to 0
" MOV R2,#0 \n"
//Initialise D16 registers to 0
" VMOV D0, R2,R2 \n"
" VMOV D1, R2,R2 \n"
" VMOV D2, R2,R2 \n"
" VMOV D3, R2,R2 \n"
" VMOV D4, R2,R2 \n"
" VMOV D5, R2,R2 \n"
" VMOV D6, R2,R2 \n"
" VMOV D7, R2,R2 \n"
" VMOV D8, R2,R2 \n"
" VMOV D9, R2,R2 \n"
" VMOV D10,R2,R2 \n"
" VMOV D11,R2,R2 \n"
" VMOV D12,R2,R2 \n"
" VMOV D13,R2,R2 \n"
" VMOV D14,R2,R2 \n"
" VMOV D15,R2,R2 \n"
#if __ARM_NEON == 1
//Initialise D32 registers to 0
" VMOV D16,R2,R2 \n"
" VMOV D17,R2,R2 \n"
" VMOV D18,R2,R2 \n"
" VMOV D19,R2,R2 \n"
" VMOV D20,R2,R2 \n"
" VMOV D21,R2,R2 \n"
" VMOV D22,R2,R2 \n"
" VMOV D23,R2,R2 \n"
" VMOV D24,R2,R2 \n"
" VMOV D25,R2,R2 \n"
" VMOV D26,R2,R2 \n"
" VMOV D27,R2,R2 \n"
" VMOV D28,R2,R2 \n"
" VMOV D29,R2,R2 \n"
" VMOV D30,R2,R2 \n"
" VMOV D31,R2,R2 \n"
#endif
//Initialise FPSCR to a known state
" VMRS R2,FPSCR \n"
" LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
" AND R2,R2,R3 \n"
" VMSR FPSCR,R2 "
);
}
#endif /* __CMSIS_ARMCLANG_H */

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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.0.2
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include "cmsis_iccarm.h"
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef CMSIS_DEPRECATED
#define CMSIS_DEPRECATED __attribute__((deprecated))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __UNALIGNED_UINT32
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef CMSIS_DEPRECATED
#define CMSIS_DEPRECATED __attribute__((deprecated))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __UNALIGNED_UINT32
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef CMSIS_DEPRECATED
#warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored.
#define CMSIS_DEPRECATED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __UNALIGNED_UINT32
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */

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/**************************************************************************//**
* @file cmsis_cp15.h
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.0.1
* @date 07. Sep 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_CP15_H
#define __CMSIS_CP15_H
/** \brief Get ACTLR
\return Auxiliary Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_ACTLR(void)
{
uint32_t result;
__get_CP(15, 0, result, 1, 0, 1);
return(result);
}
/** \brief Set ACTLR
\param [in] actlr Auxiliary Control value to set
*/
__STATIC_FORCEINLINE void __set_ACTLR(uint32_t actlr)
{
__set_CP(15, 0, actlr, 1, 0, 1);
}
/** \brief Get CPACR
\return Coprocessor Access Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_CPACR(void)
{
uint32_t result;
__get_CP(15, 0, result, 1, 0, 2);
return result;
}
/** \brief Set CPACR
\param [in] cpacr Coprocessor Access Control value to set
*/
__STATIC_FORCEINLINE void __set_CPACR(uint32_t cpacr)
{
__set_CP(15, 0, cpacr, 1, 0, 2);
}
/** \brief Get DFSR
\return Data Fault Status Register value
*/
__STATIC_FORCEINLINE uint32_t __get_DFSR(void)
{
uint32_t result;
__get_CP(15, 0, result, 5, 0, 0);
return result;
}
/** \brief Set DFSR
\param [in] dfsr Data Fault Status value to set
*/
__STATIC_FORCEINLINE void __set_DFSR(uint32_t dfsr)
{
__set_CP(15, 0, dfsr, 5, 0, 0);
}
/** \brief Get IFSR
\return Instruction Fault Status Register value
*/
__STATIC_FORCEINLINE uint32_t __get_IFSR(void)
{
uint32_t result;
__get_CP(15, 0, result, 5, 0, 1);
return result;
}
/** \brief Set IFSR
\param [in] ifsr Instruction Fault Status value to set
*/
__STATIC_FORCEINLINE void __set_IFSR(uint32_t ifsr)
{
__set_CP(15, 0, ifsr, 5, 0, 1);
}
/** \brief Get ISR
\return Interrupt Status Register value
*/
__STATIC_FORCEINLINE uint32_t __get_ISR(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 1, 0);
return result;
}
/** \brief Get CBAR
\return Configuration Base Address register value
*/
__STATIC_FORCEINLINE uint32_t __get_CBAR(void)
{
uint32_t result;
__get_CP(15, 4, result, 15, 0, 0);
return result;
}
/** \brief Get TTBR0
This function returns the value of the Translation Table Base Register 0.
\return Translation Table Base Register 0 value
*/
__STATIC_FORCEINLINE uint32_t __get_TTBR0(void)
{
uint32_t result;
__get_CP(15, 0, result, 2, 0, 0);
return result;
}
/** \brief Set TTBR0
This function assigns the given value to the Translation Table Base Register 0.
\param [in] ttbr0 Translation Table Base Register 0 value to set
*/
__STATIC_FORCEINLINE void __set_TTBR0(uint32_t ttbr0)
{
__set_CP(15, 0, ttbr0, 2, 0, 0);
}
/** \brief Get DACR
This function returns the value of the Domain Access Control Register.
\return Domain Access Control Register value
*/
__STATIC_FORCEINLINE uint32_t __get_DACR(void)
{
uint32_t result;
__get_CP(15, 0, result, 3, 0, 0);
return result;
}
/** \brief Set DACR
This function assigns the given value to the Domain Access Control Register.
\param [in] dacr Domain Access Control Register value to set
*/
__STATIC_FORCEINLINE void __set_DACR(uint32_t dacr)
{
__set_CP(15, 0, dacr, 3, 0, 0);
}
/** \brief Set SCTLR
This function assigns the given value to the System Control Register.
\param [in] sctlr System Control Register value to set
*/
__STATIC_FORCEINLINE void __set_SCTLR(uint32_t sctlr)
{
__set_CP(15, 0, sctlr, 1, 0, 0);
}
/** \brief Get SCTLR
\return System Control Register value
*/
__STATIC_FORCEINLINE uint32_t __get_SCTLR(void)
{
uint32_t result;
__get_CP(15, 0, result, 1, 0, 0);
return result;
}
/** \brief Set ACTRL
\param [in] actrl Auxiliary Control Register value to set
*/
__STATIC_FORCEINLINE void __set_ACTRL(uint32_t actrl)
{
__set_CP(15, 0, actrl, 1, 0, 1);
}
/** \brief Get ACTRL
\return Auxiliary Control Register value
*/
__STATIC_FORCEINLINE uint32_t __get_ACTRL(void)
{
uint32_t result;
__get_CP(15, 0, result, 1, 0, 1);
return result;
}
/** \brief Get MPIDR
This function returns the value of the Multiprocessor Affinity Register.
\return Multiprocessor Affinity Register value
*/
__STATIC_FORCEINLINE uint32_t __get_MPIDR(void)
{
uint32_t result;
__get_CP(15, 0, result, 0, 0, 5);
return result;
}
/** \brief Get VBAR
This function returns the value of the Vector Base Address Register.
\return Vector Base Address Register
*/
__STATIC_FORCEINLINE uint32_t __get_VBAR(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 0, 0);
return result;
}
/** \brief Set VBAR
This function assigns the given value to the Vector Base Address Register.
\param [in] vbar Vector Base Address Register value to set
*/
__STATIC_FORCEINLINE void __set_VBAR(uint32_t vbar)
{
__set_CP(15, 0, vbar, 12, 0, 0);
}
/** \brief Get MVBAR
This function returns the value of the Monitor Vector Base Address Register.
\return Monitor Vector Base Address Register
*/
__STATIC_FORCEINLINE uint32_t __get_MVBAR(void)
{
uint32_t result;
__get_CP(15, 0, result, 12, 0, 1);
return result;
}
/** \brief Set MVBAR
This function assigns the given value to the Monitor Vector Base Address Register.
\param [in] mvbar Monitor Vector Base Address Register value to set
*/
__STATIC_FORCEINLINE void __set_MVBAR(uint32_t mvbar)
{
__set_CP(15, 0, mvbar, 12, 0, 1);
}
#if (defined(__CORTEX_A) && (__CORTEX_A == 7U) && \
defined(__TIM_PRESENT) && (__TIM_PRESENT == 1U)) || \
defined(DOXYGEN)
/** \brief Set CNTFRQ
This function assigns the given value to PL1 Physical Timer Counter Frequency Register (CNTFRQ).
\param [in] value CNTFRQ Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTFRQ(uint32_t value)
{
__set_CP(15, 0, value, 14, 0, 0);
}
/** \brief Get CNTFRQ
This function returns the value of the PL1 Physical Timer Counter Frequency Register (CNTFRQ).
\return CNTFRQ Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CNTFRQ(void)
{
uint32_t result;
__get_CP(15, 0, result, 14, 0 , 0);
return result;
}
/** \brief Set CNTP_TVAL
This function assigns the given value to PL1 Physical Timer Value Register (CNTP_TVAL).
\param [in] value CNTP_TVAL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTP_TVAL(uint32_t value)
{
__set_CP(15, 0, value, 14, 2, 0);
}
/** \brief Get CNTP_TVAL
This function returns the value of the PL1 Physical Timer Value Register (CNTP_TVAL).
\return CNTP_TVAL Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CNTP_TVAL(void)
{
uint32_t result;
__get_CP(15, 0, result, 14, 2, 0);
return result;
}
/** \brief Get CNTPCT
This function returns the value of the 64 bits PL1 Physical Count Register (CNTPCT).
\return CNTPCT Register value
*/
__STATIC_FORCEINLINE uint64_t __get_CNTPCT(void)
{
uint64_t result;
__get_CP64(15, 0, result, 14);
return result;
}
/** \brief Set CNTP_CVAL
This function assigns the given value to 64bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
\param [in] value CNTP_CVAL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTP_CVAL(uint64_t value)
{
__set_CP64(15, 2, value, 14);
}
/** \brief Get CNTP_CVAL
This function returns the value of the 64 bits PL1 Physical Timer CompareValue Register (CNTP_CVAL).
\return CNTP_CVAL Register value
*/
__STATIC_FORCEINLINE uint64_t __get_CNTP_CVAL(void)
{
uint64_t result;
__get_CP64(15, 2, result, 14);
return result;
}
/** \brief Set CNTP_CTL
This function assigns the given value to PL1 Physical Timer Control Register (CNTP_CTL).
\param [in] value CNTP_CTL Register value to set
*/
__STATIC_FORCEINLINE void __set_CNTP_CTL(uint32_t value)
{
__set_CP(15, 0, value, 14, 2, 1);
}
/** \brief Get CNTP_CTL register
\return CNTP_CTL Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CNTP_CTL(void)
{
uint32_t result;
__get_CP(15, 0, result, 14, 2, 1);
return result;
}
#endif
/** \brief Set TLBIALL
TLB Invalidate All
*/
__STATIC_FORCEINLINE void __set_TLBIALL(uint32_t value)
{
__set_CP(15, 0, value, 8, 7, 0);
}
/** \brief Set BPIALL.
Branch Predictor Invalidate All
*/
__STATIC_FORCEINLINE void __set_BPIALL(uint32_t value)
{
__set_CP(15, 0, value, 7, 5, 6);
}
/** \brief Set ICIALLU
Instruction Cache Invalidate All
*/
__STATIC_FORCEINLINE void __set_ICIALLU(uint32_t value)
{
__set_CP(15, 0, value, 7, 5, 0);
}
/** \brief Set DCCMVAC
Data cache clean
*/
__STATIC_FORCEINLINE void __set_DCCMVAC(uint32_t value)
{
__set_CP(15, 0, value, 7, 10, 1);
}
/** \brief Set DCIMVAC
Data cache invalidate
*/
__STATIC_FORCEINLINE void __set_DCIMVAC(uint32_t value)
{
__set_CP(15, 0, value, 7, 6, 1);
}
/** \brief Set DCCIMVAC
Data cache clean and invalidate
*/
__STATIC_FORCEINLINE void __set_DCCIMVAC(uint32_t value)
{
__set_CP(15, 0, value, 7, 14, 1);
}
/** \brief Set CSSELR
*/
__STATIC_FORCEINLINE void __set_CSSELR(uint32_t value)
{
// __ASM volatile("MCR p15, 2, %0, c0, c0, 0" : : "r"(value) : "memory");
__set_CP(15, 2, value, 0, 0, 0);
}
/** \brief Get CSSELR
\return CSSELR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CSSELR(void)
{
uint32_t result;
// __ASM volatile("MRC p15, 2, %0, c0, c0, 0" : "=r"(result) : : "memory");
__get_CP(15, 2, result, 0, 0, 0);
return result;
}
/** \brief Set CCSIDR
\deprecated CCSIDR itself is read-only. Use __set_CSSELR to select cache level instead.
*/
CMSIS_DEPRECATED
__STATIC_FORCEINLINE void __set_CCSIDR(uint32_t value)
{
__set_CSSELR(value);
}
/** \brief Get CCSIDR
\return CCSIDR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CCSIDR(void)
{
uint32_t result;
// __ASM volatile("MRC p15, 1, %0, c0, c0, 0" : "=r"(result) : : "memory");
__get_CP(15, 1, result, 0, 0, 0);
return result;
}
/** \brief Get CLIDR
\return CLIDR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CLIDR(void)
{
uint32_t result;
// __ASM volatile("MRC p15, 1, %0, c0, c0, 1" : "=r"(result) : : "memory");
__get_CP(15, 1, result, 0, 0, 1);
return result;
}
/** \brief Set DCISW
*/
__STATIC_FORCEINLINE void __set_DCISW(uint32_t value)
{
// __ASM volatile("MCR p15, 0, %0, c7, c6, 2" : : "r"(value) : "memory")
__set_CP(15, 0, value, 7, 6, 2);
}
/** \brief Set DCCSW
*/
__STATIC_FORCEINLINE void __set_DCCSW(uint32_t value)
{
// __ASM volatile("MCR p15, 0, %0, c7, c10, 2" : : "r"(value) : "memory")
__set_CP(15, 0, value, 7, 10, 2);
}
/** \brief Set DCCISW
*/
__STATIC_FORCEINLINE void __set_DCCISW(uint32_t value)
{
// __ASM volatile("MCR p15, 0, %0, c7, c14, 2" : : "r"(value) : "memory")
__set_CP(15, 0, value, 7, 14, 2);
}
#endif

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/**************************************************************************//**
* @file cmsis_gcc.h
* @brief CMSIS compiler specific macros, functions, instructions
* @version V1.0.2
* @date 09. April 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_GCC_H
#define __CMSIS_GCC_H
/* ignore some GCC warnings */
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wsign-conversion"
#pragma GCC diagnostic ignored "-Wconversion"
#pragma GCC diagnostic ignored "-Wunused-parameter"
/* Fallback for __has_builtin */
#ifndef __has_builtin
#define __has_builtin(x) (0)
#endif
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE __attribute__((always_inline))
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((__noreturn__))
#endif
#ifndef CMSIS_DEPRECATED
#define CMSIS_DEPRECATED __attribute__((deprecated))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpacked"
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#pragma GCC diagnostic pop
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
/* ########################## Core Instruction Access ######################### */
/**
\brief No Operation
*/
#define __NOP() __ASM volatile ("nop")
/**
\brief Wait For Interrupt
*/
#define __WFI() __ASM volatile ("wfi")
/**
\brief Wait For Event
*/
#define __WFE() __ASM volatile ("wfe")
/**
\brief Send Event
*/
#define __SEV() __ASM volatile ("sev")
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
__STATIC_FORCEINLINE void __ISB(void)
{
__ASM volatile ("isb 0xF":::"memory");
}
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__STATIC_FORCEINLINE void __DSB(void)
{
__ASM volatile ("dsb 0xF":::"memory");
}
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__STATIC_FORCEINLINE void __DMB(void)
{
__ASM volatile ("dmb 0xF":::"memory");
}
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
\param [in] value Value to reverse
\return Reversed value
*/
__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return result;
#endif
}
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile("rev16 %0, %1" : "=r" (result) : "r" (value));
return result;
}
#endif
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
\param [in] value Value to reverse
\return Reversed value
*/
__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (int16_t)__builtin_bswap16(value);
#else
int16_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return result;
#endif
}
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] op1 Value to rotate
\param [in] op2 Number of Bits to rotate
\return Rotated value
*/
__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
op2 %= 32U;
if (op2 == 0U) {
return op1;
}
return (op1 >> op2) | (op1 << (32U - op2));
}
/**
\brief Breakpoint
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
#else
int32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
}
/**
\brief Count leading zeros
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ (uint8_t)__builtin_clz
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint8_t) result); /* Add explicit type cast here */
}
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return ((uint16_t) result); /* Add explicit type cast here */
}
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
return(result);
}
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
__STATIC_FORCEINLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
__extension__ \
({ \
int32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
__extension__ \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/* ########################### Core Function Access ########################### */
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#if __has_builtin(__builtin_arm_get_fpscr)
// Re-enable using built-in when GCC has been fixed
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
return __builtin_arm_get_fpscr();
#else
uint32_t result;
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
return(result);
#endif
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
{
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
#if __has_builtin(__builtin_arm_set_fpscr)
// Re-enable using built-in when GCC has been fixed
// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
__builtin_arm_set_fpscr(fpscr);
#else
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
#endif
#else
(void)fpscr;
#endif
}
/** \brief Get CPSR Register
\return CPSR Register value
*/
__STATIC_FORCEINLINE uint32_t __get_CPSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, cpsr" : "=r" (result) );
return(result);
}
/** \brief Set CPSR Register
\param [in] cpsr CPSR value to set
*/
__STATIC_FORCEINLINE void __set_CPSR(uint32_t cpsr)
{
__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "memory");
}
/** \brief Get Mode
\return Processor Mode
*/
__STATIC_FORCEINLINE uint32_t __get_mode(void)
{
return (__get_CPSR() & 0x1FU);
}
/** \brief Set Mode
\param [in] mode Mode value to set
*/
__STATIC_FORCEINLINE void __set_mode(uint32_t mode)
{
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
}
/** \brief Get Stack Pointer
\return Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP(void)
{
uint32_t result;
__ASM volatile("MOV %0, sp" : "=r" (result) : : "memory");
return result;
}
/** \brief Set Stack Pointer
\param [in] stack Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP(uint32_t stack)
{
__ASM volatile("MOV sp, %0" : : "r" (stack) : "memory");
}
/** \brief Get USR/SYS Stack Pointer
\return USR/SYS Stack Pointer value
*/
__STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
{
uint32_t cpsr = __get_CPSR();
uint32_t result;
__ASM volatile(
"CPS #0x1F \n"
"MOV %0, sp " : "=r"(result) : : "memory"
);
__set_CPSR(cpsr);
__ISB();
return result;
}
/** \brief Set USR/SYS Stack Pointer
\param [in] topOfProcStack USR/SYS Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
{
uint32_t cpsr = __get_CPSR();
__ASM volatile(
"CPS #0x1F \n"
"MOV sp, %0 " : : "r" (topOfProcStack) : "memory"
);
__set_CPSR(cpsr);
__ISB();
}
/** \brief Get FPEXC
\return Floating Point Exception Control register value
*/
__STATIC_FORCEINLINE uint32_t __get_FPEXC(void)
{
#if (__FPU_PRESENT == 1)
uint32_t result;
__ASM volatile("VMRS %0, fpexc" : "=r" (result) );
return(result);
#else
return(0);
#endif
}
/** \brief Set FPEXC
\param [in] fpexc Floating Point Exception Control value to set
*/
__STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
{
#if (__FPU_PRESENT == 1)
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
#endif
}
/*
* Include common core functions to access Coprocessor 15 registers
*/
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
#include "cmsis_cp15.h"
/** \brief Enable Floating Point Unit
Critical section, called from undef handler, so systick is disabled
*/
__STATIC_INLINE void __FPU_Enable(void)
{
__ASM volatile(
//Permit access to VFP/NEON, registers by modifying CPACR
" MRC p15,0,R1,c1,c0,2 \n"
" ORR R1,R1,#0x00F00000 \n"
" MCR p15,0,R1,c1,c0,2 \n"
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
" ISB \n"
//Enable VFP/NEON
" VMRS R1,FPEXC \n"
" ORR R1,R1,#0x40000000 \n"
" VMSR FPEXC,R1 \n"
//Initialise VFP/NEON registers to 0
" MOV R2,#0 \n"
//Initialise D16 registers to 0
" VMOV D0, R2,R2 \n"
" VMOV D1, R2,R2 \n"
" VMOV D2, R2,R2 \n"
" VMOV D3, R2,R2 \n"
" VMOV D4, R2,R2 \n"
" VMOV D5, R2,R2 \n"
" VMOV D6, R2,R2 \n"
" VMOV D7, R2,R2 \n"
" VMOV D8, R2,R2 \n"
" VMOV D9, R2,R2 \n"
" VMOV D10,R2,R2 \n"
" VMOV D11,R2,R2 \n"
" VMOV D12,R2,R2 \n"
" VMOV D13,R2,R2 \n"
" VMOV D14,R2,R2 \n"
" VMOV D15,R2,R2 \n"
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
//Initialise D32 registers to 0
" VMOV D16,R2,R2 \n"
" VMOV D17,R2,R2 \n"
" VMOV D18,R2,R2 \n"
" VMOV D19,R2,R2 \n"
" VMOV D20,R2,R2 \n"
" VMOV D21,R2,R2 \n"
" VMOV D22,R2,R2 \n"
" VMOV D23,R2,R2 \n"
" VMOV D24,R2,R2 \n"
" VMOV D25,R2,R2 \n"
" VMOV D26,R2,R2 \n"
" VMOV D27,R2,R2 \n"
" VMOV D28,R2,R2 \n"
" VMOV D29,R2,R2 \n"
" VMOV D30,R2,R2 \n"
" VMOV D31,R2,R2 \n"
#endif
//Initialise FPSCR to a known state
" VMRS R2,FPSCR \n"
" LDR R3,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
" AND R2,R2,R3 \n"
" VMSR FPSCR,R2 "
);
}
#pragma GCC diagnostic pop
#endif /* __CMSIS_GCC_H */

559
soft/processor32f446/Drivers/CMSIS/Core_A/Include/cmsis_iccarm.h Normal file
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@ -0,0 +1,559 @@
/**************************************************************************//**
* @file cmsis_iccarm.h
* @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
* @version V5.0.6
* @date 02. March 2018
******************************************************************************/
//------------------------------------------------------------------------------
//
// Copyright (c) 2017-2018 IAR Systems
//
// Licensed under the Apache License, Version 2.0 (the "License")
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
//------------------------------------------------------------------------------
#ifndef __CMSIS_ICCARM_H__
#define __CMSIS_ICCARM_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#define __IAR_FT _Pragma("inline=forced") __intrinsic
#if (__VER__ >= 8000000)
#define __ICCARM_V8 1
#else
#define __ICCARM_V8 0
#endif
#pragma language=extended
#ifndef __ALIGNED
#if __ICCARM_V8
#define __ALIGNED(x) __attribute__((aligned(x)))
#elif (__VER__ >= 7080000)
/* Needs IAR language extensions */
#define __ALIGNED(x) __attribute__((aligned(x)))
#else
#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#endif
/* Define compiler macros for CPU architecture, used in CMSIS 5.
*/
#if __ARM_ARCH_7A__
/* Macro already defined */
#else
#if defined(__ARM7A__)
#define __ARM_ARCH_7A__ 1
#endif
#endif
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __NO_RETURN
#if __ICCARM_V8
#define __NO_RETURN __attribute__((__noreturn__))
#else
#define __NO_RETURN _Pragma("object_attribute=__noreturn")
#endif
#endif
#ifndef __PACKED
/* Needs IAR language extensions */
#if __ICCARM_V8
#define __PACKED __attribute__((packed, aligned(1)))
#else
#define __PACKED __packed
#endif
#endif
#ifndef __PACKED_STRUCT
/* Needs IAR language extensions */
#if __ICCARM_V8
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#else
#define __PACKED_STRUCT __packed struct
#endif
#endif
#ifndef __PACKED_UNION
/* Needs IAR language extensions */
#if __ICCARM_V8
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#else
#define __PACKED_UNION __packed union
#endif
#endif
#ifndef __RESTRICT
#define __RESTRICT __restrict
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __FORCEINLINE
#define __FORCEINLINE _Pragma("inline=forced")
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
#endif
#ifndef CMSIS_DEPRECATED
#define CMSIS_DEPRECATED __attribute__((deprecated))
#endif
#ifndef __UNALIGNED_UINT16_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
{
return *(__packed uint16_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
{
*(__packed uint16_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
#endif
#ifndef __UNALIGNED_UINT32_READ
#pragma language=save
#pragma language=extended
__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
{
return *(__packed uint32_t*)(ptr);
}
#pragma language=restore
#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
#pragma language=save
#pragma language=extended
__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
{
*(__packed uint32_t*)(ptr) = val;;
}
#pragma language=restore
#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
#endif
#if 0
#ifndef __UNALIGNED_UINT32 /* deprecated */
#pragma language=save
#pragma language=extended
__packed struct __iar_u32 { uint32_t v; };
#pragma language=restore
#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
#endif
#endif
#ifndef __USED
#if __ICCARM_V8
#define __USED __attribute__((used))
#else
#define __USED _Pragma("__root")
#endif
#endif
#ifndef __WEAK
#if __ICCARM_V8
#define __WEAK __attribute__((weak))
#else
#define __WEAK _Pragma("__weak")
#endif
#endif
#ifndef __ICCARM_INTRINSICS_VERSION__
#define __ICCARM_INTRINSICS_VERSION__ 0
#endif
#if __ICCARM_INTRINSICS_VERSION__ == 2
#if defined(__CLZ)
#undef __CLZ
#endif
#if defined(__REVSH)
#undef __REVSH
#endif
#if defined(__RBIT)
#undef __RBIT
#endif
#if defined(__SSAT)
#undef __SSAT
#endif
#if defined(__USAT)
#undef __USAT
#endif
#include "iccarm_builtin.h"
#define __enable_irq __iar_builtin_enable_interrupt
#define __disable_irq __iar_builtin_disable_interrupt
#define __enable_fault_irq __iar_builtin_enable_fiq
#define __disable_fault_irq __iar_builtin_disable_fiq
#define __arm_rsr __iar_builtin_rsr
#define __arm_wsr __iar_builtin_wsr
#if __FPU_PRESENT
#define __get_FPSCR() (__arm_rsr("FPSCR"))
#else
#define __get_FPSCR() ( 0 )
#endif
#define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", VALUE))
#define __get_CPSR() (__arm_rsr("CPSR"))
#define __get_mode() (__get_CPSR() & 0x1FU)
#define __set_CPSR(VALUE) (__arm_wsr("CPSR", (VALUE)))
#define __set_mode(VALUE) (__arm_wsr("CPSR_c", (VALUE)))
#define __get_FPEXC() (__arm_rsr("FPEXC"))
#define __set_FPEXC(VALUE) (__arm_wsr("FPEXC", VALUE))
#define __get_CP(cp, op1, RT, CRn, CRm, op2) \
((RT) = __arm_rsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2))
#define __set_CP(cp, op1, RT, CRn, CRm, op2) \
(__arm_wsr("p" # cp ":" # op1 ":c" # CRn ":c" # CRm ":" # op2, (RT)))
#define __get_CP64(cp, op1, Rt, CRm) \
__ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
#define __set_CP64(cp, op1, Rt, CRm) \
__ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
#include "cmsis_cp15.h"
#define __NOP __iar_builtin_no_operation
#define __CLZ __iar_builtin_CLZ
#define __CLREX __iar_builtin_CLREX
#define __DMB __iar_builtin_DMB
#define __DSB __iar_builtin_DSB
#define __ISB __iar_builtin_ISB
#define __LDREXB __iar_builtin_LDREXB
#define __LDREXH __iar_builtin_LDREXH
#define __LDREXW __iar_builtin_LDREX
#define __RBIT __iar_builtin_RBIT
#define __REV __iar_builtin_REV
#define __REV16 __iar_builtin_REV16
__IAR_FT int16_t __REVSH(int16_t val)
{
return (int16_t) __iar_builtin_REVSH(val);
}
#define __ROR __iar_builtin_ROR
#define __RRX __iar_builtin_RRX
#define __SEV __iar_builtin_SEV
#define __SSAT __iar_builtin_SSAT
#define __STREXB __iar_builtin_STREXB
#define __STREXH __iar_builtin_STREXH
#define __STREXW __iar_builtin_STREX
#define __USAT __iar_builtin_USAT
#define __WFE __iar_builtin_WFE
#define __WFI __iar_builtin_WFI
#define __SADD8 __iar_builtin_SADD8
#define __QADD8 __iar_builtin_QADD8
#define __SHADD8 __iar_builtin_SHADD8
#define __UADD8 __iar_builtin_UADD8
#define __UQADD8 __iar_builtin_UQADD8
#define __UHADD8 __iar_builtin_UHADD8
#define __SSUB8 __iar_builtin_SSUB8
#define __QSUB8 __iar_builtin_QSUB8
#define __SHSUB8 __iar_builtin_SHSUB8
#define __USUB8 __iar_builtin_USUB8
#define __UQSUB8 __iar_builtin_UQSUB8
#define __UHSUB8 __iar_builtin_UHSUB8
#define __SADD16 __iar_builtin_SADD16
#define __QADD16 __iar_builtin_QADD16
#define __SHADD16 __iar_builtin_SHADD16
#define __UADD16 __iar_builtin_UADD16
#define __UQADD16 __iar_builtin_UQADD16
#define __UHADD16 __iar_builtin_UHADD16
#define __SSUB16 __iar_builtin_SSUB16
#define __QSUB16 __iar_builtin_QSUB16
#define __SHSUB16 __iar_builtin_SHSUB16
#define __USUB16 __iar_builtin_USUB16
#define __UQSUB16 __iar_builtin_UQSUB16
#define __UHSUB16 __iar_builtin_UHSUB16
#define __SASX __iar_builtin_SASX
#define __QASX __iar_builtin_QASX
#define __SHASX __iar_builtin_SHASX
#define __UASX __iar_builtin_UASX
#define __UQASX __iar_builtin_UQASX
#define __UHASX __iar_builtin_UHASX
#define __SSAX __iar_builtin_SSAX
#define __QSAX __iar_builtin_QSAX
#define __SHSAX __iar_builtin_SHSAX
#define __USAX __iar_builtin_USAX
#define __UQSAX __iar_builtin_UQSAX
#define __UHSAX __iar_builtin_UHSAX
#define __USAD8 __iar_builtin_USAD8
#define __USADA8 __iar_builtin_USADA8
#define __SSAT16 __iar_builtin_SSAT16
#define __USAT16 __iar_builtin_USAT16
#define __UXTB16 __iar_builtin_UXTB16
#define __UXTAB16 __iar_builtin_UXTAB16
#define __SXTB16 __iar_builtin_SXTB16
#define __SXTAB16 __iar_builtin_SXTAB16
#define __SMUAD __iar_builtin_SMUAD
#define __SMUADX __iar_builtin_SMUADX
#define __SMMLA __iar_builtin_SMMLA
#define __SMLAD __iar_builtin_SMLAD
#define __SMLADX __iar_builtin_SMLADX
#define __SMLALD __iar_builtin_SMLALD
#define __SMLALDX __iar_builtin_SMLALDX
#define __SMUSD __iar_builtin_SMUSD
#define __SMUSDX __iar_builtin_SMUSDX
#define __SMLSD __iar_builtin_SMLSD
#define __SMLSDX __iar_builtin_SMLSDX
#define __SMLSLD __iar_builtin_SMLSLD
#define __SMLSLDX __iar_builtin_SMLSLDX
#define __SEL __iar_builtin_SEL
#define __QADD __iar_builtin_QADD
#define __QSUB __iar_builtin_QSUB
#define __PKHBT __iar_builtin_PKHBT
#define __PKHTB __iar_builtin_PKHTB
#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#if !__FPU_PRESENT
#define __get_FPSCR __cmsis_iar_get_FPSR_not_active
#endif
#ifdef __INTRINSICS_INCLUDED
#error intrinsics.h is already included previously!
#endif
#include <intrinsics.h>
#if !__FPU_PRESENT
#define __get_FPSCR() (0)
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#define __NOP __no_operation
#define __get_xPSR __get_PSR
__IAR_FT void __set_mode(uint32_t mode)
{
__ASM volatile("MSR cpsr_c, %0" : : "r" (mode) : "memory");
}
__IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
{
return __LDREX((unsigned long *)ptr);
}
__IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
{
return __STREX(value, (unsigned long *)ptr);
}
__IAR_FT uint32_t __RRX(uint32_t value)
{
uint32_t result;
__ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc");
return(result);
}
__IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
__IAR_FT uint32_t __get_FPEXC(void)
{
#if (__FPU_PRESENT == 1)
uint32_t result;
__ASM volatile("VMRS %0, fpexc" : "=r" (result) : : "memory");
return(result);
#else
return(0);
#endif
}
__IAR_FT void __set_FPEXC(uint32_t fpexc)
{
#if (__FPU_PRESENT == 1)
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc) : "memory");
#endif
}
#define __get_CP(cp, op1, Rt, CRn, CRm, op2) \
__ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
#define __set_CP(cp, op1, Rt, CRn, CRm, op2) \
__ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
#define __get_CP64(cp, op1, Rt, CRm) \
__ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" )
#define __set_CP64(cp, op1, Rt, CRm) \
__ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" )
#include "cmsis_cp15.h"
#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
__IAR_FT uint32_t __get_SP_usr(void)
{
uint32_t cpsr;
uint32_t result;
__ASM volatile(
"MRS %0, cpsr \n"
"CPS #0x1F \n" // no effect in USR mode
"MOV %1, sp \n"
"MSR cpsr_c, %2 \n" // no effect in USR mode
"ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
);
return result;
}
__IAR_FT void __set_SP_usr(uint32_t topOfProcStack)
{
uint32_t cpsr;
__ASM volatile(
"MRS %0, cpsr \n"
"CPS #0x1F \n" // no effect in USR mode
"MOV sp, %1 \n"
"MSR cpsr_c, %2 \n" // no effect in USR mode
"ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
);
}
#define __get_mode() (__get_CPSR() & 0x1FU)
__STATIC_INLINE
void __FPU_Enable(void)
{
__ASM volatile(
//Permit access to VFP/NEON, registers by modifying CPACR
" MRC p15,0,R1,c1,c0,2 \n"
" ORR R1,R1,#0x00F00000 \n"
" MCR p15,0,R1,c1,c0,2 \n"
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
" ISB \n"
//Enable VFP/NEON
" VMRS R1,FPEXC \n"
" ORR R1,R1,#0x40000000 \n"
" VMSR FPEXC,R1 \n"
//Initialise VFP/NEON registers to 0
" MOV R2,#0 \n"
//Initialise D16 registers to 0
" VMOV D0, R2,R2 \n"
" VMOV D1, R2,R2 \n"
" VMOV D2, R2,R2 \n"
" VMOV D3, R2,R2 \n"
" VMOV D4, R2,R2 \n"
" VMOV D5, R2,R2 \n"
" VMOV D6, R2,R2 \n"
" VMOV D7, R2,R2 \n"
" VMOV D8, R2,R2 \n"
" VMOV D9, R2,R2 \n"
" VMOV D10,R2,R2 \n"
" VMOV D11,R2,R2 \n"
" VMOV D12,R2,R2 \n"
" VMOV D13,R2,R2 \n"
" VMOV D14,R2,R2 \n"
" VMOV D15,R2,R2 \n"
#ifdef __ARM_ADVANCED_SIMD__
//Initialise D32 registers to 0
" VMOV D16,R2,R2 \n"
" VMOV D17,R2,R2 \n"
" VMOV D18,R2,R2 \n"
" VMOV D19,R2,R2 \n"
" VMOV D20,R2,R2 \n"
" VMOV D21,R2,R2 \n"
" VMOV D22,R2,R2 \n"
" VMOV D23,R2,R2 \n"
" VMOV D24,R2,R2 \n"
" VMOV D25,R2,R2 \n"
" VMOV D26,R2,R2 \n"
" VMOV D27,R2,R2 \n"
" VMOV D28,R2,R2 \n"
" VMOV D29,R2,R2 \n"
" VMOV D30,R2,R2 \n"
" VMOV D31,R2,R2 \n"
#endif
//Initialise FPSCR to a known state
" VMRS R2,FPSCR \n"
" MOV32 R3,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
" AND R2,R2,R3 \n"
" VMSR FPSCR,R2 \n");
}
#undef __IAR_FT
#undef __ICCARM_V8
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_ICCARM_H__ */

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/**************************************************************************//**
* @file irq_ctrl.h
* @brief Interrupt Controller API header file
* @version V1.0.0
* @date 23. June 2017
******************************************************************************/
/*
* Copyright (c) 2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef IRQ_CTRL_H_
#define IRQ_CTRL_H_
#include <stdint.h>
#ifndef IRQHANDLER_T
#define IRQHANDLER_T
/// Interrupt handler data type
typedef void (*IRQHandler_t) (void);
#endif
#ifndef IRQN_ID_T
#define IRQN_ID_T
/// Interrupt ID number data type
typedef int32_t IRQn_ID_t;
#endif
/* Interrupt mode bit-masks */
#define IRQ_MODE_TRIG_Pos (0U)
#define IRQ_MODE_TRIG_Msk (0x07UL /*<< IRQ_MODE_TRIG_Pos*/)
#define IRQ_MODE_TRIG_LEVEL (0x00UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: level triggered interrupt
#define IRQ_MODE_TRIG_LEVEL_LOW (0x01UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: low level triggered interrupt
#define IRQ_MODE_TRIG_LEVEL_HIGH (0x02UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: high level triggered interrupt
#define IRQ_MODE_TRIG_EDGE (0x04UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: edge triggered interrupt
#define IRQ_MODE_TRIG_EDGE_RISING (0x05UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising edge triggered interrupt
#define IRQ_MODE_TRIG_EDGE_FALLING (0x06UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: falling edge triggered interrupt
#define IRQ_MODE_TRIG_EDGE_BOTH (0x07UL /*<< IRQ_MODE_TRIG_Pos*/) ///< Trigger: rising and falling edge triggered interrupt
#define IRQ_MODE_TYPE_Pos (3U)
#define IRQ_MODE_TYPE_Msk (0x01UL << IRQ_MODE_TYPE_Pos)
#define IRQ_MODE_TYPE_IRQ (0x00UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU IRQ line
#define IRQ_MODE_TYPE_FIQ (0x01UL << IRQ_MODE_TYPE_Pos) ///< Type: interrupt source triggers CPU FIQ line
#define IRQ_MODE_DOMAIN_Pos (4U)
#define IRQ_MODE_DOMAIN_Msk (0x01UL << IRQ_MODE_DOMAIN_Pos)
#define IRQ_MODE_DOMAIN_NONSECURE (0x00UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting non-secure domain
#define IRQ_MODE_DOMAIN_SECURE (0x01UL << IRQ_MODE_DOMAIN_Pos) ///< Domain: interrupt is targeting secure domain
#define IRQ_MODE_CPU_Pos (5U)
#define IRQ_MODE_CPU_Msk (0xFFUL << IRQ_MODE_CPU_Pos)
#define IRQ_MODE_CPU_ALL (0x00UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets all CPUs
#define IRQ_MODE_CPU_0 (0x01UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 0
#define IRQ_MODE_CPU_1 (0x02UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 1
#define IRQ_MODE_CPU_2 (0x04UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 2
#define IRQ_MODE_CPU_3 (0x08UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 3
#define IRQ_MODE_CPU_4 (0x10UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 4
#define IRQ_MODE_CPU_5 (0x20UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 5
#define IRQ_MODE_CPU_6 (0x40UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 6
#define IRQ_MODE_CPU_7 (0x80UL << IRQ_MODE_CPU_Pos) ///< CPU: interrupt targets CPU 7
#define IRQ_MODE_ERROR (0x80000000UL) ///< Bit indicating mode value error
/* Interrupt priority bit-masks */
#define IRQ_PRIORITY_Msk (0x0000FFFFUL) ///< Interrupt priority value bit-mask
#define IRQ_PRIORITY_ERROR (0x80000000UL) ///< Bit indicating priority value error
/// Initialize interrupt controller.
/// \return 0 on success, -1 on error.
int32_t IRQ_Initialize (void);
/// Register interrupt handler.
/// \param[in] irqn interrupt ID number
/// \param[in] handler interrupt handler function address
/// \return 0 on success, -1 on error.
int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler);
/// Get the registered interrupt handler.
/// \param[in] irqn interrupt ID number
/// \return registered interrupt handler function address.
IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn);
/// Enable interrupt.
/// \param[in] irqn interrupt ID number
/// \return 0 on success, -1 on error.
int32_t IRQ_Enable (IRQn_ID_t irqn);
/// Disable interrupt.
/// \param[in] irqn interrupt ID number
/// \return 0 on success, -1 on error.
int32_t IRQ_Disable (IRQn_ID_t irqn);
/// Get interrupt enable state.
/// \param[in] irqn interrupt ID number
/// \return 0 - interrupt is disabled, 1 - interrupt is enabled.
uint32_t IRQ_GetEnableState (IRQn_ID_t irqn);
/// Configure interrupt request mode.
/// \param[in] irqn interrupt ID number
/// \param[in] mode mode configuration
/// \return 0 on success, -1 on error.
int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode);
/// Get interrupt mode configuration.
/// \param[in] irqn interrupt ID number
/// \return current interrupt mode configuration with optional IRQ_MODE_ERROR bit set.
uint32_t IRQ_GetMode (IRQn_ID_t irqn);
/// Get ID number of current interrupt request (IRQ).
/// \return interrupt ID number.
IRQn_ID_t IRQ_GetActiveIRQ (void);
/// Get ID number of current fast interrupt request (FIQ).
/// \return interrupt ID number.
IRQn_ID_t IRQ_GetActiveFIQ (void);
/// Signal end of interrupt processing.
/// \param[in] irqn interrupt ID number
/// \return 0 on success, -1 on error.
int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn);
/// Set interrupt pending flag.
/// \param[in] irqn interrupt ID number
/// \return 0 on success, -1 on error.
int32_t IRQ_SetPending (IRQn_ID_t irqn);
/// Get interrupt pending flag.
/// \param[in] irqn interrupt ID number
/// \return 0 - interrupt is not pending, 1 - interrupt is pending.
uint32_t IRQ_GetPending (IRQn_ID_t irqn);
/// Clear interrupt pending flag.
/// \param[in] irqn interrupt ID number
/// \return 0 on success, -1 on error.
int32_t IRQ_ClearPending (IRQn_ID_t irqn);
/// Set interrupt priority value.
/// \param[in] irqn interrupt ID number
/// \param[in] priority interrupt priority value
/// \return 0 on success, -1 on error.
int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority);
/// Get interrupt priority.
/// \param[in] irqn interrupt ID number
/// \return current interrupt priority value with optional IRQ_PRIORITY_ERROR bit set.
uint32_t IRQ_GetPriority (IRQn_ID_t irqn);
/// Set priority masking threshold.
/// \param[in] priority priority masking threshold value
/// \return 0 on success, -1 on error.
int32_t IRQ_SetPriorityMask (uint32_t priority);
/// Get priority masking threshold
/// \return current priority masking threshold value with optional IRQ_PRIORITY_ERROR bit set.
uint32_t IRQ_GetPriorityMask (void);
/// Set priority grouping field split point
/// \param[in] bits number of MSB bits included in the group priority field comparison
/// \return 0 on success, -1 on error.
int32_t IRQ_SetPriorityGroupBits (uint32_t bits);
/// Get priority grouping field split point
/// \return current number of MSB bits included in the group priority field comparison with
/// optional IRQ_PRIORITY_ERROR bit set.
uint32_t IRQ_GetPriorityGroupBits (void);
#endif // IRQ_CTRL_H_

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/**************************************************************************//**
* @file irq_ctrl_gic.c
* @brief Interrupt controller handling implementation for GIC
* @version V1.0.1
* @date 9. April 2018
******************************************************************************/
/*
* Copyright (c) 2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "RTE_Components.h"
#include CMSIS_device_header
#include "irq_ctrl.h"
#if defined(__GIC_PRESENT) && (__GIC_PRESENT == 1U)
/// Number of implemented interrupt lines
#ifndef IRQ_GIC_LINE_COUNT
#define IRQ_GIC_LINE_COUNT (1020U)
#endif
static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
static uint32_t IRQ_ID0;
/// Initialize interrupt controller.
__WEAK int32_t IRQ_Initialize (void) {
uint32_t i;
for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
IRQTable[i] = (IRQHandler_t)NULL;
}
GIC_Enable();
return (0);
}
/// Register interrupt handler.
__WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
int32_t status;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
IRQTable[irqn] = handler;
status = 0;
} else {
status = -1;
}
return (status);
}
/// Get the registered interrupt handler.
__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
IRQHandler_t h;
// Ignore CPUID field (software generated interrupts)
irqn &= 0x3FFU;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
h = IRQTable[irqn];
} else {
h = (IRQHandler_t)0;
}
return (h);
}
/// Enable interrupt.
__WEAK int32_t IRQ_Enable (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
GIC_EnableIRQ ((IRQn_Type)irqn);
status = 0;
} else {
status = -1;
}
return (status);
}
/// Disable interrupt.
__WEAK int32_t IRQ_Disable (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
GIC_DisableIRQ ((IRQn_Type)irqn);
status = 0;
} else {
status = -1;
}
return (status);
}
/// Get interrupt enable state.
__WEAK uint32_t IRQ_GetEnableState (IRQn_ID_t irqn) {
uint32_t enable;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
enable = GIC_GetEnableIRQ((IRQn_Type)irqn);
} else {
enable = 0U;
}
return (enable);
}
/// Configure interrupt request mode.
__WEAK int32_t IRQ_SetMode (IRQn_ID_t irqn, uint32_t mode) {
uint32_t val;
uint8_t cfg;
uint8_t secure;
uint8_t cpu;
int32_t status = 0;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
// Check triggering mode
val = (mode & IRQ_MODE_TRIG_Msk);
if (val == IRQ_MODE_TRIG_LEVEL) {
cfg = 0x00U;
} else if (val == IRQ_MODE_TRIG_EDGE) {
cfg = 0x02U;
} else {
cfg = 0x00U;
status = -1;
}
// Check interrupt type
val = mode & IRQ_MODE_TYPE_Msk;
if (val != IRQ_MODE_TYPE_IRQ) {
status = -1;
}
// Check interrupt domain
val = mode & IRQ_MODE_DOMAIN_Msk;
if (val == IRQ_MODE_DOMAIN_NONSECURE) {
secure = 0U;
} else {
// Check security extensions support
val = GIC_DistributorInfo() & (1UL << 10U);
if (val != 0U) {
// Security extensions are supported
secure = 1U;
} else {
secure = 0U;
status = -1;
}
}
// Check interrupt CPU targets
val = mode & IRQ_MODE_CPU_Msk;
if (val == IRQ_MODE_CPU_ALL) {
cpu = 0xFFU;
} else {
cpu = val >> IRQ_MODE_CPU_Pos;
}
// Apply configuration if no mode error
if (status == 0) {
GIC_SetConfiguration((IRQn_Type)irqn, cfg);
GIC_SetTarget ((IRQn_Type)irqn, cpu);
if (secure != 0U) {
GIC_SetGroup ((IRQn_Type)irqn, secure);
}
}
}
return (status);
}
/// Get interrupt mode configuration.
__WEAK uint32_t IRQ_GetMode (IRQn_ID_t irqn) {
uint32_t mode;
uint32_t val;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
mode = IRQ_MODE_TYPE_IRQ;
// Get trigger mode
val = GIC_GetConfiguration((IRQn_Type)irqn);
if ((val & 2U) != 0U) {
// Corresponding interrupt is edge triggered
mode |= IRQ_MODE_TRIG_EDGE;
} else {
// Corresponding interrupt is level triggered
mode |= IRQ_MODE_TRIG_LEVEL;
}
// Get interrupt CPU targets
mode |= GIC_GetTarget ((IRQn_Type)irqn) << IRQ_MODE_CPU_Pos;
} else {
mode = IRQ_MODE_ERROR;
}
return (mode);
}
/// Get ID number of current interrupt request (IRQ).
__WEAK IRQn_ID_t IRQ_GetActiveIRQ (void) {
IRQn_ID_t irqn;
uint32_t prio;
/* Dummy read to avoid GIC 390 errata 801120 */
GIC_GetHighPendingIRQ();
irqn = GIC_AcknowledgePending();
__DSB();
/* Workaround GIC 390 errata 733075 (GIC-390_Errata_Notice_v6.pdf, 09-Jul-2014) */
/* The following workaround code is for a single-core system. It would be */
/* different in a multi-core system. */
/* If the ID is 0 or 0x3FE or 0x3FF, then the GIC CPU interface may be locked-up */
/* so unlock it, otherwise service the interrupt as normal. */
/* Special IDs 1020=0x3FC and 1021=0x3FD are reserved values in GICv1 and GICv2 */
/* so will not occur here. */
if ((irqn == 0) || (irqn >= 0x3FE)) {
/* Unlock the CPU interface with a dummy write to Interrupt Priority Register */
prio = GIC_GetPriority((IRQn_Type)0);
GIC_SetPriority ((IRQn_Type)0, prio);
__DSB();
if ((irqn == 0U) && ((GIC_GetIRQStatus ((IRQn_Type)irqn) & 1U) != 0U) && (IRQ_ID0 == 0U)) {
/* If the ID is 0, is active and has not been seen before */
IRQ_ID0 = 1U;
}
/* End of Workaround GIC 390 errata 733075 */
}
return (irqn);
}
/// Get ID number of current fast interrupt request (FIQ).
__WEAK IRQn_ID_t IRQ_GetActiveFIQ (void) {
return ((IRQn_ID_t)-1);
}
/// Signal end of interrupt processing.
__WEAK int32_t IRQ_EndOfInterrupt (IRQn_ID_t irqn) {
int32_t status;
IRQn_Type irq = (IRQn_Type)irqn;
irqn &= 0x3FFU;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
GIC_EndInterrupt (irq);
if (irqn == 0) {
IRQ_ID0 = 0U;
}
status = 0;
} else {
status = -1;
}
return (status);
}
/// Set interrupt pending flag.
__WEAK int32_t IRQ_SetPending (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
GIC_SetPendingIRQ ((IRQn_Type)irqn);
status = 0;
} else {
status = -1;
}
return (status);
}
/// Get interrupt pending flag.
__WEAK uint32_t IRQ_GetPending (IRQn_ID_t irqn) {
uint32_t pending;
if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
pending = GIC_GetPendingIRQ ((IRQn_Type)irqn);
} else {
pending = 0U;
}
return (pending & 1U);
}
/// Clear interrupt pending flag.
__WEAK int32_t IRQ_ClearPending (IRQn_ID_t irqn) {
int32_t status;
if ((irqn >= 16) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
GIC_ClearPendingIRQ ((IRQn_Type)irqn);
status = 0;
} else {
status = -1;
}
return (status);
}
/// Set interrupt priority value.
__WEAK int32_t IRQ_SetPriority (IRQn_ID_t irqn, uint32_t priority) {
int32_t status;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
GIC_SetPriority ((IRQn_Type)irqn, priority);
status = 0;
} else {
status = -1;
}
return (status);
}
/// Get interrupt priority.
__WEAK uint32_t IRQ_GetPriority (IRQn_ID_t irqn) {
uint32_t priority;
if ((irqn >= 0) && (irqn < (IRQn_ID_t)IRQ_GIC_LINE_COUNT)) {
priority = GIC_GetPriority ((IRQn_Type)irqn);
} else {
priority = IRQ_PRIORITY_ERROR;
}
return (priority);
}
/// Set priority masking threshold.
__WEAK int32_t IRQ_SetPriorityMask (uint32_t priority) {
GIC_SetInterfacePriorityMask (priority);
return (0);
}
/// Get priority masking threshold
__WEAK uint32_t IRQ_GetPriorityMask (void) {
return GIC_GetInterfacePriorityMask();
}
/// Set priority grouping field split point
__WEAK int32_t IRQ_SetPriorityGroupBits (uint32_t bits) {
int32_t status;
if (bits == IRQ_PRIORITY_Msk) {
bits = 7U;
}
if (bits < 8U) {
GIC_SetBinaryPoint (7U - bits);
status = 0;
} else {
status = -1;
}
return (status);
}
/// Get priority grouping field split point
__WEAK uint32_t IRQ_GetPriorityGroupBits (void) {
uint32_t bp;
bp = GIC_GetBinaryPoint() & 0x07U;
return (7U - bp);
}
#endif

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