ADD: TIM3 timer and oscillate diod LED1 with 200us
This commit is contained in:
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421ba982dd
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314af70ff0
9 changed files with 878 additions and 26 deletions
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@ -63,7 +63,7 @@
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/* #define HAL_SD_MODULE_ENABLED */
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/* #define HAL_MMC_MODULE_ENABLED */
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/* #define HAL_SPI_MODULE_ENABLED */
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/* #define HAL_TIM_MODULE_ENABLED */
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#define HAL_TIM_MODULE_ENABLED
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/* #define HAL_UART_MODULE_ENABLED */
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/* #define HAL_USART_MODULE_ENABLED */
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/* #define HAL_IRDA_MODULE_ENABLED */
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@ -59,6 +59,7 @@ void ADC_IRQHandler(void);
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void TIM1_BRK_TIM9_IRQHandler(void);
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void TIM1_CC_IRQHandler(void);
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void TIM2_IRQHandler(void);
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void TIM3_IRQHandler(void);
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/* USER CODE BEGIN EFP */
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/* USER CODE END EFP */
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@ -32,12 +32,15 @@ extern "C" {
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/* USER CODE END Includes */
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extern TIM_HandleTypeDef htim3;
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/* USER CODE BEGIN Private defines */
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/* USER CODE END Private defines */
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void MX_TIM1_Init(void);
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void MX_TIM2_Init(void);
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void MX_TIM3_Init(void);
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/* USER CODE BEGIN Prototypes */
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20
Src/main.c
20
Src/main.c
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@ -78,7 +78,6 @@ int main(void)
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HAL_Init();
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/* USER CODE BEGIN Init */
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/* USER CODE END Init */
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/* Configure the system clock */
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@ -98,23 +97,18 @@ int main(void)
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MX_SPI2_Init();
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MX_CAN1_Init();
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MX_CAN2_Init();
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MX_TIM3_Init();
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/* Initialize interrupts */
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MX_NVIC_Init();
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/* USER CODE BEGIN 2 */
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if (HAL_TIM_Base_Start_IT(&htim3) != HAL_OK)
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{
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/* Starting Error */
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Error_Handler();
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}
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/* USER CODE END 2 */
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// Blink RED LED
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HAL_GPIO_TogglePin(LED1_GPIO_Port, LED1_Pin);
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HAL_Delay(500);
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HAL_GPIO_TogglePin(LED1_GPIO_Port, LED1_Pin);
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HAL_Delay(500);
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HAL_GPIO_TogglePin(LED1_GPIO_Port, LED1_Pin);
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HAL_Delay(500);
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HAL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
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HAL_Delay(1000);
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HAL_GPIO_TogglePin(LED2_GPIO_Port, LED2_Pin);
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HAL_GPIO_TogglePin(LED1_GPIO_Port, LED1_Pin);
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/* Infinite loop */
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/* USER CODE BEGIN WHILE */
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while (1)
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@ -55,7 +55,7 @@
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/* USER CODE END 0 */
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/* External variables --------------------------------------------------------*/
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extern TIM_HandleTypeDef htim3;
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/* USER CODE BEGIN EV */
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/* USER CODE END EV */
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@ -245,13 +245,28 @@ void TIM1_CC_IRQHandler(void)
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void TIM2_IRQHandler(void)
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{
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/* USER CODE BEGIN TIM2_IRQn 0 */
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/* USER CODE END TIM2_IRQn 0 */
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/* USER CODE BEGIN TIM2_IRQn 1 */
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/* USER CODE END TIM2_IRQn 1 */
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}
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/**
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* @brief This function handles TIM3 global interrupt.
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*/
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void TIM3_IRQHandler(void)
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{
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/* USER CODE BEGIN TIM3_IRQn 0 */
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// BLink Led1
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HAL_GPIO_TogglePin(LED1_GPIO_Port, LED1_Pin);
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/* USER CODE END TIM3_IRQn 0 */
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HAL_TIM_IRQHandler(&htim3);
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/* USER CODE BEGIN TIM3_IRQn 1 */
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/* USER CODE END TIM3_IRQn 1 */
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}
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/* USER CODE BEGIN 1 */
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/* USER CODE END 1 */
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747
Src/system_stm32f4xx.c
Normal file
747
Src/system_stm32f4xx.c
Normal file
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@ -0,0 +1,747 @@
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/**
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******************************************************************************
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* @file system_stm32f4xx.c
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* @author MCD Application Team
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* @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32f4xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32f4xx_system
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* @{
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*/
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/** @addtogroup STM32F4xx_System_Private_Includes
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* @{
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*/
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#include "stm32f4xx.h"
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#if !defined (HSE_VALUE)
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#define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/**
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* @}
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*/
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/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F4xx_System_Private_Defines
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* @{
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*/
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/************************* Miscellaneous Configuration ************************/
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/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
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#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
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|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
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|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
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/* #define DATA_IN_ExtSRAM */
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#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\
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STM32F412Zx || STM32F412Vx */
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
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|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
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/* #define DATA_IN_ExtSDRAM */
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#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
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STM32F479xx */
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/* Note: Following vector table addresses must be defined in line with linker
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configuration. */
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/*!< Uncomment the following line if you need to relocate the vector table
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anywhere in Flash or Sram, else the vector table is kept at the automatic
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remap of boot address selected */
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/* #define USER_VECT_TAB_ADDRESS */
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#if defined(USER_VECT_TAB_ADDRESS)
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/*!< Uncomment the following line if you need to relocate your vector Table
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in Sram else user remap will be done in Flash. */
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/* #define VECT_TAB_SRAM */
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#if defined(VECT_TAB_SRAM)
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#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
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This value must be a multiple of 0x200. */
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#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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#else
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#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
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This value must be a multiple of 0x200. */
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#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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#endif /* VECT_TAB_SRAM */
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#endif /* USER_VECT_TAB_ADDRESS */
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/******************************************************************************/
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/**
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* @}
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*/
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/** @addtogroup STM32F4xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32F4xx_System_Private_Variables
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* @{
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*/
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/* This variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 16000000;
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const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
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const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
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/**
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* @}
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*/
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/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
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* @{
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*/
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#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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static void SystemInit_ExtMemCtl(void);
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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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/**
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* @}
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*/
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/** @addtogroup STM32F4xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system
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* Initialize the FPU setting, vector table location and External memory
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* configuration.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
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#endif
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#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
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SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
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/* Configure the Vector Table location -------------------------------------*/
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#if defined(USER_VECT_TAB_ADDRESS)
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SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#endif /* USER_VECT_TAB_ADDRESS */
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
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* or HSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
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* 16 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
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* depends on the application requirements), user has to ensure that HSE_VALUE
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* is same as the real frequency of the crystal used. Otherwise, this function
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* may have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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*
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
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/* Get SYSCLK source -------------------------------------------------------*/
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tmp = RCC->CFGR & RCC_CFGR_SWS;
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switch (tmp)
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{
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case 0x00: /* HSI used as system clock source */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x04: /* HSE used as system clock source */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x08: /* PLL used as system clock source */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
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SYSCLK = PLL_VCO / PLL_P
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*/
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pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
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pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
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if (pllsource != 0)
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{
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/* HSE used as PLL clock source */
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pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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}
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else
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{
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/* HSI used as PLL clock source */
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pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
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}
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pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
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SystemCoreClock = pllvco/pllp;
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break;
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default:
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SystemCoreClock = HSI_VALUE;
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break;
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}
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/* Compute HCLK frequency --------------------------------------------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
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/* HCLK frequency */
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SystemCoreClock >>= tmp;
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}
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#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM)
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#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
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|| defined(STM32F469xx) || defined(STM32F479xx)
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/**
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* @brief Setup the external memory controller.
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* Called in startup_stm32f4xx.s before jump to main.
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* This function configures the external memories (SRAM/SDRAM)
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* This SRAM/SDRAM will be used as program data memory (including heap and stack).
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* @param None
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* @retval None
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*/
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void SystemInit_ExtMemCtl(void)
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{
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__IO uint32_t tmp = 0x00;
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register uint32_t tmpreg = 0, timeout = 0xFFFF;
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register __IO uint32_t index;
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/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */
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RCC->AHB1ENR |= 0x000001F8;
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/* Delay after an RCC peripheral clock enabling */
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tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
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/* Connect PDx pins to FMC Alternate function */
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GPIOD->AFR[0] = 0x00CCC0CC;
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GPIOD->AFR[1] = 0xCCCCCCCC;
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/* Configure PDx pins in Alternate function mode */
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GPIOD->MODER = 0xAAAA0A8A;
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/* Configure PDx pins speed to 100 MHz */
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GPIOD->OSPEEDR = 0xFFFF0FCF;
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/* Configure PDx pins Output type to push-pull */
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GPIOD->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PDx pins */
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GPIOD->PUPDR = 0x00000000;
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/* Connect PEx pins to FMC Alternate function */
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GPIOE->AFR[0] = 0xC00CC0CC;
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GPIOE->AFR[1] = 0xCCCCCCCC;
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/* Configure PEx pins in Alternate function mode */
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GPIOE->MODER = 0xAAAA828A;
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/* Configure PEx pins speed to 100 MHz */
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GPIOE->OSPEEDR = 0xFFFFC3CF;
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/* Configure PEx pins Output type to push-pull */
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GPIOE->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PEx pins */
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GPIOE->PUPDR = 0x00000000;
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/* Connect PFx pins to FMC Alternate function */
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GPIOF->AFR[0] = 0xCCCCCCCC;
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GPIOF->AFR[1] = 0xCCCCCCCC;
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/* Configure PFx pins in Alternate function mode */
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GPIOF->MODER = 0xAA800AAA;
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/* Configure PFx pins speed to 50 MHz */
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GPIOF->OSPEEDR = 0xAA800AAA;
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/* Configure PFx pins Output type to push-pull */
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GPIOF->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PFx pins */
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GPIOF->PUPDR = 0x00000000;
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/* Connect PGx pins to FMC Alternate function */
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GPIOG->AFR[0] = 0xCCCCCCCC;
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GPIOG->AFR[1] = 0xCCCCCCCC;
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/* Configure PGx pins in Alternate function mode */
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GPIOG->MODER = 0xAAAAAAAA;
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/* Configure PGx pins speed to 50 MHz */
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GPIOG->OSPEEDR = 0xAAAAAAAA;
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/* Configure PGx pins Output type to push-pull */
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GPIOG->OTYPER = 0x00000000;
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/* No pull-up, pull-down for PGx pins */
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||||
GPIOG->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PHx pins to FMC Alternate function */
|
||||
GPIOH->AFR[0] = 0x00C0CC00;
|
||||
GPIOH->AFR[1] = 0xCCCCCCCC;
|
||||
/* Configure PHx pins in Alternate function mode */
|
||||
GPIOH->MODER = 0xAAAA08A0;
|
||||
/* Configure PHx pins speed to 50 MHz */
|
||||
GPIOH->OSPEEDR = 0xAAAA08A0;
|
||||
/* Configure PHx pins Output type to push-pull */
|
||||
GPIOH->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PHx pins */
|
||||
GPIOH->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PIx pins to FMC Alternate function */
|
||||
GPIOI->AFR[0] = 0xCCCCCCCC;
|
||||
GPIOI->AFR[1] = 0x00000CC0;
|
||||
/* Configure PIx pins in Alternate function mode */
|
||||
GPIOI->MODER = 0x0028AAAA;
|
||||
/* Configure PIx pins speed to 50 MHz */
|
||||
GPIOI->OSPEEDR = 0x0028AAAA;
|
||||
/* Configure PIx pins Output type to push-pull */
|
||||
GPIOI->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PIx pins */
|
||||
GPIOI->PUPDR = 0x00000000;
|
||||
|
||||
/*-- FMC Configuration -------------------------------------------------------*/
|
||||
/* Enable the FMC interface clock */
|
||||
RCC->AHB3ENR |= 0x00000001;
|
||||
/* Delay after an RCC peripheral clock enabling */
|
||||
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
|
||||
|
||||
FMC_Bank5_6->SDCR[0] = 0x000019E4;
|
||||
FMC_Bank5_6->SDTR[0] = 0x01115351;
|
||||
|
||||
/* SDRAM initialization sequence */
|
||||
/* Clock enable command */
|
||||
FMC_Bank5_6->SDCMR = 0x00000011;
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
while((tmpreg != 0) && (timeout-- > 0))
|
||||
{
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
}
|
||||
|
||||
/* Delay */
|
||||
for (index = 0; index<1000; index++);
|
||||
|
||||
/* PALL command */
|
||||
FMC_Bank5_6->SDCMR = 0x00000012;
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
timeout = 0xFFFF;
|
||||
while((tmpreg != 0) && (timeout-- > 0))
|
||||
{
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
}
|
||||
|
||||
/* Auto refresh command */
|
||||
FMC_Bank5_6->SDCMR = 0x00000073;
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
timeout = 0xFFFF;
|
||||
while((tmpreg != 0) && (timeout-- > 0))
|
||||
{
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
}
|
||||
|
||||
/* MRD register program */
|
||||
FMC_Bank5_6->SDCMR = 0x00046014;
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
timeout = 0xFFFF;
|
||||
while((tmpreg != 0) && (timeout-- > 0))
|
||||
{
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
}
|
||||
|
||||
/* Set refresh count */
|
||||
tmpreg = FMC_Bank5_6->SDRTR;
|
||||
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
|
||||
|
||||
/* Disable write protection */
|
||||
tmpreg = FMC_Bank5_6->SDCR[0];
|
||||
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
|
||||
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||
/* Configure and enable Bank1_SRAM2 */
|
||||
FMC_Bank1->BTCR[2] = 0x00001011;
|
||||
FMC_Bank1->BTCR[3] = 0x00000201;
|
||||
FMC_Bank1E->BWTR[2] = 0x0fffffff;
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
#if defined(STM32F469xx) || defined(STM32F479xx)
|
||||
/* Configure and enable Bank1_SRAM2 */
|
||||
FMC_Bank1->BTCR[2] = 0x00001091;
|
||||
FMC_Bank1->BTCR[3] = 0x00110212;
|
||||
FMC_Bank1E->BWTR[2] = 0x0fffffff;
|
||||
#endif /* STM32F469xx || STM32F479xx */
|
||||
|
||||
(void)(tmp);
|
||||
}
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
|
||||
#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
|
||||
/**
|
||||
* @brief Setup the external memory controller.
|
||||
* Called in startup_stm32f4xx.s before jump to main.
|
||||
* This function configures the external memories (SRAM/SDRAM)
|
||||
* This SRAM/SDRAM will be used as program data memory (including heap and stack).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit_ExtMemCtl(void)
|
||||
{
|
||||
__IO uint32_t tmp = 0x00;
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|
||||
|| defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
|
||||
#if defined (DATA_IN_ExtSDRAM)
|
||||
register uint32_t tmpreg = 0, timeout = 0xFFFF;
|
||||
register __IO uint32_t index;
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
/* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface
|
||||
clock */
|
||||
RCC->AHB1ENR |= 0x0000007D;
|
||||
#else
|
||||
/* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
|
||||
clock */
|
||||
RCC->AHB1ENR |= 0x000001F8;
|
||||
#endif /* STM32F446xx */
|
||||
/* Delay after an RCC peripheral clock enabling */
|
||||
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);
|
||||
|
||||
#if defined(STM32F446xx)
|
||||
/* Connect PAx pins to FMC Alternate function */
|
||||
GPIOA->AFR[0] |= 0xC0000000;
|
||||
GPIOA->AFR[1] |= 0x00000000;
|
||||
/* Configure PDx pins in Alternate function mode */
|
||||
GPIOA->MODER |= 0x00008000;
|
||||
/* Configure PDx pins speed to 50 MHz */
|
||||
GPIOA->OSPEEDR |= 0x00008000;
|
||||
/* Configure PDx pins Output type to push-pull */
|
||||
GPIOA->OTYPER |= 0x00000000;
|
||||
/* No pull-up, pull-down for PDx pins */
|
||||
GPIOA->PUPDR |= 0x00000000;
|
||||
|
||||
/* Connect PCx pins to FMC Alternate function */
|
||||
GPIOC->AFR[0] |= 0x00CC0000;
|
||||
GPIOC->AFR[1] |= 0x00000000;
|
||||
/* Configure PDx pins in Alternate function mode */
|
||||
GPIOC->MODER |= 0x00000A00;
|
||||
/* Configure PDx pins speed to 50 MHz */
|
||||
GPIOC->OSPEEDR |= 0x00000A00;
|
||||
/* Configure PDx pins Output type to push-pull */
|
||||
GPIOC->OTYPER |= 0x00000000;
|
||||
/* No pull-up, pull-down for PDx pins */
|
||||
GPIOC->PUPDR |= 0x00000000;
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
/* Connect PDx pins to FMC Alternate function */
|
||||
GPIOD->AFR[0] = 0x000000CC;
|
||||
GPIOD->AFR[1] = 0xCC000CCC;
|
||||
/* Configure PDx pins in Alternate function mode */
|
||||
GPIOD->MODER = 0xA02A000A;
|
||||
/* Configure PDx pins speed to 50 MHz */
|
||||
GPIOD->OSPEEDR = 0xA02A000A;
|
||||
/* Configure PDx pins Output type to push-pull */
|
||||
GPIOD->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PDx pins */
|
||||
GPIOD->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PEx pins to FMC Alternate function */
|
||||
GPIOE->AFR[0] = 0xC00000CC;
|
||||
GPIOE->AFR[1] = 0xCCCCCCCC;
|
||||
/* Configure PEx pins in Alternate function mode */
|
||||
GPIOE->MODER = 0xAAAA800A;
|
||||
/* Configure PEx pins speed to 50 MHz */
|
||||
GPIOE->OSPEEDR = 0xAAAA800A;
|
||||
/* Configure PEx pins Output type to push-pull */
|
||||
GPIOE->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PEx pins */
|
||||
GPIOE->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PFx pins to FMC Alternate function */
|
||||
GPIOF->AFR[0] = 0xCCCCCCCC;
|
||||
GPIOF->AFR[1] = 0xCCCCCCCC;
|
||||
/* Configure PFx pins in Alternate function mode */
|
||||
GPIOF->MODER = 0xAA800AAA;
|
||||
/* Configure PFx pins speed to 50 MHz */
|
||||
GPIOF->OSPEEDR = 0xAA800AAA;
|
||||
/* Configure PFx pins Output type to push-pull */
|
||||
GPIOF->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PFx pins */
|
||||
GPIOF->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PGx pins to FMC Alternate function */
|
||||
GPIOG->AFR[0] = 0xCCCCCCCC;
|
||||
GPIOG->AFR[1] = 0xCCCCCCCC;
|
||||
/* Configure PGx pins in Alternate function mode */
|
||||
GPIOG->MODER = 0xAAAAAAAA;
|
||||
/* Configure PGx pins speed to 50 MHz */
|
||||
GPIOG->OSPEEDR = 0xAAAAAAAA;
|
||||
/* Configure PGx pins Output type to push-pull */
|
||||
GPIOG->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PGx pins */
|
||||
GPIOG->PUPDR = 0x00000000;
|
||||
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|
||||
|| defined(STM32F469xx) || defined(STM32F479xx)
|
||||
/* Connect PHx pins to FMC Alternate function */
|
||||
GPIOH->AFR[0] = 0x00C0CC00;
|
||||
GPIOH->AFR[1] = 0xCCCCCCCC;
|
||||
/* Configure PHx pins in Alternate function mode */
|
||||
GPIOH->MODER = 0xAAAA08A0;
|
||||
/* Configure PHx pins speed to 50 MHz */
|
||||
GPIOH->OSPEEDR = 0xAAAA08A0;
|
||||
/* Configure PHx pins Output type to push-pull */
|
||||
GPIOH->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PHx pins */
|
||||
GPIOH->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PIx pins to FMC Alternate function */
|
||||
GPIOI->AFR[0] = 0xCCCCCCCC;
|
||||
GPIOI->AFR[1] = 0x00000CC0;
|
||||
/* Configure PIx pins in Alternate function mode */
|
||||
GPIOI->MODER = 0x0028AAAA;
|
||||
/* Configure PIx pins speed to 50 MHz */
|
||||
GPIOI->OSPEEDR = 0x0028AAAA;
|
||||
/* Configure PIx pins Output type to push-pull */
|
||||
GPIOI->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PIx pins */
|
||||
GPIOI->PUPDR = 0x00000000;
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
|
||||
|
||||
/*-- FMC Configuration -------------------------------------------------------*/
|
||||
/* Enable the FMC interface clock */
|
||||
RCC->AHB3ENR |= 0x00000001;
|
||||
/* Delay after an RCC peripheral clock enabling */
|
||||
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
|
||||
|
||||
/* Configure and enable SDRAM bank1 */
|
||||
#if defined(STM32F446xx)
|
||||
FMC_Bank5_6->SDCR[0] = 0x00001954;
|
||||
#else
|
||||
FMC_Bank5_6->SDCR[0] = 0x000019E4;
|
||||
#endif /* STM32F446xx */
|
||||
FMC_Bank5_6->SDTR[0] = 0x01115351;
|
||||
|
||||
/* SDRAM initialization sequence */
|
||||
/* Clock enable command */
|
||||
FMC_Bank5_6->SDCMR = 0x00000011;
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
while((tmpreg != 0) && (timeout-- > 0))
|
||||
{
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
}
|
||||
|
||||
/* Delay */
|
||||
for (index = 0; index<1000; index++);
|
||||
|
||||
/* PALL command */
|
||||
FMC_Bank5_6->SDCMR = 0x00000012;
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
timeout = 0xFFFF;
|
||||
while((tmpreg != 0) && (timeout-- > 0))
|
||||
{
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
}
|
||||
|
||||
/* Auto refresh command */
|
||||
#if defined(STM32F446xx)
|
||||
FMC_Bank5_6->SDCMR = 0x000000F3;
|
||||
#else
|
||||
FMC_Bank5_6->SDCMR = 0x00000073;
|
||||
#endif /* STM32F446xx */
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
timeout = 0xFFFF;
|
||||
while((tmpreg != 0) && (timeout-- > 0))
|
||||
{
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
}
|
||||
|
||||
/* MRD register program */
|
||||
#if defined(STM32F446xx)
|
||||
FMC_Bank5_6->SDCMR = 0x00044014;
|
||||
#else
|
||||
FMC_Bank5_6->SDCMR = 0x00046014;
|
||||
#endif /* STM32F446xx */
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
timeout = 0xFFFF;
|
||||
while((tmpreg != 0) && (timeout-- > 0))
|
||||
{
|
||||
tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
|
||||
}
|
||||
|
||||
/* Set refresh count */
|
||||
tmpreg = FMC_Bank5_6->SDRTR;
|
||||
#if defined(STM32F446xx)
|
||||
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1));
|
||||
#else
|
||||
FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
|
||||
#endif /* STM32F446xx */
|
||||
|
||||
/* Disable write protection */
|
||||
tmpreg = FMC_Bank5_6->SDCR[0];
|
||||
FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
|
||||
#endif /* DATA_IN_ExtSDRAM */
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
|
||||
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
|
||||
|| defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
|
||||
|| defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
|
||||
|
||||
#if defined(DATA_IN_ExtSRAM)
|
||||
/*-- GPIOs Configuration -----------------------------------------------------*/
|
||||
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
|
||||
RCC->AHB1ENR |= 0x00000078;
|
||||
/* Delay after an RCC peripheral clock enabling */
|
||||
tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
|
||||
|
||||
/* Connect PDx pins to FMC Alternate function */
|
||||
GPIOD->AFR[0] = 0x00CCC0CC;
|
||||
GPIOD->AFR[1] = 0xCCCCCCCC;
|
||||
/* Configure PDx pins in Alternate function mode */
|
||||
GPIOD->MODER = 0xAAAA0A8A;
|
||||
/* Configure PDx pins speed to 100 MHz */
|
||||
GPIOD->OSPEEDR = 0xFFFF0FCF;
|
||||
/* Configure PDx pins Output type to push-pull */
|
||||
GPIOD->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PDx pins */
|
||||
GPIOD->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PEx pins to FMC Alternate function */
|
||||
GPIOE->AFR[0] = 0xC00CC0CC;
|
||||
GPIOE->AFR[1] = 0xCCCCCCCC;
|
||||
/* Configure PEx pins in Alternate function mode */
|
||||
GPIOE->MODER = 0xAAAA828A;
|
||||
/* Configure PEx pins speed to 100 MHz */
|
||||
GPIOE->OSPEEDR = 0xFFFFC3CF;
|
||||
/* Configure PEx pins Output type to push-pull */
|
||||
GPIOE->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PEx pins */
|
||||
GPIOE->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PFx pins to FMC Alternate function */
|
||||
GPIOF->AFR[0] = 0x00CCCCCC;
|
||||
GPIOF->AFR[1] = 0xCCCC0000;
|
||||
/* Configure PFx pins in Alternate function mode */
|
||||
GPIOF->MODER = 0xAA000AAA;
|
||||
/* Configure PFx pins speed to 100 MHz */
|
||||
GPIOF->OSPEEDR = 0xFF000FFF;
|
||||
/* Configure PFx pins Output type to push-pull */
|
||||
GPIOF->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PFx pins */
|
||||
GPIOF->PUPDR = 0x00000000;
|
||||
|
||||
/* Connect PGx pins to FMC Alternate function */
|
||||
GPIOG->AFR[0] = 0x00CCCCCC;
|
||||
GPIOG->AFR[1] = 0x000000C0;
|
||||
/* Configure PGx pins in Alternate function mode */
|
||||
GPIOG->MODER = 0x00085AAA;
|
||||
/* Configure PGx pins speed to 100 MHz */
|
||||
GPIOG->OSPEEDR = 0x000CAFFF;
|
||||
/* Configure PGx pins Output type to push-pull */
|
||||
GPIOG->OTYPER = 0x00000000;
|
||||
/* No pull-up, pull-down for PGx pins */
|
||||
GPIOG->PUPDR = 0x00000000;
|
||||
|
||||
/*-- FMC/FSMC Configuration --------------------------------------------------*/
|
||||
/* Enable the FMC/FSMC interface clock */
|
||||
RCC->AHB3ENR |= 0x00000001;
|
||||
|
||||
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
|
||||
/* Delay after an RCC peripheral clock enabling */
|
||||
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
|
||||
/* Configure and enable Bank1_SRAM2 */
|
||||
FMC_Bank1->BTCR[2] = 0x00001011;
|
||||
FMC_Bank1->BTCR[3] = 0x00000201;
|
||||
FMC_Bank1E->BWTR[2] = 0x0fffffff;
|
||||
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
|
||||
#if defined(STM32F469xx) || defined(STM32F479xx)
|
||||
/* Delay after an RCC peripheral clock enabling */
|
||||
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
|
||||
/* Configure and enable Bank1_SRAM2 */
|
||||
FMC_Bank1->BTCR[2] = 0x00001091;
|
||||
FMC_Bank1->BTCR[3] = 0x00110212;
|
||||
FMC_Bank1E->BWTR[2] = 0x0fffffff;
|
||||
#endif /* STM32F469xx || STM32F479xx */
|
||||
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\
|
||||
|| defined(STM32F412Zx) || defined(STM32F412Vx)
|
||||
/* Delay after an RCC peripheral clock enabling */
|
||||
tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);
|
||||
/* Configure and enable Bank1_SRAM2 */
|
||||
FSMC_Bank1->BTCR[2] = 0x00001011;
|
||||
FSMC_Bank1->BTCR[3] = 0x00000201;
|
||||
FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */
|
||||
|
||||
#endif /* DATA_IN_ExtSRAM */
|
||||
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
|
||||
STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */
|
||||
(void)(tmp);
|
||||
}
|
||||
#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
81
Src/tim.c
81
Src/tim.c
|
@ -24,6 +24,8 @@
|
|||
|
||||
/* USER CODE END 0 */
|
||||
|
||||
TIM_HandleTypeDef htim3;
|
||||
|
||||
/* TIM1 init function */
|
||||
void MX_TIM1_Init(void)
|
||||
{
|
||||
|
@ -129,6 +131,85 @@ void MX_TIM2_Init(void)
|
|||
/* USER CODE END TIM2_Init 2 */
|
||||
|
||||
}
|
||||
/* TIM3 init function */
|
||||
void MX_TIM3_Init(void)
|
||||
{
|
||||
|
||||
/* USER CODE BEGIN TIM3_Init 0 */
|
||||
|
||||
/* USER CODE END TIM3_Init 0 */
|
||||
|
||||
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
||||
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
||||
|
||||
/* USER CODE BEGIN TIM3_Init 1 */
|
||||
|
||||
/* USER CODE END TIM3_Init 1 */
|
||||
htim3.Instance = TIM3;
|
||||
htim3.Init.Prescaler = 89;
|
||||
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
|
||||
htim3.Init.Period = 199;
|
||||
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
||||
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
||||
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
||||
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
||||
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
||||
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
|
||||
{
|
||||
Error_Handler();
|
||||
}
|
||||
/* USER CODE BEGIN TIM3_Init 2 */
|
||||
|
||||
/* USER CODE END TIM3_Init 2 */
|
||||
|
||||
}
|
||||
|
||||
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
|
||||
{
|
||||
|
||||
if(tim_baseHandle->Instance==TIM3)
|
||||
{
|
||||
/* USER CODE BEGIN TIM3_MspInit 0 */
|
||||
|
||||
/* USER CODE END TIM3_MspInit 0 */
|
||||
/* TIM3 clock enable */
|
||||
__HAL_RCC_TIM3_CLK_ENABLE();
|
||||
|
||||
/* TIM3 interrupt Init */
|
||||
HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0);
|
||||
HAL_NVIC_EnableIRQ(TIM3_IRQn);
|
||||
/* USER CODE BEGIN TIM3_MspInit 1 */
|
||||
|
||||
/* USER CODE END TIM3_MspInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)
|
||||
{
|
||||
|
||||
if(tim_baseHandle->Instance==TIM3)
|
||||
{
|
||||
/* USER CODE BEGIN TIM3_MspDeInit 0 */
|
||||
|
||||
/* USER CODE END TIM3_MspDeInit 0 */
|
||||
/* Peripheral clock disable */
|
||||
__HAL_RCC_TIM3_CLK_DISABLE();
|
||||
|
||||
/* TIM3 interrupt Deinit */
|
||||
HAL_NVIC_DisableIRQ(TIM3_IRQn);
|
||||
/* USER CODE BEGIN TIM3_MspDeInit 1 */
|
||||
|
||||
/* USER CODE END TIM3_MspDeInit 1 */
|
||||
}
|
||||
}
|
||||
|
||||
/* USER CODE BEGIN 1 */
|
||||
|
||||
|
|
|
@ -7,6 +7,9 @@
|
|||
;
|
||||
; Please visit documentation for the other options and examples
|
||||
; https://docs.platformio.org/page/projectconf.html
|
||||
[platformio]
|
||||
include_dir = Inc
|
||||
src_dir = Src
|
||||
|
||||
[env:robotroller]
|
||||
platform = ststm32
|
||||
|
@ -16,10 +19,10 @@ board_build.stm32cube.custom_config_header = yes
|
|||
build_flags =
|
||||
-D USE_FULL_LL_DRIVER
|
||||
-D USE_HAL_DRIVER
|
||||
|
||||
|
||||
board_build.stm32cube.startup = startup_stm32f446retx.s
|
||||
board_build.stm32cube.ldscript = STM32F446RETx_FLASH.ld
|
||||
; board_upload.offset_address = 0x08008000
|
||||
upload_protocol = stlink
|
||||
[platformio]
|
||||
include_dir = Inc
|
||||
src_dir = Src
|
||||
debug_tool = stlink
|
||||
|
||||
|
|
|
@ -46,7 +46,8 @@ Mcu.CPN=STM32F446RET6
|
|||
Mcu.Family=STM32F4
|
||||
Mcu.IP0=ADC1
|
||||
Mcu.IP1=CAN1
|
||||
Mcu.IP10=USART2
|
||||
Mcu.IP10=USART1
|
||||
Mcu.IP11=USART2
|
||||
Mcu.IP2=CAN2
|
||||
Mcu.IP3=NVIC
|
||||
Mcu.IP4=RCC
|
||||
|
@ -54,8 +55,8 @@ Mcu.IP5=SPI2
|
|||
Mcu.IP6=SYS
|
||||
Mcu.IP7=TIM1
|
||||
Mcu.IP8=TIM2
|
||||
Mcu.IP9=USART1
|
||||
Mcu.IPNb=11
|
||||
Mcu.IP9=TIM3
|
||||
Mcu.IPNb=12
|
||||
Mcu.Name=STM32F446R(C-E)Tx
|
||||
Mcu.Package=LQFP64
|
||||
Mcu.Pin0=PH0-OSC_IN
|
||||
|
@ -88,13 +89,14 @@ Mcu.Pin32=PB9
|
|||
Mcu.Pin33=VP_SYS_VS_Systick
|
||||
Mcu.Pin34=VP_TIM1_VS_no_output4
|
||||
Mcu.Pin35=VP_TIM2_VS_ClockSourceINT
|
||||
Mcu.Pin36=VP_TIM3_VS_ClockSourceINT
|
||||
Mcu.Pin4=PA1
|
||||
Mcu.Pin5=PA2
|
||||
Mcu.Pin6=PA3
|
||||
Mcu.Pin7=PA4
|
||||
Mcu.Pin8=PA5
|
||||
Mcu.Pin9=PA6
|
||||
Mcu.PinsNb=36
|
||||
Mcu.PinsNb=37
|
||||
Mcu.ThirdPartyNb=0
|
||||
Mcu.UserConstants=
|
||||
Mcu.UserName=STM32F446RETx
|
||||
|
@ -114,6 +116,7 @@ NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false
|
|||
NVIC.TIM1_BRK_TIM9_IRQn=true\:1\:0\:true\:true\:true\:1\:true\:true\:true
|
||||
NVIC.TIM1_CC_IRQn=true\:3\:0\:true\:true\:true\:2\:true\:true\:true
|
||||
NVIC.TIM2_IRQn=true\:4\:0\:true\:true\:true\:3\:true\:true\:true
|
||||
NVIC.TIM3_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
|
||||
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
|
||||
PA0-WKUP.Mode=CTS_RTS
|
||||
PA0-WKUP.Signal=USART2_CTS
|
||||
|
@ -229,13 +232,13 @@ ProjectManager.NoMain=false
|
|||
ProjectManager.PreviousToolchain=STM32CubeIDE
|
||||
ProjectManager.ProjectBuild=false
|
||||
ProjectManager.ProjectFileName=processor32f446.ioc
|
||||
ProjectManager.ProjectName=robotroller_platformio
|
||||
ProjectManager.ProjectName=processor32f446
|
||||
ProjectManager.RegisterCallBack=
|
||||
ProjectManager.StackSize=0x400
|
||||
ProjectManager.TargetToolchain=Other Toolchains (GPDSC)
|
||||
ProjectManager.ToolChainLocation=
|
||||
ProjectManager.UnderRoot=false
|
||||
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_ADC1_Init-ADC1-false-LL-true,4-MX_TIM1_Init-TIM1-false-LL-true,5-MX_USART1_UART_Init-USART1-false-LL-true,6-MX_USART2_UART_Init-USART2-false-LL-true,7-MX_TIM2_Init-TIM2-false-LL-true,8-MX_SPI2_Init-SPI2-false-LL-true,9-MX_CAN1_Init-CAN1-false-HAL-true,10-MX_CAN2_Init-CAN2-false-HAL-true
|
||||
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-LL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_ADC1_Init-ADC1-false-LL-true,4-MX_TIM1_Init-TIM1-false-LL-true,5-MX_USART1_UART_Init-USART1-false-LL-true,6-MX_USART2_UART_Init-USART2-false-LL-true,7-MX_TIM2_Init-TIM2-false-LL-true,8-MX_SPI2_Init-SPI2-false-LL-true,9-MX_CAN1_Init-CAN1-false-HAL-true,10-MX_CAN2_Init-CAN2-false-HAL-true,11-MX_TIM3_Init-TIM3-false-HAL-true
|
||||
RCC.AHBFreq_Value=180000000
|
||||
RCC.APB1CLKDivider=RCC_HCLK_DIV4
|
||||
RCC.APB1Freq_Value=45000000
|
||||
|
@ -320,6 +323,9 @@ TIM1.OffStateRunMode=TIM_OSSR_DISABLE
|
|||
TIM1.TIM_MasterOutputTrigger=TIM_TRGO_OC4REF
|
||||
TIM2.IPParameters=TIM_MasterOutputTrigger
|
||||
TIM2.TIM_MasterOutputTrigger=TIM_TRGO_UPDATE
|
||||
TIM3.IPParameters=Period,Prescaler
|
||||
TIM3.Period=199
|
||||
TIM3.Prescaler=89
|
||||
USART1.IPParameters=VirtualMode
|
||||
USART1.VirtualMode=VM_ASYNC
|
||||
USART2.IPParameters=VirtualMode
|
||||
|
@ -330,4 +336,6 @@ VP_TIM1_VS_no_output4.Mode=PWM Generation4 No Output
|
|||
VP_TIM1_VS_no_output4.Signal=TIM1_VS_no_output4
|
||||
VP_TIM2_VS_ClockSourceINT.Mode=Internal
|
||||
VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT
|
||||
VP_TIM3_VS_ClockSourceINT.Mode=Internal
|
||||
VP_TIM3_VS_ClockSourceINT.Signal=TIM3_VS_ClockSourceINT
|
||||
board=custom
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue