Added CAN
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on4ip84
parent
526b689693
commit
fc1f245eb2
13 changed files with 489 additions and 183 deletions
245
Src/main.c
245
Src/main.c
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@ -27,7 +27,9 @@
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/* Private includes ----------------------------------------------------------*/
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/* USER CODE BEGIN Includes */
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#include "CAN_API.h"
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#include "InitDrive.h"
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/* USER CODE END Includes */
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/* Private typedef -----------------------------------------------------------*/
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@ -69,47 +71,49 @@ static void MX_NVIC_Init(void);
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/* USER CODE END 0 */
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/**
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* @brief The application entry point.
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* @retval int
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*/
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int main(void) {
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/* USER CODE BEGIN 1 */
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* @brief The application entry point.
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* @retval int
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*/
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int main(void)
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{
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/* USER CODE BEGIN 1 */
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__disable_irq();
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/* USER CODE END 1 */
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/* USER CODE END 1 */
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/* MCU Configuration--------------------------------------------------------*/
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/* MCU Configuration--------------------------------------------------------*/
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/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
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HAL_Init();
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/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
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HAL_Init();
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/* USER CODE BEGIN Init */
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/* USER CODE BEGIN Init */
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SysTick_Config(0xFFFFFF);
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LL_DBGMCU_APB1_GRP1_FreezePeriph( LL_DBGMCU_APB1_GRP1_TIM3_STOP);
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LL_DBGMCU_APB1_GRP1_FreezePeriph( LL_DBGMCU_APB1_GRP1_TIM2_STOP);
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LL_DBGMCU_APB2_GRP1_FreezePeriph( LL_DBGMCU_APB2_GRP1_TIM1_STOP);
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LL_DBGMCU_APB2_GRP1_FreezePeriph( LL_DBGMCU_APB2_GRP1_TIM8_STOP);
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/* USER CODE END Init */
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/* USER CODE END Init */
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/* Configure the system clock */
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SystemClock_Config();
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/* Configure the system clock */
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SystemClock_Config();
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/* USER CODE BEGIN SysInit */
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/* USER CODE BEGIN SysInit */
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SystemCoreClockUpdate();
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/* USER CODE END SysInit */
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/* USER CODE END SysInit */
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/* Initialize all configured peripherals */
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MX_GPIO_Init();
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MX_ADC1_Init();
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MX_TIM1_Init();
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MX_USART1_UART_Init();
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MX_USART2_UART_Init();
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MX_CAN2_Init();
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MX_TIM2_Init();
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MX_SPI2_Init();
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/* Initialize all configured peripherals */
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MX_GPIO_Init();
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MX_ADC1_Init();
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MX_TIM1_Init();
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MX_USART1_UART_Init();
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MX_USART2_UART_Init();
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MX_TIM2_Init();
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MX_SPI2_Init();
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MX_CAN1_Init();
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MX_CAN2_Init();
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/* Initialize interrupts */
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MX_NVIC_Init();
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/* USER CODE BEGIN 2 */
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/* Initialize interrupts */
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MX_NVIC_Init();
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/* USER CODE BEGIN 2 */
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LL_GPIO_ResetOutputPin(LED1_GPIO_Port, LED1_Pin);
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LL_GPIO_ResetOutputPin(LED2_GPIO_Port, LED2_Pin);
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@ -131,24 +135,27 @@ int main(void) {
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LL_TIM_EnableCounter(TIM2);
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LL_GPIO_SetOutputPin(AS5045_CS_GPIO_Port, AS5045_CS_Pin);
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LL_SPI_SetBaudRatePrescaler(SPI2,LL_SPI_BAUDRATEPRESCALER_DIV64 );
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LL_SPI_SetBaudRatePrescaler(SPI2, LL_SPI_BAUDRATEPRESCALER_DIV64);
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LL_SPI_Enable(SPI2);
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/*Init Control structure*/
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float TSAMPLE_FAST = 1.f / PWM_FRQ_HZ;
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float TSAMPLE_SLOW = 1.f / ALG_TIMER_HZ;
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DriveInit(TSAMPLE_FAST, TSAMPLE_SLOW);
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//initCAN(CAN_BAUD_1000);
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__enable_irq();
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/* USER CODE END 2 */
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/* USER CODE END 2 */
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/* Infinite loop */
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/* USER CODE BEGIN WHILE */
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/* Infinite loop */
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/* USER CODE BEGIN WHILE */
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while (1) {
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/* USER CODE END WHILE */
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/* USER CODE END WHILE */
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/* USER CODE BEGIN 3 */
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/* USER CODE BEGIN 3 */
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if (!LL_SPI_IsActiveFlag_OVR(SPI2)) {
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LL_GPIO_ResetOutputPin(AS5045_CS_GPIO_Port, AS5045_CS_Pin);
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while (!LL_SPI_IsActiveFlag_TXE(SPI2)){};
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while (!LL_SPI_IsActiveFlag_TXE(SPI2)) {
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};
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LL_SPI_TransmitData16(SPI2, 0xFFFF);
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while (!LL_SPI_IsActiveFlag_RXNE(SPI2)) {
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}
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@ -159,79 +166,114 @@ int main(void) {
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} else {
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LL_SPI_ClearFlag_OVR(SPI2);
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}
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CAN_TxHeaderTypeDef txheader;
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uint8_t txdata[8];
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txheader.DLC = 8;
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txheader.ExtId = 0x11111111;
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txheader.IDE = CAN_ID_STD;
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txheader.RTR = CAN_RTR_DATA;
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for (uint8_t i = 0; i < 8; i++) {
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txdata[i] = i;
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}
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static uint32_t txMailBox = 0;
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if (HAL_CAN_AddTxMessage(&hcan2, &txheader, txdata,
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(uint32_t*) &txMailBox) != HAL_OK) {
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HAL_CAN_AbortTxRequest(&hcan2,
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CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2);
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}
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/*
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if (HAL_CAN_AddTxMessage(&hcan1, &txheader, txdata,
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(uint32_t*) &txMailBox) != HAL_OK) {
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HAL_CAN_AbortTxRequest(&hcan1,
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CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2);
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}
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if (HAL_CAN_AddTxMessage(&hcan2, &txheader, txdata,
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(uint32_t*) &txMailBox) != HAL_OK) {
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HAL_CAN_AbortTxRequest(&hcan2,
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CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2);
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}
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*/
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HAL_Delay(10);
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static uint16_t state =0;
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//state = HAL_CAN_GetState(&hcan2);
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//LL_GPIO_TogglePin(CAN2_RX_GPIO_Port, CAN2_RX_Pin);
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//LL_GPIO_TogglePin(CAN2_TX_GPIO_Port, CAN2_TX_Pin);
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}
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/* USER CODE END 3 */
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/* USER CODE END 3 */
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}
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/**
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* @brief System Clock Configuration
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* @retval None
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*/
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void SystemClock_Config(void) {
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LL_FLASH_SetLatency(LL_FLASH_LATENCY_5);
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while (LL_FLASH_GetLatency() != LL_FLASH_LATENCY_5) {
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}
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LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
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LL_PWR_EnableOverDriveMode();
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LL_RCC_HSE_Enable();
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* @brief System Clock Configuration
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* @retval None
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*/
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void SystemClock_Config(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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/* Wait till HSE is ready */
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while (LL_RCC_HSE_IsReady() != 1) {
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/** Configure the main internal regulator output voltage
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*/
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__HAL_RCC_PWR_CLK_ENABLE();
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__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
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}
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LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLLM_DIV_4, 180,
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LL_RCC_PLLP_DIV_2);
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LL_RCC_PLL_Enable();
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/** Initializes the RCC Oscillators according to the specified parameters
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* in the RCC_OscInitTypeDef structure.
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 4;
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RCC_OscInitStruct.PLL.PLLN = 180;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = 2;
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RCC_OscInitStruct.PLL.PLLR = 2;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
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{
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Error_Handler();
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}
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/* Wait till PLL is ready */
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while (LL_RCC_PLL_IsReady() != 1) {
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/** Activate the Over-Drive mode
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*/
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if (HAL_PWREx_EnableOverDrive() != HAL_OK)
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{
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Error_Handler();
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}
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}
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LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
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LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_4);
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LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2);
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
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/** Initializes the CPU, AHB and APB buses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
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|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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/* Wait till System clock is ready */
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while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {
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}
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LL_SetSystemCoreClock(180000000);
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/* Update the time base */
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if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) {
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Error_Handler();
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}
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LL_RCC_SetTIMPrescaler(LL_RCC_TIM_PRESCALER_TWICE);
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
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{
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Error_Handler();
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}
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}
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/**
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* @brief NVIC Configuration.
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* @retval None
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*/
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static void MX_NVIC_Init(void) {
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/* TIM1_BRK_TIM9_IRQn interrupt configuration */
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NVIC_SetPriority(TIM1_BRK_TIM9_IRQn,
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NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 1, 0));
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NVIC_EnableIRQ(TIM1_BRK_TIM9_IRQn);
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/* TIM1_CC_IRQn interrupt configuration */
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NVIC_SetPriority(TIM1_CC_IRQn,
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NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 3, 0));
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NVIC_EnableIRQ(TIM1_CC_IRQn);
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/* TIM2_IRQn interrupt configuration */
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NVIC_SetPriority(TIM2_IRQn,
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NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 4, 0));
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NVIC_EnableIRQ(TIM2_IRQn);
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/* ADC_IRQn interrupt configuration */
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NVIC_SetPriority(ADC_IRQn,
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NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 2, 0));
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NVIC_EnableIRQ(ADC_IRQn);
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/* CAN2_RX0_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(CAN2_RX0_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(CAN2_RX0_IRQn);
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/* CAN2_RX1_IRQn interrupt configuration */
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HAL_NVIC_SetPriority(CAN2_RX1_IRQn, 5, 0);
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HAL_NVIC_EnableIRQ(CAN2_RX1_IRQn);
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* @brief NVIC Configuration.
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* @retval None
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*/
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static void MX_NVIC_Init(void)
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{
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/* TIM1_BRK_TIM9_IRQn interrupt configuration */
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NVIC_SetPriority(TIM1_BRK_TIM9_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),1, 0));
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NVIC_EnableIRQ(TIM1_BRK_TIM9_IRQn);
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/* TIM1_CC_IRQn interrupt configuration */
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NVIC_SetPriority(TIM1_CC_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),3, 0));
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NVIC_EnableIRQ(TIM1_CC_IRQn);
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/* TIM2_IRQn interrupt configuration */
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NVIC_SetPriority(TIM2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),4, 0));
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NVIC_EnableIRQ(TIM2_IRQn);
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/* ADC_IRQn interrupt configuration */
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NVIC_SetPriority(ADC_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),2, 0));
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NVIC_EnableIRQ(ADC_IRQn);
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}
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/* USER CODE BEGIN 4 */
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@ -239,16 +281,17 @@ static void MX_NVIC_Init(void) {
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/* USER CODE END 4 */
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/**
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* @brief This function is executed in case of error occurrence.
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* @retval None
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*/
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void Error_Handler(void) {
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/* USER CODE BEGIN Error_Handler_Debug */
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* @brief This function is executed in case of error occurrence.
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* @retval None
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*/
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void Error_Handler(void)
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{
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/* USER CODE BEGIN Error_Handler_Debug */
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/* User can add his own implementation to report the HAL error return state */
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__disable_irq();
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while (1) {
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}
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/* USER CODE END Error_Handler_Debug */
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/* USER CODE END Error_Handler_Debug */
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}
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#ifdef USE_FULL_ASSERT
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