robossembler/servo
7
0
Fork 0
Code Issues 27 Pull requests 2 Projects 1 Releases 1 Packages Wiki Activity Actions
servo/controller/fw/bootloader/Debug/bootloader_.list

14917 lines
554 KiB
Text
Raw Blame History

This file contains ambiguous Unicode characters

This file contains Unicode characters that might be confused with other characters. If you think that this is intentional, you can safely ignore this warning. Use the Escape button to reveal them.

bootloader_.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001c4 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00005880 080001c4 080001c4 000011c4 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 00000018 08005a44 08005a44 00006a44 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08005a5c 08005a5c 00007014 2**0
CONTENTS
4 .ARM 00000008 08005a5c 08005a5c 00006a5c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08005a64 08005a64 00007014 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08005a64 08005a64 00006a64 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 08005a68 08005a68 00006a68 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 00000014 20000000 08005a6c 00007000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000002b8 20000014 08005a80 00007014 2**2
ALLOC
10 ._user_heap_stack 00000604 200002cc 08005a80 000072cc 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 00007014 2**0
CONTENTS, READONLY
12 .debug_info 00017a70 00000000 00000000 00007044 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00003f43 00000000 00000000 0001eab4 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 000014c0 00000000 00000000 000229f8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 0000100e 00000000 00000000 00023eb8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 00025b05 00000000 00000000 00024ec6 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 0001b6d6 00000000 00000000 0004a9cb 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 000e2d70 00000000 00000000 000660a1 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 00148e11 2**0
CONTENTS, READONLY
20 .debug_frame 000055c8 00000000 00000000 00148e54 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000050 00000000 00000000 0014e41c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001c4 <__do_global_dtors_aux>:
80001c4: b510 push {r4, lr}
80001c6: 4c05 ldr r4, [pc, #20] @ (80001dc <__do_global_dtors_aux+0x18>)
80001c8: 7823 ldrb r3, [r4, #0]
80001ca: b933 cbnz r3, 80001da <__do_global_dtors_aux+0x16>
80001cc: 4b04 ldr r3, [pc, #16] @ (80001e0 <__do_global_dtors_aux+0x1c>)
80001ce: b113 cbz r3, 80001d6 <__do_global_dtors_aux+0x12>
80001d0: 4804 ldr r0, [pc, #16] @ (80001e4 <__do_global_dtors_aux+0x20>)
80001d2: f3af 8000 nop.w
80001d6: 2301 movs r3, #1
80001d8: 7023 strb r3, [r4, #0]
80001da: bd10 pop {r4, pc}
80001dc: 20000014 .word 0x20000014
80001e0: 00000000 .word 0x00000000
80001e4: 08005a2c .word 0x08005a2c
080001e8 <frame_dummy>:
80001e8: b508 push {r3, lr}
80001ea: 4b03 ldr r3, [pc, #12] @ (80001f8 <frame_dummy+0x10>)
80001ec: b11b cbz r3, 80001f6 <frame_dummy+0xe>
80001ee: 4903 ldr r1, [pc, #12] @ (80001fc <frame_dummy+0x14>)
80001f0: 4803 ldr r0, [pc, #12] @ (8000200 <frame_dummy+0x18>)
80001f2: f3af 8000 nop.w
80001f6: bd08 pop {r3, pc}
80001f8: 00000000 .word 0x00000000
80001fc: 20000018 .word 0x20000018
8000200: 08005a2c .word 0x08005a2c
08000204 <__aeabi_uldivmod>:
8000204: b953 cbnz r3, 800021c <__aeabi_uldivmod+0x18>
8000206: b94a cbnz r2, 800021c <__aeabi_uldivmod+0x18>
8000208: 2900 cmp r1, #0
800020a: bf08 it eq
800020c: 2800 cmpeq r0, #0
800020e: bf1c itt ne
8000210: f04f 31ff movne.w r1, #4294967295
8000214: f04f 30ff movne.w r0, #4294967295
8000218: f000 b96a b.w 80004f0 <__aeabi_idiv0>
800021c: f1ad 0c08 sub.w ip, sp, #8
8000220: e96d ce04 strd ip, lr, [sp, #-16]!
8000224: f000 f806 bl 8000234 <__udivmoddi4>
8000228: f8dd e004 ldr.w lr, [sp, #4]
800022c: e9dd 2302 ldrd r2, r3, [sp, #8]
8000230: b004 add sp, #16
8000232: 4770 bx lr
08000234 <__udivmoddi4>:
8000234: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
8000238: 9d08 ldr r5, [sp, #32]
800023a: 460c mov r4, r1
800023c: 2b00 cmp r3, #0
800023e: d14e bne.n 80002de <__udivmoddi4+0xaa>
8000240: 4694 mov ip, r2
8000242: 458c cmp ip, r1
8000244: 4686 mov lr, r0
8000246: fab2 f282 clz r2, r2
800024a: d962 bls.n 8000312 <__udivmoddi4+0xde>
800024c: b14a cbz r2, 8000262 <__udivmoddi4+0x2e>
800024e: f1c2 0320 rsb r3, r2, #32
8000252: 4091 lsls r1, r2
8000254: fa20 f303 lsr.w r3, r0, r3
8000258: fa0c fc02 lsl.w ip, ip, r2
800025c: 4319 orrs r1, r3
800025e: fa00 fe02 lsl.w lr, r0, r2
8000262: ea4f 471c mov.w r7, ip, lsr #16
8000266: fa1f f68c uxth.w r6, ip
800026a: fbb1 f4f7 udiv r4, r1, r7
800026e: ea4f 431e mov.w r3, lr, lsr #16
8000272: fb07 1114 mls r1, r7, r4, r1
8000276: ea43 4301 orr.w r3, r3, r1, lsl #16
800027a: fb04 f106 mul.w r1, r4, r6
800027e: 4299 cmp r1, r3
8000280: d90a bls.n 8000298 <__udivmoddi4+0x64>
8000282: eb1c 0303 adds.w r3, ip, r3
8000286: f104 30ff add.w r0, r4, #4294967295
800028a: f080 8112 bcs.w 80004b2 <__udivmoddi4+0x27e>
800028e: 4299 cmp r1, r3
8000290: f240 810f bls.w 80004b2 <__udivmoddi4+0x27e>
8000294: 3c02 subs r4, #2
8000296: 4463 add r3, ip
8000298: 1a59 subs r1, r3, r1
800029a: fa1f f38e uxth.w r3, lr
800029e: fbb1 f0f7 udiv r0, r1, r7
80002a2: fb07 1110 mls r1, r7, r0, r1
80002a6: ea43 4301 orr.w r3, r3, r1, lsl #16
80002aa: fb00 f606 mul.w r6, r0, r6
80002ae: 429e cmp r6, r3
80002b0: d90a bls.n 80002c8 <__udivmoddi4+0x94>
80002b2: eb1c 0303 adds.w r3, ip, r3
80002b6: f100 31ff add.w r1, r0, #4294967295
80002ba: f080 80fc bcs.w 80004b6 <__udivmoddi4+0x282>
80002be: 429e cmp r6, r3
80002c0: f240 80f9 bls.w 80004b6 <__udivmoddi4+0x282>
80002c4: 4463 add r3, ip
80002c6: 3802 subs r0, #2
80002c8: 1b9b subs r3, r3, r6
80002ca: ea40 4004 orr.w r0, r0, r4, lsl #16
80002ce: 2100 movs r1, #0
80002d0: b11d cbz r5, 80002da <__udivmoddi4+0xa6>
80002d2: 40d3 lsrs r3, r2
80002d4: 2200 movs r2, #0
80002d6: e9c5 3200 strd r3, r2, [r5]
80002da: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002de: 428b cmp r3, r1
80002e0: d905 bls.n 80002ee <__udivmoddi4+0xba>
80002e2: b10d cbz r5, 80002e8 <__udivmoddi4+0xb4>
80002e4: e9c5 0100 strd r0, r1, [r5]
80002e8: 2100 movs r1, #0
80002ea: 4608 mov r0, r1
80002ec: e7f5 b.n 80002da <__udivmoddi4+0xa6>
80002ee: fab3 f183 clz r1, r3
80002f2: 2900 cmp r1, #0
80002f4: d146 bne.n 8000384 <__udivmoddi4+0x150>
80002f6: 42a3 cmp r3, r4
80002f8: d302 bcc.n 8000300 <__udivmoddi4+0xcc>
80002fa: 4290 cmp r0, r2
80002fc: f0c0 80f0 bcc.w 80004e0 <__udivmoddi4+0x2ac>
8000300: 1a86 subs r6, r0, r2
8000302: eb64 0303 sbc.w r3, r4, r3
8000306: 2001 movs r0, #1
8000308: 2d00 cmp r5, #0
800030a: d0e6 beq.n 80002da <__udivmoddi4+0xa6>
800030c: e9c5 6300 strd r6, r3, [r5]
8000310: e7e3 b.n 80002da <__udivmoddi4+0xa6>
8000312: 2a00 cmp r2, #0
8000314: f040 8090 bne.w 8000438 <__udivmoddi4+0x204>
8000318: eba1 040c sub.w r4, r1, ip
800031c: ea4f 481c mov.w r8, ip, lsr #16
8000320: fa1f f78c uxth.w r7, ip
8000324: 2101 movs r1, #1
8000326: fbb4 f6f8 udiv r6, r4, r8
800032a: ea4f 431e mov.w r3, lr, lsr #16
800032e: fb08 4416 mls r4, r8, r6, r4
8000332: ea43 4304 orr.w r3, r3, r4, lsl #16
8000336: fb07 f006 mul.w r0, r7, r6
800033a: 4298 cmp r0, r3
800033c: d908 bls.n 8000350 <__udivmoddi4+0x11c>
800033e: eb1c 0303 adds.w r3, ip, r3
8000342: f106 34ff add.w r4, r6, #4294967295
8000346: d202 bcs.n 800034e <__udivmoddi4+0x11a>
8000348: 4298 cmp r0, r3
800034a: f200 80cd bhi.w 80004e8 <__udivmoddi4+0x2b4>
800034e: 4626 mov r6, r4
8000350: 1a1c subs r4, r3, r0
8000352: fa1f f38e uxth.w r3, lr
8000356: fbb4 f0f8 udiv r0, r4, r8
800035a: fb08 4410 mls r4, r8, r0, r4
800035e: ea43 4304 orr.w r3, r3, r4, lsl #16
8000362: fb00 f707 mul.w r7, r0, r7
8000366: 429f cmp r7, r3
8000368: d908 bls.n 800037c <__udivmoddi4+0x148>
800036a: eb1c 0303 adds.w r3, ip, r3
800036e: f100 34ff add.w r4, r0, #4294967295
8000372: d202 bcs.n 800037a <__udivmoddi4+0x146>
8000374: 429f cmp r7, r3
8000376: f200 80b0 bhi.w 80004da <__udivmoddi4+0x2a6>
800037a: 4620 mov r0, r4
800037c: 1bdb subs r3, r3, r7
800037e: ea40 4006 orr.w r0, r0, r6, lsl #16
8000382: e7a5 b.n 80002d0 <__udivmoddi4+0x9c>
8000384: f1c1 0620 rsb r6, r1, #32
8000388: 408b lsls r3, r1
800038a: fa22 f706 lsr.w r7, r2, r6
800038e: 431f orrs r7, r3
8000390: fa20 fc06 lsr.w ip, r0, r6
8000394: fa04 f301 lsl.w r3, r4, r1
8000398: ea43 030c orr.w r3, r3, ip
800039c: 40f4 lsrs r4, r6
800039e: fa00 f801 lsl.w r8, r0, r1
80003a2: 0c38 lsrs r0, r7, #16
80003a4: ea4f 4913 mov.w r9, r3, lsr #16
80003a8: fbb4 fef0 udiv lr, r4, r0
80003ac: fa1f fc87 uxth.w ip, r7
80003b0: fb00 441e mls r4, r0, lr, r4
80003b4: ea49 4404 orr.w r4, r9, r4, lsl #16
80003b8: fb0e f90c mul.w r9, lr, ip
80003bc: 45a1 cmp r9, r4
80003be: fa02 f201 lsl.w r2, r2, r1
80003c2: d90a bls.n 80003da <__udivmoddi4+0x1a6>
80003c4: 193c adds r4, r7, r4
80003c6: f10e 3aff add.w sl, lr, #4294967295
80003ca: f080 8084 bcs.w 80004d6 <__udivmoddi4+0x2a2>
80003ce: 45a1 cmp r9, r4
80003d0: f240 8081 bls.w 80004d6 <__udivmoddi4+0x2a2>
80003d4: f1ae 0e02 sub.w lr, lr, #2
80003d8: 443c add r4, r7
80003da: eba4 0409 sub.w r4, r4, r9
80003de: fa1f f983 uxth.w r9, r3
80003e2: fbb4 f3f0 udiv r3, r4, r0
80003e6: fb00 4413 mls r4, r0, r3, r4
80003ea: ea49 4404 orr.w r4, r9, r4, lsl #16
80003ee: fb03 fc0c mul.w ip, r3, ip
80003f2: 45a4 cmp ip, r4
80003f4: d907 bls.n 8000406 <__udivmoddi4+0x1d2>
80003f6: 193c adds r4, r7, r4
80003f8: f103 30ff add.w r0, r3, #4294967295
80003fc: d267 bcs.n 80004ce <__udivmoddi4+0x29a>
80003fe: 45a4 cmp ip, r4
8000400: d965 bls.n 80004ce <__udivmoddi4+0x29a>
8000402: 3b02 subs r3, #2
8000404: 443c add r4, r7
8000406: ea43 400e orr.w r0, r3, lr, lsl #16
800040a: fba0 9302 umull r9, r3, r0, r2
800040e: eba4 040c sub.w r4, r4, ip
8000412: 429c cmp r4, r3
8000414: 46ce mov lr, r9
8000416: 469c mov ip, r3
8000418: d351 bcc.n 80004be <__udivmoddi4+0x28a>
800041a: d04e beq.n 80004ba <__udivmoddi4+0x286>
800041c: b155 cbz r5, 8000434 <__udivmoddi4+0x200>
800041e: ebb8 030e subs.w r3, r8, lr
8000422: eb64 040c sbc.w r4, r4, ip
8000426: fa04 f606 lsl.w r6, r4, r6
800042a: 40cb lsrs r3, r1
800042c: 431e orrs r6, r3
800042e: 40cc lsrs r4, r1
8000430: e9c5 6400 strd r6, r4, [r5]
8000434: 2100 movs r1, #0
8000436: e750 b.n 80002da <__udivmoddi4+0xa6>
8000438: f1c2 0320 rsb r3, r2, #32
800043c: fa20 f103 lsr.w r1, r0, r3
8000440: fa0c fc02 lsl.w ip, ip, r2
8000444: fa24 f303 lsr.w r3, r4, r3
8000448: 4094 lsls r4, r2
800044a: 430c orrs r4, r1
800044c: ea4f 481c mov.w r8, ip, lsr #16
8000450: fa00 fe02 lsl.w lr, r0, r2
8000454: fa1f f78c uxth.w r7, ip
8000458: fbb3 f0f8 udiv r0, r3, r8
800045c: fb08 3110 mls r1, r8, r0, r3
8000460: 0c23 lsrs r3, r4, #16
8000462: ea43 4301 orr.w r3, r3, r1, lsl #16
8000466: fb00 f107 mul.w r1, r0, r7
800046a: 4299 cmp r1, r3
800046c: d908 bls.n 8000480 <__udivmoddi4+0x24c>
800046e: eb1c 0303 adds.w r3, ip, r3
8000472: f100 36ff add.w r6, r0, #4294967295
8000476: d22c bcs.n 80004d2 <__udivmoddi4+0x29e>
8000478: 4299 cmp r1, r3
800047a: d92a bls.n 80004d2 <__udivmoddi4+0x29e>
800047c: 3802 subs r0, #2
800047e: 4463 add r3, ip
8000480: 1a5b subs r3, r3, r1
8000482: b2a4 uxth r4, r4
8000484: fbb3 f1f8 udiv r1, r3, r8
8000488: fb08 3311 mls r3, r8, r1, r3
800048c: ea44 4403 orr.w r4, r4, r3, lsl #16
8000490: fb01 f307 mul.w r3, r1, r7
8000494: 42a3 cmp r3, r4
8000496: d908 bls.n 80004aa <__udivmoddi4+0x276>
8000498: eb1c 0404 adds.w r4, ip, r4
800049c: f101 36ff add.w r6, r1, #4294967295
80004a0: d213 bcs.n 80004ca <__udivmoddi4+0x296>
80004a2: 42a3 cmp r3, r4
80004a4: d911 bls.n 80004ca <__udivmoddi4+0x296>
80004a6: 3902 subs r1, #2
80004a8: 4464 add r4, ip
80004aa: 1ae4 subs r4, r4, r3
80004ac: ea41 4100 orr.w r1, r1, r0, lsl #16
80004b0: e739 b.n 8000326 <__udivmoddi4+0xf2>
80004b2: 4604 mov r4, r0
80004b4: e6f0 b.n 8000298 <__udivmoddi4+0x64>
80004b6: 4608 mov r0, r1
80004b8: e706 b.n 80002c8 <__udivmoddi4+0x94>
80004ba: 45c8 cmp r8, r9
80004bc: d2ae bcs.n 800041c <__udivmoddi4+0x1e8>
80004be: ebb9 0e02 subs.w lr, r9, r2
80004c2: eb63 0c07 sbc.w ip, r3, r7
80004c6: 3801 subs r0, #1
80004c8: e7a8 b.n 800041c <__udivmoddi4+0x1e8>
80004ca: 4631 mov r1, r6
80004cc: e7ed b.n 80004aa <__udivmoddi4+0x276>
80004ce: 4603 mov r3, r0
80004d0: e799 b.n 8000406 <__udivmoddi4+0x1d2>
80004d2: 4630 mov r0, r6
80004d4: e7d4 b.n 8000480 <__udivmoddi4+0x24c>
80004d6: 46d6 mov lr, sl
80004d8: e77f b.n 80003da <__udivmoddi4+0x1a6>
80004da: 4463 add r3, ip
80004dc: 3802 subs r0, #2
80004de: e74d b.n 800037c <__udivmoddi4+0x148>
80004e0: 4606 mov r6, r0
80004e2: 4623 mov r3, r4
80004e4: 4608 mov r0, r1
80004e6: e70f b.n 8000308 <__udivmoddi4+0xd4>
80004e8: 3e02 subs r6, #2
80004ea: 4463 add r3, ip
80004ec: e730 b.n 8000350 <__udivmoddi4+0x11c>
80004ee: bf00 nop
080004f0 <__aeabi_idiv0>:
80004f0: 4770 bx lr
80004f2: bf00 nop
080004f4 <MX_ADC2_Init>:
ADC_HandleTypeDef hadc2;
/* ADC2 init function */
void MX_ADC2_Init(void)
{
80004f4: b580 push {r7, lr}
80004f6: b084 sub sp, #16
80004f8: af00 add r7, sp, #0
/* USER CODE BEGIN ADC2_Init 0 */
/* USER CODE END ADC2_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
80004fa: 463b mov r3, r7
80004fc: 2200 movs r2, #0
80004fe: 601a str r2, [r3, #0]
8000500: 605a str r2, [r3, #4]
8000502: 609a str r2, [r3, #8]
8000504: 60da str r2, [r3, #12]
/* USER CODE END ADC2_Init 1 */
/** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
*/
hadc2.Instance = ADC2;
8000506: 4b2f ldr r3, [pc, #188] @ (80005c4 <MX_ADC2_Init+0xd0>)
8000508: 4a2f ldr r2, [pc, #188] @ (80005c8 <MX_ADC2_Init+0xd4>)
800050a: 601a str r2, [r3, #0]
hadc2.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
800050c: 4b2d ldr r3, [pc, #180] @ (80005c4 <MX_ADC2_Init+0xd0>)
800050e: f44f 3280 mov.w r2, #65536 @ 0x10000
8000512: 605a str r2, [r3, #4]
hadc2.Init.Resolution = ADC_RESOLUTION_12B;
8000514: 4b2b ldr r3, [pc, #172] @ (80005c4 <MX_ADC2_Init+0xd0>)
8000516: 2200 movs r2, #0
8000518: 609a str r2, [r3, #8]
hadc2.Init.ScanConvMode = ENABLE;
800051a: 4b2a ldr r3, [pc, #168] @ (80005c4 <MX_ADC2_Init+0xd0>)
800051c: 2201 movs r2, #1
800051e: 611a str r2, [r3, #16]
hadc2.Init.ContinuousConvMode = DISABLE;
8000520: 4b28 ldr r3, [pc, #160] @ (80005c4 <MX_ADC2_Init+0xd0>)
8000522: 2200 movs r2, #0
8000524: 761a strb r2, [r3, #24]
hadc2.Init.DiscontinuousConvMode = DISABLE;
8000526: 4b27 ldr r3, [pc, #156] @ (80005c4 <MX_ADC2_Init+0xd0>)
8000528: 2200 movs r2, #0
800052a: f883 2020 strb.w r2, [r3, #32]
hadc2.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
800052e: 4b25 ldr r3, [pc, #148] @ (80005c4 <MX_ADC2_Init+0xd0>)
8000530: 2200 movs r2, #0
8000532: 62da str r2, [r3, #44] @ 0x2c
hadc2.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8000534: 4b23 ldr r3, [pc, #140] @ (80005c4 <MX_ADC2_Init+0xd0>)
8000536: 4a25 ldr r2, [pc, #148] @ (80005cc <MX_ADC2_Init+0xd8>)
8000538: 629a str r2, [r3, #40] @ 0x28
hadc2.Init.DataAlign = ADC_DATAALIGN_RIGHT;
800053a: 4b22 ldr r3, [pc, #136] @ (80005c4 <MX_ADC2_Init+0xd0>)
800053c: 2200 movs r2, #0
800053e: 60da str r2, [r3, #12]
hadc2.Init.NbrOfConversion = 3;
8000540: 4b20 ldr r3, [pc, #128] @ (80005c4 <MX_ADC2_Init+0xd0>)
8000542: 2203 movs r2, #3
8000544: 61da str r2, [r3, #28]
hadc2.Init.DMAContinuousRequests = DISABLE;
8000546: 4b1f ldr r3, [pc, #124] @ (80005c4 <MX_ADC2_Init+0xd0>)
8000548: 2200 movs r2, #0
800054a: f883 2030 strb.w r2, [r3, #48] @ 0x30
hadc2.Init.EOCSelection = ADC_EOC_SEQ_CONV;
800054e: 4b1d ldr r3, [pc, #116] @ (80005c4 <MX_ADC2_Init+0xd0>)
8000550: 2200 movs r2, #0
8000552: 615a str r2, [r3, #20]
if (HAL_ADC_Init(&hadc2) != HAL_OK)
8000554: 481b ldr r0, [pc, #108] @ (80005c4 <MX_ADC2_Init+0xd0>)
8000556: f001 fba9 bl 8001cac <HAL_ADC_Init>
800055a: 4603 mov r3, r0
800055c: 2b00 cmp r3, #0
800055e: d001 beq.n 8000564 <MX_ADC2_Init+0x70>
{
Error_Handler();
8000560: f000 ff05 bl 800136e <Error_Handler>
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_15;
8000564: 230f movs r3, #15
8000566: 603b str r3, [r7, #0]
sConfig.Rank = 1;
8000568: 2301 movs r3, #1
800056a: 607b str r3, [r7, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_3CYCLES;
800056c: 2300 movs r3, #0
800056e: 60bb str r3, [r7, #8]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
8000570: 463b mov r3, r7
8000572: 4619 mov r1, r3
8000574: 4813 ldr r0, [pc, #76] @ (80005c4 <MX_ADC2_Init+0xd0>)
8000576: f001 fd0b bl 8001f90 <HAL_ADC_ConfigChannel>
800057a: 4603 mov r3, r0
800057c: 2b00 cmp r3, #0
800057e: d001 beq.n 8000584 <MX_ADC2_Init+0x90>
{
Error_Handler();
8000580: f000 fef5 bl 800136e <Error_Handler>
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_8;
8000584: 2308 movs r3, #8
8000586: 603b str r3, [r7, #0]
sConfig.Rank = 2;
8000588: 2302 movs r3, #2
800058a: 607b str r3, [r7, #4]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
800058c: 463b mov r3, r7
800058e: 4619 mov r1, r3
8000590: 480c ldr r0, [pc, #48] @ (80005c4 <MX_ADC2_Init+0xd0>)
8000592: f001 fcfd bl 8001f90 <HAL_ADC_ConfigChannel>
8000596: 4603 mov r3, r0
8000598: 2b00 cmp r3, #0
800059a: d001 beq.n 80005a0 <MX_ADC2_Init+0xac>
{
Error_Handler();
800059c: f000 fee7 bl 800136e <Error_Handler>
}
/** Configure for the selected ADC regular channel its corresponding rank in the sequencer and its sample time.
*/
sConfig.Channel = ADC_CHANNEL_9;
80005a0: 2309 movs r3, #9
80005a2: 603b str r3, [r7, #0]
sConfig.Rank = 3;
80005a4: 2303 movs r3, #3
80005a6: 607b str r3, [r7, #4]
if (HAL_ADC_ConfigChannel(&hadc2, &sConfig) != HAL_OK)
80005a8: 463b mov r3, r7
80005aa: 4619 mov r1, r3
80005ac: 4805 ldr r0, [pc, #20] @ (80005c4 <MX_ADC2_Init+0xd0>)
80005ae: f001 fcef bl 8001f90 <HAL_ADC_ConfigChannel>
80005b2: 4603 mov r3, r0
80005b4: 2b00 cmp r3, #0
80005b6: d001 beq.n 80005bc <MX_ADC2_Init+0xc8>
{
Error_Handler();
80005b8: f000 fed9 bl 800136e <Error_Handler>
}
/* USER CODE BEGIN ADC2_Init 2 */
/* USER CODE END ADC2_Init 2 */
}
80005bc: bf00 nop
80005be: 3710 adds r7, #16
80005c0: 46bd mov sp, r7
80005c2: bd80 pop {r7, pc}
80005c4: 20000030 .word 0x20000030
80005c8: 40012100 .word 0x40012100
80005cc: 0f000001 .word 0x0f000001
080005d0 <HAL_ADC_MspInit>:
void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle)
{
80005d0: b580 push {r7, lr}
80005d2: b08a sub sp, #40 @ 0x28
80005d4: af00 add r7, sp, #0
80005d6: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80005d8: f107 0314 add.w r3, r7, #20
80005dc: 2200 movs r2, #0
80005de: 601a str r2, [r3, #0]
80005e0: 605a str r2, [r3, #4]
80005e2: 609a str r2, [r3, #8]
80005e4: 60da str r2, [r3, #12]
80005e6: 611a str r2, [r3, #16]
if(adcHandle->Instance==ADC2)
80005e8: 687b ldr r3, [r7, #4]
80005ea: 681b ldr r3, [r3, #0]
80005ec: 4a24 ldr r2, [pc, #144] @ (8000680 <HAL_ADC_MspInit+0xb0>)
80005ee: 4293 cmp r3, r2
80005f0: d141 bne.n 8000676 <HAL_ADC_MspInit+0xa6>
{
/* USER CODE BEGIN ADC2_MspInit 0 */
/* USER CODE END ADC2_MspInit 0 */
/* ADC2 clock enable */
__HAL_RCC_ADC2_CLK_ENABLE();
80005f2: 2300 movs r3, #0
80005f4: 613b str r3, [r7, #16]
80005f6: 4b23 ldr r3, [pc, #140] @ (8000684 <HAL_ADC_MspInit+0xb4>)
80005f8: 6c5b ldr r3, [r3, #68] @ 0x44
80005fa: 4a22 ldr r2, [pc, #136] @ (8000684 <HAL_ADC_MspInit+0xb4>)
80005fc: f443 7300 orr.w r3, r3, #512 @ 0x200
8000600: 6453 str r3, [r2, #68] @ 0x44
8000602: 4b20 ldr r3, [pc, #128] @ (8000684 <HAL_ADC_MspInit+0xb4>)
8000604: 6c5b ldr r3, [r3, #68] @ 0x44
8000606: f403 7300 and.w r3, r3, #512 @ 0x200
800060a: 613b str r3, [r7, #16]
800060c: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOC_CLK_ENABLE();
800060e: 2300 movs r3, #0
8000610: 60fb str r3, [r7, #12]
8000612: 4b1c ldr r3, [pc, #112] @ (8000684 <HAL_ADC_MspInit+0xb4>)
8000614: 6b1b ldr r3, [r3, #48] @ 0x30
8000616: 4a1b ldr r2, [pc, #108] @ (8000684 <HAL_ADC_MspInit+0xb4>)
8000618: f043 0304 orr.w r3, r3, #4
800061c: 6313 str r3, [r2, #48] @ 0x30
800061e: 4b19 ldr r3, [pc, #100] @ (8000684 <HAL_ADC_MspInit+0xb4>)
8000620: 6b1b ldr r3, [r3, #48] @ 0x30
8000622: f003 0304 and.w r3, r3, #4
8000626: 60fb str r3, [r7, #12]
8000628: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
800062a: 2300 movs r3, #0
800062c: 60bb str r3, [r7, #8]
800062e: 4b15 ldr r3, [pc, #84] @ (8000684 <HAL_ADC_MspInit+0xb4>)
8000630: 6b1b ldr r3, [r3, #48] @ 0x30
8000632: 4a14 ldr r2, [pc, #80] @ (8000684 <HAL_ADC_MspInit+0xb4>)
8000634: f043 0302 orr.w r3, r3, #2
8000638: 6313 str r3, [r2, #48] @ 0x30
800063a: 4b12 ldr r3, [pc, #72] @ (8000684 <HAL_ADC_MspInit+0xb4>)
800063c: 6b1b ldr r3, [r3, #48] @ 0x30
800063e: f003 0302 and.w r3, r3, #2
8000642: 60bb str r3, [r7, #8]
8000644: 68bb ldr r3, [r7, #8]
/**ADC2 GPIO Configuration
PC5 ------> ADC2_IN15
PB0 ------> ADC2_IN8
PB1 ------> ADC2_IN9
*/
GPIO_InitStruct.Pin = SENSE3_Pin;
8000646: 2320 movs r3, #32
8000648: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
800064a: 2303 movs r3, #3
800064c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800064e: 2300 movs r3, #0
8000650: 61fb str r3, [r7, #28]
HAL_GPIO_Init(SENSE3_GPIO_Port, &GPIO_InitStruct);
8000652: f107 0314 add.w r3, r7, #20
8000656: 4619 mov r1, r3
8000658: 480b ldr r0, [pc, #44] @ (8000688 <HAL_ADC_MspInit+0xb8>)
800065a: f002 fda1 bl 80031a0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = SENSE2_Pin|SENSE1_Pin;
800065e: 2303 movs r3, #3
8000660: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8000662: 2303 movs r3, #3
8000664: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000666: 2300 movs r3, #0
8000668: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
800066a: f107 0314 add.w r3, r7, #20
800066e: 4619 mov r1, r3
8000670: 4806 ldr r0, [pc, #24] @ (800068c <HAL_ADC_MspInit+0xbc>)
8000672: f002 fd95 bl 80031a0 <HAL_GPIO_Init>
/* USER CODE BEGIN ADC2_MspInit 1 */
/* USER CODE END ADC2_MspInit 1 */
}
}
8000676: bf00 nop
8000678: 3728 adds r7, #40 @ 0x28
800067a: 46bd mov sp, r7
800067c: bd80 pop {r7, pc}
800067e: bf00 nop
8000680: 40012100 .word 0x40012100
8000684: 40023800 .word 0x40023800
8000688: 40020800 .word 0x40020800
800068c: 40020400 .word 0x40020400
08000690 <MX_CAN2_Init>:
CAN_HandleTypeDef hcan2;
/* CAN2 init function */
void MX_CAN2_Init(void)
{
8000690: b580 push {r7, lr}
8000692: af00 add r7, sp, #0
/* USER CODE END CAN2_Init 0 */
/* USER CODE BEGIN CAN2_Init 1 */
/* USER CODE END CAN2_Init 1 */
hcan2.Instance = CAN2;
8000694: 4b17 ldr r3, [pc, #92] @ (80006f4 <MX_CAN2_Init+0x64>)
8000696: 4a18 ldr r2, [pc, #96] @ (80006f8 <MX_CAN2_Init+0x68>)
8000698: 601a str r2, [r3, #0]
hcan2.Init.Prescaler = 3;
800069a: 4b16 ldr r3, [pc, #88] @ (80006f4 <MX_CAN2_Init+0x64>)
800069c: 2203 movs r2, #3
800069e: 605a str r2, [r3, #4]
hcan2.Init.Mode = CAN_MODE_NORMAL;
80006a0: 4b14 ldr r3, [pc, #80] @ (80006f4 <MX_CAN2_Init+0x64>)
80006a2: 2200 movs r2, #0
80006a4: 609a str r2, [r3, #8]
hcan2.Init.SyncJumpWidth = CAN_SJW_1TQ;
80006a6: 4b13 ldr r3, [pc, #76] @ (80006f4 <MX_CAN2_Init+0x64>)
80006a8: 2200 movs r2, #0
80006aa: 60da str r2, [r3, #12]
hcan2.Init.TimeSeg1 = CAN_BS1_12TQ;
80006ac: 4b11 ldr r3, [pc, #68] @ (80006f4 <MX_CAN2_Init+0x64>)
80006ae: f44f 2230 mov.w r2, #720896 @ 0xb0000
80006b2: 611a str r2, [r3, #16]
hcan2.Init.TimeSeg2 = CAN_BS2_2TQ;
80006b4: 4b0f ldr r3, [pc, #60] @ (80006f4 <MX_CAN2_Init+0x64>)
80006b6: f44f 1280 mov.w r2, #1048576 @ 0x100000
80006ba: 615a str r2, [r3, #20]
hcan2.Init.TimeTriggeredMode = DISABLE;
80006bc: 4b0d ldr r3, [pc, #52] @ (80006f4 <MX_CAN2_Init+0x64>)
80006be: 2200 movs r2, #0
80006c0: 761a strb r2, [r3, #24]
hcan2.Init.AutoBusOff = DISABLE;
80006c2: 4b0c ldr r3, [pc, #48] @ (80006f4 <MX_CAN2_Init+0x64>)
80006c4: 2200 movs r2, #0
80006c6: 765a strb r2, [r3, #25]
hcan2.Init.AutoWakeUp = DISABLE;
80006c8: 4b0a ldr r3, [pc, #40] @ (80006f4 <MX_CAN2_Init+0x64>)
80006ca: 2200 movs r2, #0
80006cc: 769a strb r2, [r3, #26]
hcan2.Init.AutoRetransmission = DISABLE;
80006ce: 4b09 ldr r3, [pc, #36] @ (80006f4 <MX_CAN2_Init+0x64>)
80006d0: 2200 movs r2, #0
80006d2: 76da strb r2, [r3, #27]
hcan2.Init.ReceiveFifoLocked = DISABLE;
80006d4: 4b07 ldr r3, [pc, #28] @ (80006f4 <MX_CAN2_Init+0x64>)
80006d6: 2200 movs r2, #0
80006d8: 771a strb r2, [r3, #28]
hcan2.Init.TransmitFifoPriority = DISABLE;
80006da: 4b06 ldr r3, [pc, #24] @ (80006f4 <MX_CAN2_Init+0x64>)
80006dc: 2200 movs r2, #0
80006de: 775a strb r2, [r3, #29]
if (HAL_CAN_Init(&hcan2) != HAL_OK)
80006e0: 4804 ldr r0, [pc, #16] @ (80006f4 <MX_CAN2_Init+0x64>)
80006e2: f001 fe8d bl 8002400 <HAL_CAN_Init>
80006e6: 4603 mov r3, r0
80006e8: 2b00 cmp r3, #0
80006ea: d001 beq.n 80006f0 <MX_CAN2_Init+0x60>
{
Error_Handler();
80006ec: f000 fe3f bl 800136e <Error_Handler>
}
/* USER CODE BEGIN CAN2_Init 2 */
/* USER CODE END CAN2_Init 2 */
}
80006f0: bf00 nop
80006f2: bd80 pop {r7, pc}
80006f4: 20000078 .word 0x20000078
80006f8: 40006800 .word 0x40006800
080006fc <HAL_CAN_MspInit>:
void HAL_CAN_MspInit(CAN_HandleTypeDef* canHandle)
{
80006fc: b580 push {r7, lr}
80006fe: b08a sub sp, #40 @ 0x28
8000700: af00 add r7, sp, #0
8000702: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000704: f107 0314 add.w r3, r7, #20
8000708: 2200 movs r2, #0
800070a: 601a str r2, [r3, #0]
800070c: 605a str r2, [r3, #4]
800070e: 609a str r2, [r3, #8]
8000710: 60da str r2, [r3, #12]
8000712: 611a str r2, [r3, #16]
if(canHandle->Instance==CAN2)
8000714: 687b ldr r3, [r7, #4]
8000716: 681b ldr r3, [r3, #0]
8000718: 4a20 ldr r2, [pc, #128] @ (800079c <HAL_CAN_MspInit+0xa0>)
800071a: 4293 cmp r3, r2
800071c: d13a bne.n 8000794 <HAL_CAN_MspInit+0x98>
{
/* USER CODE BEGIN CAN2_MspInit 0 */
/* USER CODE END CAN2_MspInit 0 */
/* CAN2 clock enable */
__HAL_RCC_CAN2_CLK_ENABLE();
800071e: 2300 movs r3, #0
8000720: 613b str r3, [r7, #16]
8000722: 4b1f ldr r3, [pc, #124] @ (80007a0 <HAL_CAN_MspInit+0xa4>)
8000724: 6c1b ldr r3, [r3, #64] @ 0x40
8000726: 4a1e ldr r2, [pc, #120] @ (80007a0 <HAL_CAN_MspInit+0xa4>)
8000728: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
800072c: 6413 str r3, [r2, #64] @ 0x40
800072e: 4b1c ldr r3, [pc, #112] @ (80007a0 <HAL_CAN_MspInit+0xa4>)
8000730: 6c1b ldr r3, [r3, #64] @ 0x40
8000732: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
8000736: 613b str r3, [r7, #16]
8000738: 693b ldr r3, [r7, #16]
__HAL_RCC_CAN1_CLK_ENABLE();
800073a: 2300 movs r3, #0
800073c: 60fb str r3, [r7, #12]
800073e: 4b18 ldr r3, [pc, #96] @ (80007a0 <HAL_CAN_MspInit+0xa4>)
8000740: 6c1b ldr r3, [r3, #64] @ 0x40
8000742: 4a17 ldr r2, [pc, #92] @ (80007a0 <HAL_CAN_MspInit+0xa4>)
8000744: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
8000748: 6413 str r3, [r2, #64] @ 0x40
800074a: 4b15 ldr r3, [pc, #84] @ (80007a0 <HAL_CAN_MspInit+0xa4>)
800074c: 6c1b ldr r3, [r3, #64] @ 0x40
800074e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8000752: 60fb str r3, [r7, #12]
8000754: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000756: 2300 movs r3, #0
8000758: 60bb str r3, [r7, #8]
800075a: 4b11 ldr r3, [pc, #68] @ (80007a0 <HAL_CAN_MspInit+0xa4>)
800075c: 6b1b ldr r3, [r3, #48] @ 0x30
800075e: 4a10 ldr r2, [pc, #64] @ (80007a0 <HAL_CAN_MspInit+0xa4>)
8000760: f043 0302 orr.w r3, r3, #2
8000764: 6313 str r3, [r2, #48] @ 0x30
8000766: 4b0e ldr r3, [pc, #56] @ (80007a0 <HAL_CAN_MspInit+0xa4>)
8000768: 6b1b ldr r3, [r3, #48] @ 0x30
800076a: f003 0302 and.w r3, r3, #2
800076e: 60bb str r3, [r7, #8]
8000770: 68bb ldr r3, [r7, #8]
/**CAN2 GPIO Configuration
PB12 ------> CAN2_RX
PB13 ------> CAN2_TX
*/
GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13;
8000772: f44f 5340 mov.w r3, #12288 @ 0x3000
8000776: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8000778: 2302 movs r3, #2
800077a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800077c: 2300 movs r3, #0
800077e: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000780: 2303 movs r3, #3
8000782: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF9_CAN2;
8000784: 2309 movs r3, #9
8000786: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8000788: f107 0314 add.w r3, r7, #20
800078c: 4619 mov r1, r3
800078e: 4805 ldr r0, [pc, #20] @ (80007a4 <HAL_CAN_MspInit+0xa8>)
8000790: f002 fd06 bl 80031a0 <HAL_GPIO_Init>
/* USER CODE BEGIN CAN2_MspInit 1 */
/* USER CODE END CAN2_MspInit 1 */
}
}
8000794: bf00 nop
8000796: 3728 adds r7, #40 @ 0x28
8000798: 46bd mov sp, r7
800079a: bd80 pop {r7, pc}
800079c: 40006800 .word 0x40006800
80007a0: 40023800 .word 0x40023800
80007a4: 40020400 .word 0x40020400
080007a8 <flash_unlock>:
}conv_float_to_int;
static uint32_t write_ptr = SECTOR_6;
static uint32_t ptr_fl = APP_ADDRESS;
void flash_unlock(){
80007a8: b480 push {r7}
80007aa: af00 add r7, sp, #0
// Check if flash is locked
if(!(FLASH->CR & FLASH_CR_LOCK)) {
80007ac: 4b07 ldr r3, [pc, #28] @ (80007cc <flash_unlock+0x24>)
80007ae: 691b ldr r3, [r3, #16]
80007b0: 2b00 cmp r3, #0
80007b2: da06 bge.n 80007c2 <flash_unlock+0x1a>
return; // Already unlocked
}
// Write flash key sequence to unlock
FLASH->KEYR = 0x45670123; // First key
80007b4: 4b05 ldr r3, [pc, #20] @ (80007cc <flash_unlock+0x24>)
80007b6: 4a06 ldr r2, [pc, #24] @ (80007d0 <flash_unlock+0x28>)
80007b8: 605a str r2, [r3, #4]
FLASH->KEYR = 0xCDEF89AB; // Second key
80007ba: 4b04 ldr r3, [pc, #16] @ (80007cc <flash_unlock+0x24>)
80007bc: 4a05 ldr r2, [pc, #20] @ (80007d4 <flash_unlock+0x2c>)
80007be: 605a str r2, [r3, #4]
80007c0: e000 b.n 80007c4 <flash_unlock+0x1c>
return; // Already unlocked
80007c2: bf00 nop
}
80007c4: 46bd mov sp, r7
80007c6: f85d 7b04 ldr.w r7, [sp], #4
80007ca: 4770 bx lr
80007cc: 40023c00 .word 0x40023c00
80007d0: 45670123 .word 0x45670123
80007d4: cdef89ab .word 0xcdef89ab
080007d8 <flash_lock>:
void flash_lock() {
80007d8: b480 push {r7}
80007da: af00 add r7, sp, #0
if(FLASH->CR & FLASH_CR_LOCK) {
80007dc: 4b07 ldr r3, [pc, #28] @ (80007fc <flash_lock+0x24>)
80007de: 691b ldr r3, [r3, #16]
80007e0: 2b00 cmp r3, #0
80007e2: db06 blt.n 80007f2 <flash_lock+0x1a>
return; // Already locked
}
FLASH->CR |= FLASH_CR_LOCK; // Lock flash memory
80007e4: 4b05 ldr r3, [pc, #20] @ (80007fc <flash_lock+0x24>)
80007e6: 691b ldr r3, [r3, #16]
80007e8: 4a04 ldr r2, [pc, #16] @ (80007fc <flash_lock+0x24>)
80007ea: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
80007ee: 6113 str r3, [r2, #16]
80007f0: e000 b.n 80007f4 <flash_lock+0x1c>
return; // Already locked
80007f2: bf00 nop
}
80007f4: 46bd mov sp, r7
80007f6: f85d 7b04 ldr.w r7, [sp], #4
80007fa: 4770 bx lr
80007fc: 40023c00 .word 0x40023c00
08000800 <erase_sector>:
void erase_sector(uint8_t sector){
8000800: b580 push {r7, lr}
8000802: b082 sub sp, #8
8000804: af00 add r7, sp, #0
8000806: 4603 mov r3, r0
8000808: 71fb strb r3, [r7, #7]
// Wait if flash is busy
while(FLASH_BUSY);
800080a: bf00 nop
800080c: 4b1b ldr r3, [pc, #108] @ (800087c <erase_sector+0x7c>)
800080e: 68db ldr r3, [r3, #12]
8000810: f403 3380 and.w r3, r3, #65536 @ 0x10000
8000814: 2b00 cmp r3, #0
8000816: d1f9 bne.n 800080c <erase_sector+0xc>
// Check if flash is locked and unlock if needed
if(FLASH->CR & FLASH_CR_LOCK) {
8000818: 4b18 ldr r3, [pc, #96] @ (800087c <erase_sector+0x7c>)
800081a: 691b ldr r3, [r3, #16]
800081c: 2b00 cmp r3, #0
800081e: da01 bge.n 8000824 <erase_sector+0x24>
flash_unlock();
8000820: f7ff ffc2 bl 80007a8 <flash_unlock>
}
// Set sector erase bit and sector number
FLASH->CR |= FLASH_CR_SER;
8000824: 4b15 ldr r3, [pc, #84] @ (800087c <erase_sector+0x7c>)
8000826: 691b ldr r3, [r3, #16]
8000828: 4a14 ldr r2, [pc, #80] @ (800087c <erase_sector+0x7c>)
800082a: f043 0302 orr.w r3, r3, #2
800082e: 6113 str r3, [r2, #16]
FLASH->CR &= ~FLASH_CR_SNB;
8000830: 4b12 ldr r3, [pc, #72] @ (800087c <erase_sector+0x7c>)
8000832: 691b ldr r3, [r3, #16]
8000834: 4a11 ldr r2, [pc, #68] @ (800087c <erase_sector+0x7c>)
8000836: f023 03f8 bic.w r3, r3, #248 @ 0xf8
800083a: 6113 str r3, [r2, #16]
FLASH->CR |= (sector << FLASH_CR_SNB_Pos) & FLASH_CR_SNB_Msk;
800083c: 4b0f ldr r3, [pc, #60] @ (800087c <erase_sector+0x7c>)
800083e: 691a ldr r2, [r3, #16]
8000840: 79fb ldrb r3, [r7, #7]
8000842: 00db lsls r3, r3, #3
8000844: b2db uxtb r3, r3
8000846: 490d ldr r1, [pc, #52] @ (800087c <erase_sector+0x7c>)
8000848: 4313 orrs r3, r2
800084a: 610b str r3, [r1, #16]
// Start erase
FLASH->CR |= FLASH_CR_STRT;
800084c: 4b0b ldr r3, [pc, #44] @ (800087c <erase_sector+0x7c>)
800084e: 691b ldr r3, [r3, #16]
8000850: 4a0a ldr r2, [pc, #40] @ (800087c <erase_sector+0x7c>)
8000852: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8000856: 6113 str r3, [r2, #16]
// Wait for erase to complete
while(FLASH_BUSY);
8000858: bf00 nop
800085a: 4b08 ldr r3, [pc, #32] @ (800087c <erase_sector+0x7c>)
800085c: 68db ldr r3, [r3, #12]
800085e: f403 3380 and.w r3, r3, #65536 @ 0x10000
8000862: 2b00 cmp r3, #0
8000864: d1f9 bne.n 800085a <erase_sector+0x5a>
// Clear sector erase bit
FLASH->CR &= ~FLASH_CR_SER;
8000866: 4b05 ldr r3, [pc, #20] @ (800087c <erase_sector+0x7c>)
8000868: 691b ldr r3, [r3, #16]
800086a: 4a04 ldr r2, [pc, #16] @ (800087c <erase_sector+0x7c>)
800086c: f023 0302 bic.w r3, r3, #2
8000870: 6113 str r3, [r2, #16]
}
8000872: bf00 nop
8000874: 3708 adds r7, #8
8000876: 46bd mov sp, r7
8000878: bd80 pop {r7, pc}
800087a: bf00 nop
800087c: 40023c00 .word 0x40023c00
08000880 <flash_write>:
// Clear program bit
FLASH->CR &= ~FLASH_CR_PG;
}
void flash_write(uint32_t addr, FLASH_RECORD* record){
8000880: b580 push {r7, lr}
8000882: b086 sub sp, #24
8000884: af00 add r7, sp, #0
8000886: 6078 str r0, [r7, #4]
8000888: 6039 str r1, [r7, #0]
uint32_t* data = (uint32_t*)record;
800088a: 683b ldr r3, [r7, #0]
800088c: 613b str r3, [r7, #16]
uint32_t size = FLASH_RECORD_SIZE / 4; //count words in struct
800088e: 2302 movs r3, #2
8000890: 60fb str r3, [r7, #12]
// Wait if flash is busy
while(FLASH_BUSY);
8000892: bf00 nop
8000894: 4b20 ldr r3, [pc, #128] @ (8000918 <flash_write+0x98>)
8000896: 68db ldr r3, [r3, #12]
8000898: f403 3380 and.w r3, r3, #65536 @ 0x10000
800089c: 2b00 cmp r3, #0
800089e: d1f9 bne.n 8000894 <flash_write+0x14>
// Check if flash is locked and unlock if needed
if(FLASH->CR & FLASH_CR_LOCK) {
80008a0: 4b1d ldr r3, [pc, #116] @ (8000918 <flash_write+0x98>)
80008a2: 691b ldr r3, [r3, #16]
80008a4: 2b00 cmp r3, #0
80008a6: da01 bge.n 80008ac <flash_write+0x2c>
flash_unlock();
80008a8: f7ff ff7e bl 80007a8 <flash_unlock>
}
// Set program bit and write data to flash
FLASH_32BYTE;
80008ac: 4b1a ldr r3, [pc, #104] @ (8000918 <flash_write+0x98>)
80008ae: 691b ldr r3, [r3, #16]
80008b0: f423 7340 bic.w r3, r3, #768 @ 0x300
80008b4: 4a18 ldr r2, [pc, #96] @ (8000918 <flash_write+0x98>)
80008b6: f443 7300 orr.w r3, r3, #512 @ 0x200
80008ba: 6113 str r3, [r2, #16]
FLASH->CR |= FLASH_CR_PG;
80008bc: 4b16 ldr r3, [pc, #88] @ (8000918 <flash_write+0x98>)
80008be: 691b ldr r3, [r3, #16]
80008c0: 4a15 ldr r2, [pc, #84] @ (8000918 <flash_write+0x98>)
80008c2: f043 0301 orr.w r3, r3, #1
80008c6: 6113 str r3, [r2, #16]
for(int i = 0;i < size;i++){
80008c8: 2300 movs r3, #0
80008ca: 617b str r3, [r7, #20]
80008cc: e00d b.n 80008ea <flash_write+0x6a>
*(volatile uint32_t*)(addr + (i * 4)) = data[i];
80008ce: 697b ldr r3, [r7, #20]
80008d0: 009b lsls r3, r3, #2
80008d2: 693a ldr r2, [r7, #16]
80008d4: 4413 add r3, r2
80008d6: 697a ldr r2, [r7, #20]
80008d8: 0092 lsls r2, r2, #2
80008da: 4611 mov r1, r2
80008dc: 687a ldr r2, [r7, #4]
80008de: 440a add r2, r1
80008e0: 681b ldr r3, [r3, #0]
80008e2: 6013 str r3, [r2, #0]
for(int i = 0;i < size;i++){
80008e4: 697b ldr r3, [r7, #20]
80008e6: 3301 adds r3, #1
80008e8: 617b str r3, [r7, #20]
80008ea: 697b ldr r3, [r7, #20]
80008ec: 68fa ldr r2, [r7, #12]
80008ee: 429a cmp r2, r3
80008f0: d8ed bhi.n 80008ce <flash_write+0x4e>
}
// Clear program bit
FLASH->CR &= ~FLASH_CR_PG;
80008f2: 4b09 ldr r3, [pc, #36] @ (8000918 <flash_write+0x98>)
80008f4: 691b ldr r3, [r3, #16]
80008f6: 4a08 ldr r2, [pc, #32] @ (8000918 <flash_write+0x98>)
80008f8: f023 0301 bic.w r3, r3, #1
80008fc: 6113 str r3, [r2, #16]
write_ptr = addr + (size * 4); //increase variable storing addr
80008fe: 68fb ldr r3, [r7, #12]
8000900: 009a lsls r2, r3, #2
8000902: 687b ldr r3, [r7, #4]
8000904: 4413 add r3, r2
8000906: 4a05 ldr r2, [pc, #20] @ (800091c <flash_write+0x9c>)
8000908: 6013 str r3, [r2, #0]
flash_lock();
800090a: f7ff ff65 bl 80007d8 <flash_lock>
}
800090e: bf00 nop
8000910: 3718 adds r7, #24
8000912: 46bd mov sp, r7
8000914: bd80 pop {r7, pc}
8000916: bf00 nop
8000918: 40023c00 .word 0x40023c00
800091c: 20000000 .word 0x20000000
08000920 <validate_crc16>:
// Wait if flash
// bool validata_crc(FLASH_RECORD* crc){
// return crc->crc == 0x6933? true : false;
// }
uint16_t validate_crc16(uint8_t *data, uint32_t length) {
8000920: b480 push {r7}
8000922: b085 sub sp, #20
8000924: af00 add r7, sp, #0
8000926: 6078 str r0, [r7, #4]
8000928: 6039 str r1, [r7, #0]
uint16_t crc = 0xFFFF; // start value for CRC MODBUS
800092a: f64f 73ff movw r3, #65535 @ 0xffff
800092e: 81fb strh r3, [r7, #14]
while (length--) {
8000930: e01f b.n 8000972 <validate_crc16+0x52>
crc ^= *data++; // XOR
8000932: 687b ldr r3, [r7, #4]
8000934: 1c5a adds r2, r3, #1
8000936: 607a str r2, [r7, #4]
8000938: 781b ldrb r3, [r3, #0]
800093a: 461a mov r2, r3
800093c: 89fb ldrh r3, [r7, #14]
800093e: 4053 eors r3, r2
8000940: 81fb strh r3, [r7, #14]
for (uint8_t i = 0; i < 8; i++) {
8000942: 2300 movs r3, #0
8000944: 737b strb r3, [r7, #13]
8000946: e011 b.n 800096c <validate_crc16+0x4c>
if (crc & 0x0001) {
8000948: 89fb ldrh r3, [r7, #14]
800094a: f003 0301 and.w r3, r3, #1
800094e: 2b00 cmp r3, #0
8000950: d006 beq.n 8000960 <validate_crc16+0x40>
crc = (crc >> 1) ^ 0xA001; // polynome 0x8005 (reverse)
8000952: 89fb ldrh r3, [r7, #14]
8000954: 085b lsrs r3, r3, #1
8000956: b29a uxth r2, r3
8000958: 4b0c ldr r3, [pc, #48] @ (800098c <validate_crc16+0x6c>)
800095a: 4053 eors r3, r2
800095c: 81fb strh r3, [r7, #14]
800095e: e002 b.n 8000966 <validate_crc16+0x46>
} else {
crc >>= 1;
8000960: 89fb ldrh r3, [r7, #14]
8000962: 085b lsrs r3, r3, #1
8000964: 81fb strh r3, [r7, #14]
for (uint8_t i = 0; i < 8; i++) {
8000966: 7b7b ldrb r3, [r7, #13]
8000968: 3301 adds r3, #1
800096a: 737b strb r3, [r7, #13]
800096c: 7b7b ldrb r3, [r7, #13]
800096e: 2b07 cmp r3, #7
8000970: d9ea bls.n 8000948 <validate_crc16+0x28>
while (length--) {
8000972: 683b ldr r3, [r7, #0]
8000974: 1e5a subs r2, r3, #1
8000976: 603a str r2, [r7, #0]
8000978: 2b00 cmp r3, #0
800097a: d1da bne.n 8000932 <validate_crc16+0x12>
}
}
}
return crc;
800097c: 89fb ldrh r3, [r7, #14]
}
800097e: 4618 mov r0, r3
8000980: 3714 adds r7, #20
8000982: 46bd mov sp, r7
8000984: f85d 7b04 ldr.w r7, [sp], #4
8000988: 4770 bx lr
800098a: bf00 nop
800098c: ffffa001 .word 0xffffa001
08000990 <calc_crc_struct>:
uint16_t calc_crc_struct(FLASH_RECORD* res){
8000990: b580 push {r7, lr}
8000992: b086 sub sp, #24
8000994: af00 add r7, sp, #0
8000996: 6078 str r0, [r7, #4]
uint8_t arr_res[FLASH_RECORD_SIZE - 2];
uint16_t crc_res;
/* sorting data without CRC */
arr_res[0] = res->data_id;
8000998: 687b ldr r3, [r7, #4]
800099a: 781b ldrb r3, [r3, #0]
800099c: 733b strb r3, [r7, #12]
arr_res[1] = res->data_type;
800099e: 687b ldr r3, [r7, #4]
80009a0: 785b ldrb r3, [r3, #1]
80009a2: 737b strb r3, [r7, #13]
/* from 32 to 8 bit */
for(int i = 0;i < 4;i++)
80009a4: 2300 movs r3, #0
80009a6: 617b str r3, [r7, #20]
80009a8: e00e b.n 80009c8 <calc_crc_struct+0x38>
arr_res[i + 2] = (uint8_t)(res->value >> i * 8);
80009aa: 687b ldr r3, [r7, #4]
80009ac: 685a ldr r2, [r3, #4]
80009ae: 697b ldr r3, [r7, #20]
80009b0: 00db lsls r3, r3, #3
80009b2: 40da lsrs r2, r3
80009b4: 697b ldr r3, [r7, #20]
80009b6: 3302 adds r3, #2
80009b8: b2d2 uxtb r2, r2
80009ba: 3318 adds r3, #24
80009bc: 443b add r3, r7
80009be: f803 2c0c strb.w r2, [r3, #-12]
for(int i = 0;i < 4;i++)
80009c2: 697b ldr r3, [r7, #20]
80009c4: 3301 adds r3, #1
80009c6: 617b str r3, [r7, #20]
80009c8: 697b ldr r3, [r7, #20]
80009ca: 2b03 cmp r3, #3
80009cc: dded ble.n 80009aa <calc_crc_struct+0x1a>
crc_res = validate_crc16(arr_res,FLASH_RECORD_SIZE - 2);
80009ce: f107 030c add.w r3, r7, #12
80009d2: 2106 movs r1, #6
80009d4: 4618 mov r0, r3
80009d6: f7ff ffa3 bl 8000920 <validate_crc16>
80009da: 4603 mov r3, r0
80009dc: 827b strh r3, [r7, #18]
return crc_res;
80009de: 8a7b ldrh r3, [r7, #18]
}
80009e0: 4618 mov r0, r3
80009e2: 3718 adds r7, #24
80009e4: 46bd mov sp, r7
80009e6: bd80 pop {r7, pc}
080009e8 <flash_read>:
/* read struct from FLASH */
void flash_read(uint32_t addr,FLASH_RECORD* ptr){
80009e8: b480 push {r7}
80009ea: b087 sub sp, #28
80009ec: af00 add r7, sp, #0
80009ee: 6078 str r0, [r7, #4]
80009f0: 6039 str r1, [r7, #0]
uint8_t* flash_ptr = (uint8_t*)addr;
80009f2: 687b ldr r3, [r7, #4]
80009f4: 613b str r3, [r7, #16]
uint8_t* dest = (uint8_t*)ptr;
80009f6: 683b ldr r3, [r7, #0]
80009f8: 60fb str r3, [r7, #12]
for(int i = 0;i < FLASH_RECORD_SIZE;i++)
80009fa: 2300 movs r3, #0
80009fc: 617b str r3, [r7, #20]
80009fe: e00a b.n 8000a16 <flash_read+0x2e>
dest[i] = flash_ptr[i];
8000a00: 697b ldr r3, [r7, #20]
8000a02: 693a ldr r2, [r7, #16]
8000a04: 441a add r2, r3
8000a06: 697b ldr r3, [r7, #20]
8000a08: 68f9 ldr r1, [r7, #12]
8000a0a: 440b add r3, r1
8000a0c: 7812 ldrb r2, [r2, #0]
8000a0e: 701a strb r2, [r3, #0]
for(int i = 0;i < FLASH_RECORD_SIZE;i++)
8000a10: 697b ldr r3, [r7, #20]
8000a12: 3301 adds r3, #1
8000a14: 617b str r3, [r7, #20]
8000a16: 697b ldr r3, [r7, #20]
8000a18: 2b07 cmp r3, #7
8000a1a: d9f1 bls.n 8000a00 <flash_read+0x18>
}
8000a1c: bf00 nop
8000a1e: bf00 nop
8000a20: 371c adds r7, #28
8000a22: 46bd mov sp, r7
8000a24: f85d 7b04 ldr.w r7, [sp], #4
8000a28: 4770 bx lr
...
08000a2c <compact_page>:
void compact_page(){
8000a2c: b580 push {r7, lr}
8000a2e: b090 sub sp, #64 @ 0x40
8000a30: af00 add r7, sp, #0
FLASH_RECORD latest[PARAM_COUNT] = {0};
8000a32: f107 030c add.w r3, r7, #12
8000a36: 2228 movs r2, #40 @ 0x28
8000a38: 2100 movs r1, #0
8000a3a: 4618 mov r0, r3
8000a3c: f004 ffbc bl 80059b8 <memset>
for(int i = (uint32_t)SECTOR_6;i < (uint32_t)SECTOR_6_END;i += FLASH_RECORD_SIZE) {
8000a40: 4b2c ldr r3, [pc, #176] @ (8000af4 <compact_page+0xc8>)
8000a42: 63fb str r3, [r7, #60] @ 0x3c
8000a44: e01f b.n 8000a86 <compact_page+0x5a>
FLASH_RECORD rec;
flash_read(i,&rec);
8000a46: 6bfb ldr r3, [r7, #60] @ 0x3c
8000a48: 1d3a adds r2, r7, #4
8000a4a: 4611 mov r1, r2
8000a4c: 4618 mov r0, r3
8000a4e: f7ff ffcb bl 80009e8 <flash_read>
uint16_t calculated_crc = calc_crc_struct(&rec);
8000a52: 1d3b adds r3, r7, #4
8000a54: 4618 mov r0, r3
8000a56: f7ff ff9b bl 8000990 <calc_crc_struct>
8000a5a: 4603 mov r3, r0
8000a5c: 86fb strh r3, [r7, #54] @ 0x36
if (calculated_crc == rec.crc && rec.data_id < PARAM_COUNT) {
8000a5e: 88fb ldrh r3, [r7, #6]
8000a60: 8efa ldrh r2, [r7, #54] @ 0x36
8000a62: 429a cmp r2, r3
8000a64: d10c bne.n 8000a80 <compact_page+0x54>
8000a66: 793b ldrb r3, [r7, #4]
8000a68: 2b04 cmp r3, #4
8000a6a: d809 bhi.n 8000a80 <compact_page+0x54>
// if the crc does not match, we check further
latest[rec.data_id] = rec;
8000a6c: 793b ldrb r3, [r7, #4]
8000a6e: 00db lsls r3, r3, #3
8000a70: 3340 adds r3, #64 @ 0x40
8000a72: 443b add r3, r7
8000a74: 3b34 subs r3, #52 @ 0x34
8000a76: 1d3a adds r2, r7, #4
8000a78: e892 0003 ldmia.w r2, {r0, r1}
8000a7c: e883 0003 stmia.w r3, {r0, r1}
for(int i = (uint32_t)SECTOR_6;i < (uint32_t)SECTOR_6_END;i += FLASH_RECORD_SIZE) {
8000a80: 6bfb ldr r3, [r7, #60] @ 0x3c
8000a82: 3308 adds r3, #8
8000a84: 63fb str r3, [r7, #60] @ 0x3c
8000a86: 6bfb ldr r3, [r7, #60] @ 0x3c
8000a88: 4a1b ldr r2, [pc, #108] @ (8000af8 <compact_page+0xcc>)
8000a8a: 4293 cmp r3, r2
8000a8c: d9db bls.n 8000a46 <compact_page+0x1a>
else
// if
continue;
}
erase_sector(6);
8000a8e: 2006 movs r0, #6
8000a90: f7ff feb6 bl 8000800 <erase_sector>
write_ptr = SECTOR_6; // Сброс на начало
8000a94: 4b19 ldr r3, [pc, #100] @ (8000afc <compact_page+0xd0>)
8000a96: 4a17 ldr r2, [pc, #92] @ (8000af4 <compact_page+0xc8>)
8000a98: 601a str r2, [r3, #0]
for (int i = 0; i < PARAM_COUNT; i++) {
8000a9a: 2300 movs r3, #0
8000a9c: 63bb str r3, [r7, #56] @ 0x38
8000a9e: e021 b.n 8000ae4 <compact_page+0xb8>
if (latest[i].data_id != 0xFF) {
8000aa0: 6bbb ldr r3, [r7, #56] @ 0x38
8000aa2: 00db lsls r3, r3, #3
8000aa4: 3340 adds r3, #64 @ 0x40
8000aa6: 443b add r3, r7
8000aa8: f813 3c34 ldrb.w r3, [r3, #-52]
8000aac: 2bff cmp r3, #255 @ 0xff
8000aae: d016 beq.n 8000ade <compact_page+0xb2>
// alignment
if (write_ptr % 4 != 0) {
8000ab0: 4b12 ldr r3, [pc, #72] @ (8000afc <compact_page+0xd0>)
8000ab2: 681b ldr r3, [r3, #0]
8000ab4: f003 0303 and.w r3, r3, #3
8000ab8: 2b00 cmp r3, #0
8000aba: d006 beq.n 8000aca <compact_page+0x9e>
write_ptr += (4 - (write_ptr % 4));
8000abc: 4b0f ldr r3, [pc, #60] @ (8000afc <compact_page+0xd0>)
8000abe: 681b ldr r3, [r3, #0]
8000ac0: f023 0303 bic.w r3, r3, #3
8000ac4: 3304 adds r3, #4
8000ac6: 4a0d ldr r2, [pc, #52] @ (8000afc <compact_page+0xd0>)
8000ac8: 6013 str r3, [r2, #0]
}
flash_write(write_ptr, &latest[i]);
8000aca: 4b0c ldr r3, [pc, #48] @ (8000afc <compact_page+0xd0>)
8000acc: 6818 ldr r0, [r3, #0]
8000ace: f107 020c add.w r2, r7, #12
8000ad2: 6bbb ldr r3, [r7, #56] @ 0x38
8000ad4: 00db lsls r3, r3, #3
8000ad6: 4413 add r3, r2
8000ad8: 4619 mov r1, r3
8000ada: f7ff fed1 bl 8000880 <flash_write>
for (int i = 0; i < PARAM_COUNT; i++) {
8000ade: 6bbb ldr r3, [r7, #56] @ 0x38
8000ae0: 3301 adds r3, #1
8000ae2: 63bb str r3, [r7, #56] @ 0x38
8000ae4: 6bbb ldr r3, [r7, #56] @ 0x38
8000ae6: 2b04 cmp r3, #4
8000ae8: ddda ble.n 8000aa0 <compact_page+0x74>
}
}
}
8000aea: bf00 nop
8000aec: bf00 nop
8000aee: 3740 adds r7, #64 @ 0x40
8000af0: 46bd mov sp, r7
8000af2: bd80 pop {r7, pc}
8000af4: 08040000 .word 0x08040000
8000af8: 0805ffff .word 0x0805ffff
8000afc: 20000000 .word 0x20000000
08000b00 <write_param>:
void write_param(uint8_t param_id, uint32_t val) {
8000b00: b580 push {r7, lr}
8000b02: b084 sub sp, #16
8000b04: af00 add r7, sp, #0
8000b06: 4603 mov r3, r0
8000b08: 6039 str r1, [r7, #0]
8000b0a: 71fb strb r3, [r7, #7]
FLASH_RECORD param_flash;
// __disable_irq(); // Interrupt off
param_flash.data_id = param_id;
8000b0c: 79fb ldrb r3, [r7, #7]
8000b0e: 723b strb r3, [r7, #8]
param_flash.value = val;
8000b10: 683b ldr r3, [r7, #0]
8000b12: 60fb str r3, [r7, #12]
param_flash.data_type = sizeof(uint8_t);
8000b14: 2301 movs r3, #1
8000b16: 727b strb r3, [r7, #9]
param_flash.crc = calc_crc_struct(&param_flash);
8000b18: f107 0308 add.w r3, r7, #8
8000b1c: 4618 mov r0, r3
8000b1e: f7ff ff37 bl 8000990 <calc_crc_struct>
8000b22: 4603 mov r3, r0
8000b24: 817b strh r3, [r7, #10]
// check alignment
if (write_ptr % 8 != 0) {
8000b26: 4b17 ldr r3, [pc, #92] @ (8000b84 <write_param+0x84>)
8000b28: 681b ldr r3, [r3, #0]
8000b2a: f003 0307 and.w r3, r3, #7
8000b2e: 2b00 cmp r3, #0
8000b30: d006 beq.n 8000b40 <write_param+0x40>
write_ptr += (8 - (write_ptr % 8));
8000b32: 4b14 ldr r3, [pc, #80] @ (8000b84 <write_param+0x84>)
8000b34: 681b ldr r3, [r3, #0]
8000b36: f023 0307 bic.w r3, r3, #7
8000b3a: 3308 adds r3, #8
8000b3c: 4a11 ldr r2, [pc, #68] @ (8000b84 <write_param+0x84>)
8000b3e: 6013 str r3, [r2, #0]
}
// check buffer overflow
if (write_ptr + FLASH_RECORD_SIZE >= SECTOR_6_END) {
8000b40: 4b10 ldr r3, [pc, #64] @ (8000b84 <write_param+0x84>)
8000b42: 681b ldr r3, [r3, #0]
8000b44: 3308 adds r3, #8
8000b46: 4a10 ldr r2, [pc, #64] @ (8000b88 <write_param+0x88>)
8000b48: 4293 cmp r3, r2
8000b4a: d90e bls.n 8000b6a <write_param+0x6a>
compact_page(); // after compact_page update
8000b4c: f7ff ff6e bl 8000a2c <compact_page>
// alignment
if (write_ptr % 8 != 0) {
8000b50: 4b0c ldr r3, [pc, #48] @ (8000b84 <write_param+0x84>)
8000b52: 681b ldr r3, [r3, #0]
8000b54: f003 0307 and.w r3, r3, #7
8000b58: 2b00 cmp r3, #0
8000b5a: d006 beq.n 8000b6a <write_param+0x6a>
write_ptr += (8 - (write_ptr % 8));
8000b5c: 4b09 ldr r3, [pc, #36] @ (8000b84 <write_param+0x84>)
8000b5e: 681b ldr r3, [r3, #0]
8000b60: f023 0307 bic.w r3, r3, #7
8000b64: 3308 adds r3, #8
8000b66: 4a07 ldr r2, [pc, #28] @ (8000b84 <write_param+0x84>)
8000b68: 6013 str r3, [r2, #0]
}
}
flash_write(write_ptr, &param_flash); //inside the function, the write_ptr pointer is automatically incremented by the size of the structure
8000b6a: 4b06 ldr r3, [pc, #24] @ (8000b84 <write_param+0x84>)
8000b6c: 681b ldr r3, [r3, #0]
8000b6e: f107 0208 add.w r2, r7, #8
8000b72: 4611 mov r1, r2
8000b74: 4618 mov r0, r3
8000b76: f7ff fe83 bl 8000880 <flash_write>
// __enable_irq(); // Interrupt on
}
8000b7a: bf00 nop
8000b7c: 3710 adds r7, #16
8000b7e: 46bd mov sp, r7
8000b80: bd80 pop {r7, pc}
8000b82: bf00 nop
8000b84: 20000000 .word 0x20000000
8000b88: 0805ffff .word 0x0805ffff
08000b8c <write_flash_page>:
void write_flash_page(const uint8_t* data, uint16_t len) { // Добавлен const
8000b8c: b5b0 push {r4, r5, r7, lr}
8000b8e: b084 sub sp, #16
8000b90: af00 add r7, sp, #0
8000b92: 6078 str r0, [r7, #4]
8000b94: 460b mov r3, r1
8000b96: 807b strh r3, [r7, #2]
flash_unlock();
8000b98: f7ff fe06 bl 80007a8 <flash_unlock>
uint32_t word = 0;
8000b9c: 2300 movs r3, #0
8000b9e: 60bb str r3, [r7, #8]
for (uint16_t i = 0; i < len; i += 4) {
8000ba0: 2300 movs r3, #0
8000ba2: 81fb strh r3, [r7, #14]
8000ba4: e014 b.n 8000bd0 <write_flash_page+0x44>
memcpy(&word, &data[i], 4);
8000ba6: 89fb ldrh r3, [r7, #14]
8000ba8: 687a ldr r2, [r7, #4]
8000baa: 4413 add r3, r2
8000bac: 681b ldr r3, [r3, #0]
8000bae: 60bb str r3, [r7, #8]
HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, ptr_fl + i, word);
8000bb0: 89fa ldrh r2, [r7, #14]
8000bb2: 4b0f ldr r3, [pc, #60] @ (8000bf0 <write_flash_page+0x64>)
8000bb4: 681b ldr r3, [r3, #0]
8000bb6: 18d1 adds r1, r2, r3
8000bb8: 68bb ldr r3, [r7, #8]
8000bba: 2200 movs r2, #0
8000bbc: 461c mov r4, r3
8000bbe: 4615 mov r5, r2
8000bc0: 4622 mov r2, r4
8000bc2: 462b mov r3, r5
8000bc4: 2002 movs r0, #2
8000bc6: f002 f835 bl 8002c34 <HAL_FLASH_Program>
for (uint16_t i = 0; i < len; i += 4) {
8000bca: 89fb ldrh r3, [r7, #14]
8000bcc: 3304 adds r3, #4
8000bce: 81fb strh r3, [r7, #14]
8000bd0: 89fa ldrh r2, [r7, #14]
8000bd2: 887b ldrh r3, [r7, #2]
8000bd4: 429a cmp r2, r3
8000bd6: d3e6 bcc.n 8000ba6 <write_flash_page+0x1a>
}
ptr_fl += len;
8000bd8: 887a ldrh r2, [r7, #2]
8000bda: 4b05 ldr r3, [pc, #20] @ (8000bf0 <write_flash_page+0x64>)
8000bdc: 681b ldr r3, [r3, #0]
8000bde: 4413 add r3, r2
8000be0: 4a03 ldr r2, [pc, #12] @ (8000bf0 <write_flash_page+0x64>)
8000be2: 6013 str r3, [r2, #0]
flash_lock();
8000be4: f7ff fdf8 bl 80007d8 <flash_lock>
}
8000be8: bf00 nop
8000bea: 3710 adds r7, #16
8000bec: 46bd mov sp, r7
8000bee: bdb0 pop {r4, r5, r7, pc}
8000bf0: 20000004 .word 0x20000004
08000bf4 <erase_flash_pages>:
void erase_flash_pages() {
8000bf4: b580 push {r7, lr}
8000bf6: b086 sub sp, #24
8000bf8: af00 add r7, sp, #0
FLASH_EraseInitTypeDef erase;
erase.TypeErase = FLASH_TYPEERASE_SECTORS;
8000bfa: 2300 movs r3, #0
8000bfc: 607b str r3, [r7, #4]
erase.Sector = FLASH_SECTOR_2;
8000bfe: 2302 movs r3, #2
8000c00: 60fb str r3, [r7, #12]
erase.NbSectors = 4;
8000c02: 2304 movs r3, #4
8000c04: 613b str r3, [r7, #16]
erase.VoltageRange = FLASH_VOLTAGE_RANGE_3;
8000c06: 2302 movs r3, #2
8000c08: 617b str r3, [r7, #20]
uint32_t error;
flash_unlock();
8000c0a: f7ff fdcd bl 80007a8 <flash_unlock>
HAL_FLASHEx_Erase(&erase, &error);
8000c0e: 463a mov r2, r7
8000c10: 1d3b adds r3, r7, #4
8000c12: 4611 mov r1, r2
8000c14: 4618 mov r0, r3
8000c16: f002 f9a1 bl 8002f5c <HAL_FLASHEx_Erase>
flash_lock();
8000c1a: f7ff fddd bl 80007d8 <flash_lock>
}
8000c1e: bf00 nop
8000c20: 3718 adds r7, #24
8000c22: 46bd mov sp, r7
8000c24: bd80 pop {r7, pc}
...
08000c28 <load_params>:
FLASH_RECORD* load_params(){
8000c28: b580 push {r7, lr}
8000c2a: b084 sub sp, #16
8000c2c: af00 add r7, sp, #0
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
8000c2e: b672 cpsid i
}
8000c30: bf00 nop
__disable_irq();
static FLASH_RECORD latest[PARAM_COUNT] = {0};
FLASH_RECORD res;
for(uint32_t addr = SECTOR_6;addr < SECTOR_6_END;addr +=FLASH_RECORD_SIZE) {
8000c32: 4b19 ldr r3, [pc, #100] @ (8000c98 <load_params+0x70>)
8000c34: 60fb str r3, [r7, #12]
8000c36: e023 b.n 8000c80 <load_params+0x58>
flash_read(addr,&res);
8000c38: 463b mov r3, r7
8000c3a: 4619 mov r1, r3
8000c3c: 68f8 ldr r0, [r7, #12]
8000c3e: f7ff fed3 bl 80009e8 <flash_read>
uint16_t calculated_crc = calc_crc_struct(&res);
8000c42: 463b mov r3, r7
8000c44: 4618 mov r0, r3
8000c46: f7ff fea3 bl 8000990 <calc_crc_struct>
8000c4a: 4603 mov r3, r0
8000c4c: 817b strh r3, [r7, #10]
if (calculated_crc != res.crc || res.data_id >= PARAM_COUNT) continue;
8000c4e: 887b ldrh r3, [r7, #2]
8000c50: 897a ldrh r2, [r7, #10]
8000c52: 429a cmp r2, r3
8000c54: d110 bne.n 8000c78 <load_params+0x50>
8000c56: 783b ldrb r3, [r7, #0]
8000c58: 2b04 cmp r3, #4
8000c5a: d80d bhi.n 8000c78 <load_params+0x50>
else{
latest[res.data_id] = res;
8000c5c: 783b ldrb r3, [r7, #0]
8000c5e: 4a0f ldr r2, [pc, #60] @ (8000c9c <load_params+0x74>)
8000c60: 00db lsls r3, r3, #3
8000c62: 4413 add r3, r2
8000c64: 463a mov r2, r7
8000c66: e892 0003 ldmia.w r2, {r0, r1}
8000c6a: e883 0003 stmia.w r3, {r0, r1}
write_ptr = addr + FLASH_RECORD_SIZE;
8000c6e: 68fb ldr r3, [r7, #12]
8000c70: 3308 adds r3, #8
8000c72: 4a0b ldr r2, [pc, #44] @ (8000ca0 <load_params+0x78>)
8000c74: 6013 str r3, [r2, #0]
8000c76: e000 b.n 8000c7a <load_params+0x52>
if (calculated_crc != res.crc || res.data_id >= PARAM_COUNT) continue;
8000c78: bf00 nop
for(uint32_t addr = SECTOR_6;addr < SECTOR_6_END;addr +=FLASH_RECORD_SIZE) {
8000c7a: 68fb ldr r3, [r7, #12]
8000c7c: 3308 adds r3, #8
8000c7e: 60fb str r3, [r7, #12]
8000c80: 68fb ldr r3, [r7, #12]
8000c82: 4a08 ldr r2, [pc, #32] @ (8000ca4 <load_params+0x7c>)
8000c84: 4293 cmp r3, r2
8000c86: d9d7 bls.n 8000c38 <load_params+0x10>
__ASM volatile ("cpsie i" : : : "memory");
8000c88: b662 cpsie i
}
8000c8a: bf00 nop
}
}
__enable_irq();
return latest;
8000c8c: 4b03 ldr r3, [pc, #12] @ (8000c9c <load_params+0x74>)
}
8000c8e: 4618 mov r0, r3
8000c90: 3710 adds r7, #16
8000c92: 46bd mov sp, r7
8000c94: bd80 pop {r7, pc}
8000c96: bf00 nop
8000c98: 08040000 .word 0x08040000
8000c9c: 200000a0 .word 0x200000a0
8000ca0: 20000000 .word 0x20000000
8000ca4: 0805ffff .word 0x0805ffff
08000ca8 <MX_GPIO_Init>:
* Output
* EVENT_OUT
* EXTI
*/
void MX_GPIO_Init(void)
{
8000ca8: b580 push {r7, lr}
8000caa: b08a sub sp, #40 @ 0x28
8000cac: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
8000cae: f107 0314 add.w r3, r7, #20
8000cb2: 2200 movs r2, #0
8000cb4: 601a str r2, [r3, #0]
8000cb6: 605a str r2, [r3, #4]
8000cb8: 609a str r2, [r3, #8]
8000cba: 60da str r2, [r3, #12]
8000cbc: 611a str r2, [r3, #16]
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOC_CLK_ENABLE();
8000cbe: 2300 movs r3, #0
8000cc0: 613b str r3, [r7, #16]
8000cc2: 4b53 ldr r3, [pc, #332] @ (8000e10 <MX_GPIO_Init+0x168>)
8000cc4: 6b1b ldr r3, [r3, #48] @ 0x30
8000cc6: 4a52 ldr r2, [pc, #328] @ (8000e10 <MX_GPIO_Init+0x168>)
8000cc8: f043 0304 orr.w r3, r3, #4
8000ccc: 6313 str r3, [r2, #48] @ 0x30
8000cce: 4b50 ldr r3, [pc, #320] @ (8000e10 <MX_GPIO_Init+0x168>)
8000cd0: 6b1b ldr r3, [r3, #48] @ 0x30
8000cd2: f003 0304 and.w r3, r3, #4
8000cd6: 613b str r3, [r7, #16]
8000cd8: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOB_CLK_ENABLE();
8000cda: 2300 movs r3, #0
8000cdc: 60fb str r3, [r7, #12]
8000cde: 4b4c ldr r3, [pc, #304] @ (8000e10 <MX_GPIO_Init+0x168>)
8000ce0: 6b1b ldr r3, [r3, #48] @ 0x30
8000ce2: 4a4b ldr r2, [pc, #300] @ (8000e10 <MX_GPIO_Init+0x168>)
8000ce4: f043 0302 orr.w r3, r3, #2
8000ce8: 6313 str r3, [r2, #48] @ 0x30
8000cea: 4b49 ldr r3, [pc, #292] @ (8000e10 <MX_GPIO_Init+0x168>)
8000cec: 6b1b ldr r3, [r3, #48] @ 0x30
8000cee: f003 0302 and.w r3, r3, #2
8000cf2: 60fb str r3, [r7, #12]
8000cf4: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8000cf6: 2300 movs r3, #0
8000cf8: 60bb str r3, [r7, #8]
8000cfa: 4b45 ldr r3, [pc, #276] @ (8000e10 <MX_GPIO_Init+0x168>)
8000cfc: 6b1b ldr r3, [r3, #48] @ 0x30
8000cfe: 4a44 ldr r2, [pc, #272] @ (8000e10 <MX_GPIO_Init+0x168>)
8000d00: f043 0301 orr.w r3, r3, #1
8000d04: 6313 str r3, [r2, #48] @ 0x30
8000d06: 4b42 ldr r3, [pc, #264] @ (8000e10 <MX_GPIO_Init+0x168>)
8000d08: 6b1b ldr r3, [r3, #48] @ 0x30
8000d0a: f003 0301 and.w r3, r3, #1
8000d0e: 60bb str r3, [r7, #8]
8000d10: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOD_CLK_ENABLE();
8000d12: 2300 movs r3, #0
8000d14: 607b str r3, [r7, #4]
8000d16: 4b3e ldr r3, [pc, #248] @ (8000e10 <MX_GPIO_Init+0x168>)
8000d18: 6b1b ldr r3, [r3, #48] @ 0x30
8000d1a: 4a3d ldr r2, [pc, #244] @ (8000e10 <MX_GPIO_Init+0x168>)
8000d1c: f043 0308 orr.w r3, r3, #8
8000d20: 6313 str r3, [r2, #48] @ 0x30
8000d22: 4b3b ldr r3, [pc, #236] @ (8000e10 <MX_GPIO_Init+0x168>)
8000d24: 6b1b ldr r3, [r3, #48] @ 0x30
8000d26: f003 0308 and.w r3, r3, #8
8000d2a: 607b str r3, [r7, #4]
8000d2c: 687b ldr r3, [r7, #4]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(AS5045_CS_GPIO_Port, AS5045_CS_Pin, GPIO_PIN_SET);
8000d2e: 2201 movs r2, #1
8000d30: f44f 4100 mov.w r1, #32768 @ 0x8000
8000d34: 4837 ldr r0, [pc, #220] @ (8000e14 <MX_GPIO_Init+0x16c>)
8000d36: f002 fbc7 bl 80034c8 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOC, EN_W_Pin|DRV_RESET_Pin|DRV_SLEEP_Pin|LED1_Pin
8000d3a: 2200 movs r2, #0
8000d3c: f44f 51fa mov.w r1, #8000 @ 0x1f40
8000d40: 4835 ldr r0, [pc, #212] @ (8000e18 <MX_GPIO_Init+0x170>)
8000d42: f002 fbc1 bl 80034c8 <HAL_GPIO_WritePin>
|LED2_Pin|LED3_Pin, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, EN_U_Pin|EN_V_Pin, GPIO_PIN_RESET);
8000d46: 2200 movs r2, #0
8000d48: f44f 51c0 mov.w r1, #6144 @ 0x1800
8000d4c: 4833 ldr r0, [pc, #204] @ (8000e1c <MX_GPIO_Init+0x174>)
8000d4e: f002 fbbb bl 80034c8 <HAL_GPIO_WritePin>
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(spi1_cs_GPIO_Port, spi1_cs_Pin, GPIO_PIN_RESET);
8000d52: 2200 movs r2, #0
8000d54: 2104 movs r1, #4
8000d56: 4832 ldr r0, [pc, #200] @ (8000e20 <MX_GPIO_Init+0x178>)
8000d58: f002 fbb6 bl 80034c8 <HAL_GPIO_WritePin>
/*Configure GPIO pin : PtPin */
GPIO_InitStruct.Pin = AS5045_CS_Pin;
8000d5c: f44f 4300 mov.w r3, #32768 @ 0x8000
8000d60: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000d62: 2301 movs r3, #1
8000d64: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_PULLUP;
8000d66: 2301 movs r3, #1
8000d68: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000d6a: 2303 movs r3, #3
8000d6c: 623b str r3, [r7, #32]
HAL_GPIO_Init(AS5045_CS_GPIO_Port, &GPIO_InitStruct);
8000d6e: f107 0314 add.w r3, r7, #20
8000d72: 4619 mov r1, r3
8000d74: 4827 ldr r0, [pc, #156] @ (8000e14 <MX_GPIO_Init+0x16c>)
8000d76: f002 fa13 bl 80031a0 <HAL_GPIO_Init>
/*Configure GPIO pin : PtPin */
GPIO_InitStruct.Pin = EN_W_Pin;
8000d7a: 2340 movs r3, #64 @ 0x40
8000d7c: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000d7e: 2301 movs r3, #1
8000d80: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
8000d82: 2302 movs r3, #2
8000d84: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8000d86: 2302 movs r3, #2
8000d88: 623b str r3, [r7, #32]
HAL_GPIO_Init(EN_W_GPIO_Port, &GPIO_InitStruct);
8000d8a: f107 0314 add.w r3, r7, #20
8000d8e: 4619 mov r1, r3
8000d90: 4821 ldr r0, [pc, #132] @ (8000e18 <MX_GPIO_Init+0x170>)
8000d92: f002 fa05 bl 80031a0 <HAL_GPIO_Init>
/*Configure GPIO pin : PtPin */
GPIO_InitStruct.Pin = DRV_FAULT_Pin;
8000d96: 2380 movs r3, #128 @ 0x80
8000d98: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
8000d9a: 2300 movs r3, #0
8000d9c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000d9e: 2300 movs r3, #0
8000da0: 61fb str r3, [r7, #28]
HAL_GPIO_Init(DRV_FAULT_GPIO_Port, &GPIO_InitStruct);
8000da2: f107 0314 add.w r3, r7, #20
8000da6: 4619 mov r1, r3
8000da8: 481b ldr r0, [pc, #108] @ (8000e18 <MX_GPIO_Init+0x170>)
8000daa: f002 f9f9 bl 80031a0 <HAL_GPIO_Init>
/*Configure GPIO pins : PCPin PCPin PCPin PCPin
PCPin */
GPIO_InitStruct.Pin = DRV_RESET_Pin|DRV_SLEEP_Pin|LED1_Pin|LED2_Pin
8000dae: f44f 53f8 mov.w r3, #7936 @ 0x1f00
8000db2: 617b str r3, [r7, #20]
|LED3_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000db4: 2301 movs r3, #1
8000db6: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8000db8: 2300 movs r3, #0
8000dba: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8000dbc: 2300 movs r3, #0
8000dbe: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8000dc0: f107 0314 add.w r3, r7, #20
8000dc4: 4619 mov r1, r3
8000dc6: 4814 ldr r0, [pc, #80] @ (8000e18 <MX_GPIO_Init+0x170>)
8000dc8: f002 f9ea bl 80031a0 <HAL_GPIO_Init>
/*Configure GPIO pins : PAPin PAPin */
GPIO_InitStruct.Pin = EN_U_Pin|EN_V_Pin;
8000dcc: f44f 53c0 mov.w r3, #6144 @ 0x1800
8000dd0: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000dd2: 2301 movs r3, #1
8000dd4: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
8000dd6: 2302 movs r3, #2
8000dd8: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
8000dda: 2302 movs r3, #2
8000ddc: 623b str r3, [r7, #32]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8000dde: f107 0314 add.w r3, r7, #20
8000de2: 4619 mov r1, r3
8000de4: 480d ldr r0, [pc, #52] @ (8000e1c <MX_GPIO_Init+0x174>)
8000de6: f002 f9db bl 80031a0 <HAL_GPIO_Init>
/*Configure GPIO pin : PtPin */
GPIO_InitStruct.Pin = spi1_cs_Pin;
8000dea: 2304 movs r3, #4
8000dec: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8000dee: 2301 movs r3, #1
8000df0: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
8000df2: 2302 movs r3, #2
8000df4: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8000df6: 2303 movs r3, #3
8000df8: 623b str r3, [r7, #32]
HAL_GPIO_Init(spi1_cs_GPIO_Port, &GPIO_InitStruct);
8000dfa: f107 0314 add.w r3, r7, #20
8000dfe: 4619 mov r1, r3
8000e00: 4807 ldr r0, [pc, #28] @ (8000e20 <MX_GPIO_Init+0x178>)
8000e02: f002 f9cd bl 80031a0 <HAL_GPIO_Init>
}
8000e06: bf00 nop
8000e08: 3728 adds r7, #40 @ 0x28
8000e0a: 46bd mov sp, r7
8000e0c: bd80 pop {r7, pc}
8000e0e: bf00 nop
8000e10: 40023800 .word 0x40023800
8000e14: 40020400 .word 0x40020400
8000e18: 40020800 .word 0x40020800
8000e1c: 40020000 .word 0x40020000
8000e20: 40020c00 .word 0x40020c00
08000e24 <__NVIC_SystemReset>:
/**
\brief System Reset
\details Initiates a system reset request to reset the MCU.
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
8000e24: b480 push {r7}
8000e26: af00 add r7, sp, #0
__ASM volatile ("dsb 0xF":::"memory");
8000e28: f3bf 8f4f dsb sy
}
8000e2c: bf00 nop
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
8000e2e: 4b06 ldr r3, [pc, #24] @ (8000e48 <__NVIC_SystemReset+0x24>)
8000e30: 68db ldr r3, [r3, #12]
8000e32: f403 62e0 and.w r2, r3, #1792 @ 0x700
SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8000e36: 4904 ldr r1, [pc, #16] @ (8000e48 <__NVIC_SystemReset+0x24>)
8000e38: 4b04 ldr r3, [pc, #16] @ (8000e4c <__NVIC_SystemReset+0x28>)
8000e3a: 4313 orrs r3, r2
8000e3c: 60cb str r3, [r1, #12]
__ASM volatile ("dsb 0xF":::"memory");
8000e3e: f3bf 8f4f dsb sy
}
8000e42: bf00 nop
SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
8000e44: bf00 nop
8000e46: e7fd b.n 8000e44 <__NVIC_SystemReset+0x20>
8000e48: e000ed00 .word 0xe000ed00
8000e4c: 05fa0004 .word 0x05fa0004
08000e50 <send_ack>:
/* USER CODE END PFP */
/* Private user code ---------------------------------------------------------*/
/* USER CODE BEGIN 0 */
void send_ack(uint8_t status) {
8000e50: b580 push {r7, lr}
8000e52: b08c sub sp, #48 @ 0x30
8000e54: af00 add r7, sp, #0
8000e56: 4603 mov r3, r0
8000e58: 71fb strb r3, [r7, #7]
CAN_TxHeaderTypeDef tx_header;
uint8_t tx_data[1] = {status};
8000e5a: 79fb ldrb r3, [r7, #7]
8000e5c: 743b strb r3, [r7, #16]
uint32_t tx_mailbox;
tx_header.ExtId = ACK_CAN_ID; // id = 0x05
8000e5e: 2305 movs r3, #5
8000e60: 61bb str r3, [r7, #24]
tx_header.IDE = CAN_ID_STD; //standart id
8000e62: 2300 movs r3, #0
8000e64: 61fb str r3, [r7, #28]
tx_header.RTR = CAN_RTR_DATA; // data frame
8000e66: 2300 movs r3, #0
8000e68: 623b str r3, [r7, #32]
tx_header.DLC = 1; // data len = 1 byte
8000e6a: 2301 movs r3, #1
8000e6c: 627b str r3, [r7, #36] @ 0x24
tx_header.TransmitGlobalTime = DISABLE;
8000e6e: 2300 movs r3, #0
8000e70: f887 3028 strb.w r3, [r7, #40] @ 0x28
//send message
HAL_StatusTypeDef result = HAL_CAN_AddTxMessage(&hcan2, &tx_header, tx_data, &tx_mailbox);
8000e74: f107 030c add.w r3, r7, #12
8000e78: f107 0210 add.w r2, r7, #16
8000e7c: f107 0114 add.w r1, r7, #20
8000e80: 4804 ldr r0, [pc, #16] @ (8000e94 <send_ack+0x44>)
8000e82: f001 fbb8 bl 80025f6 <HAL_CAN_AddTxMessage>
8000e86: 4603 mov r3, r0
8000e88: f887 302f strb.w r3, [r7, #47] @ 0x2f
if(result != HAL_OK) {
/* TO DO
*
*/
}
}
8000e8c: bf00 nop
8000e8e: 3730 adds r7, #48 @ 0x30
8000e90: 46bd mov sp, r7
8000e92: bd80 pop {r7, pc}
8000e94: 20000078 .word 0x20000078
08000e98 <verify_firmware>:
bool verify_firmware() {
8000e98: b580 push {r7, lr}
8000e9a: b082 sub sp, #8
8000e9c: af00 add r7, sp, #0
uint16_t calculated_crc = 0;
8000e9e: 2300 movs r3, #0
8000ea0: 80fb strh r3, [r7, #6]
calculated_crc = validate_crc16((uint8_t*)APP_ADDRESS,fw_size);
8000ea2: 4b0a ldr r3, [pc, #40] @ (8000ecc <verify_firmware+0x34>)
8000ea4: 681b ldr r3, [r3, #0]
8000ea6: 4619 mov r1, r3
8000ea8: 4809 ldr r0, [pc, #36] @ (8000ed0 <verify_firmware+0x38>)
8000eaa: f7ff fd39 bl 8000920 <validate_crc16>
8000eae: 4603 mov r3, r0
8000eb0: 80fb strh r3, [r7, #6]
return (calculated_crc == fw_crc);
8000eb2: 4b08 ldr r3, [pc, #32] @ (8000ed4 <verify_firmware+0x3c>)
8000eb4: 881b ldrh r3, [r3, #0]
8000eb6: b29b uxth r3, r3
8000eb8: 88fa ldrh r2, [r7, #6]
8000eba: 429a cmp r2, r3
8000ebc: bf0c ite eq
8000ebe: 2301 moveq r3, #1
8000ec0: 2300 movne r3, #0
8000ec2: b2db uxtb r3, r3
}
8000ec4: 4618 mov r0, r3
8000ec6: 3708 adds r7, #8
8000ec8: 46bd mov sp, r7
8000eca: bd80 pop {r7, pc}
8000ecc: 200000cc .word 0x200000cc
8000ed0: 08008000 .word 0x08008000
8000ed4: 200000d0 .word 0x200000d0
08000ed8 <process_can_message>:
void process_can_message(CAN_RxHeaderTypeDef *header, uint8_t *data) {
8000ed8: b580 push {r7, lr}
8000eda: b084 sub sp, #16
8000edc: af00 add r7, sp, #0
8000ede: 6078 str r0, [r7, #4]
8000ee0: 6039 str r1, [r7, #0]
msg_id = header->ExtId;
8000ee2: 687b ldr r3, [r7, #4]
8000ee4: 685b ldr r3, [r3, #4]
8000ee6: 4a41 ldr r2, [pc, #260] @ (8000fec <process_can_message+0x114>)
8000ee8: 6013 str r3, [r2, #0]
/* 0x697
69 - slave addr
7 || 8 - REG_READ or REG_WRITE */
id_x = (msg_id >> 4) & 0xFFFF; // get addr
8000eea: 4b40 ldr r3, [pc, #256] @ (8000fec <process_can_message+0x114>)
8000eec: 681b ldr r3, [r3, #0]
8000eee: 091b lsrs r3, r3, #4
8000ef0: b29a uxth r2, r3
8000ef2: 4b3f ldr r3, [pc, #252] @ (8000ff0 <process_can_message+0x118>)
8000ef4: 801a strh r2, [r3, #0]
msg_ch = msg_id & 0xF; // check cmd
8000ef6: 4b3d ldr r3, [pc, #244] @ (8000fec <process_can_message+0x114>)
8000ef8: 681b ldr r3, [r3, #0]
8000efa: b2db uxtb r3, r3
8000efc: f003 030f and.w r3, r3, #15
8000f00: b2da uxtb r2, r3
8000f02: 4b3c ldr r3, [pc, #240] @ (8000ff4 <process_can_message+0x11c>)
8000f04: 701a strb r2, [r3, #0]
// Check addr
if(id_x == flash_record[addr_id].value) {
8000f06: 4b3a ldr r3, [pc, #232] @ (8000ff0 <process_can_message+0x118>)
8000f08: 881b ldrh r3, [r3, #0]
8000f0a: b29b uxth r3, r3
8000f0c: 461a mov r2, r3
8000f0e: 4b3a ldr r3, [pc, #232] @ (8000ff8 <process_can_message+0x120>)
8000f10: 681b ldr r3, [r3, #0]
8000f12: 685b ldr r3, [r3, #4]
8000f14: 429a cmp r2, r3
8000f16: d164 bne.n 8000fe2 <process_can_message+0x10a>
switch(msg_ch) {
8000f18: 4b36 ldr r3, [pc, #216] @ (8000ff4 <process_can_message+0x11c>)
8000f1a: 781b ldrb r3, [r3, #0]
8000f1c: b2db uxtb r3, r3
8000f1e: 2b03 cmp r3, #3
8000f20: d01b beq.n 8000f5a <process_can_message+0x82>
8000f22: 2b03 cmp r3, #3
8000f24: dc5d bgt.n 8000fe2 <process_can_message+0x10a>
8000f26: 2b01 cmp r3, #1
8000f28: d002 beq.n 8000f30 <process_can_message+0x58>
8000f2a: 2b02 cmp r3, #2
8000f2c: d03b beq.n 8000fa6 <process_can_message+0xce>
erase_flash_pages(); // Erase error firwmare
}
break;
}
}
}
8000f2e: e058 b.n 8000fe2 <process_can_message+0x10a>
if(data[0] == 0x01) {
8000f30: 683b ldr r3, [r7, #0]
8000f32: 781b ldrb r3, [r3, #0]
8000f34: 2b01 cmp r3, #1
8000f36: d151 bne.n 8000fdc <process_can_message+0x104>
fw_size = *((uint32_t*)&data[1]);
8000f38: 683b ldr r3, [r7, #0]
8000f3a: f8d3 3001 ldr.w r3, [r3, #1]
8000f3e: 4a2f ldr r2, [pc, #188] @ (8000ffc <process_can_message+0x124>)
8000f40: 6013 str r3, [r2, #0]
fw_crc = *((uint16_t*)&data[5]);
8000f42: 683b ldr r3, [r7, #0]
8000f44: f8b3 2005 ldrh.w r2, [r3, #5]
8000f48: 4b2d ldr r3, [pc, #180] @ (8001000 <process_can_message+0x128>)
8000f4a: 801a strh r2, [r3, #0]
ptr_flash = APP_ADDRESS;
8000f4c: 4b2d ldr r3, [pc, #180] @ (8001004 <process_can_message+0x12c>)
8000f4e: 4a2e ldr r2, [pc, #184] @ (8001008 <process_can_message+0x130>)
8000f50: 601a str r2, [r3, #0]
send_ack(0x01);
8000f52: 2001 movs r0, #1
8000f54: f7ff ff7c bl 8000e50 <send_ack>
break;
8000f58: e040 b.n 8000fdc <process_can_message+0x104>
if(ptr_flash < (APP_ADDRESS + fw_size)) {
8000f5a: 4b28 ldr r3, [pc, #160] @ (8000ffc <process_can_message+0x124>)
8000f5c: 681b ldr r3, [r3, #0]
8000f5e: f103 6300 add.w r3, r3, #134217728 @ 0x8000000
8000f62: f503 4300 add.w r3, r3, #32768 @ 0x8000
8000f66: 4a27 ldr r2, [pc, #156] @ (8001004 <process_can_message+0x12c>)
8000f68: 6812 ldr r2, [r2, #0]
8000f6a: 4293 cmp r3, r2
8000f6c: d938 bls.n 8000fe0 <process_can_message+0x108>
memcpy(aligned_data, data, header->DLC); //copy from data to aligned_data
8000f6e: 687b ldr r3, [r7, #4]
8000f70: 691a ldr r2, [r3, #16]
8000f72: f107 0308 add.w r3, r7, #8
8000f76: 6839 ldr r1, [r7, #0]
8000f78: 4618 mov r0, r3
8000f7a: f004 fd49 bl 8005a10 <memcpy>
write_flash_page(aligned_data, header->DLC);
8000f7e: 687b ldr r3, [r7, #4]
8000f80: 691b ldr r3, [r3, #16]
8000f82: b29a uxth r2, r3
8000f84: f107 0308 add.w r3, r7, #8
8000f88: 4611 mov r1, r2
8000f8a: 4618 mov r0, r3
8000f8c: f7ff fdfe bl 8000b8c <write_flash_page>
ptr_flash += header->DLC;
8000f90: 687b ldr r3, [r7, #4]
8000f92: 691a ldr r2, [r3, #16]
8000f94: 4b1b ldr r3, [pc, #108] @ (8001004 <process_can_message+0x12c>)
8000f96: 681b ldr r3, [r3, #0]
8000f98: 4413 add r3, r2
8000f9a: 4a1a ldr r2, [pc, #104] @ (8001004 <process_can_message+0x12c>)
8000f9c: 6013 str r3, [r2, #0]
send_ack(0x02);
8000f9e: 2002 movs r0, #2
8000fa0: f7ff ff56 bl 8000e50 <send_ack>
break;
8000fa4: e01c b.n 8000fe0 <process_can_message+0x108>
if(verify_firmware()) {
8000fa6: f7ff ff77 bl 8000e98 <verify_firmware>
8000faa: 4603 mov r3, r0
8000fac: 2b00 cmp r3, #0
8000fae: d00f beq.n 8000fd0 <process_can_message+0xf8>
send_ack(0xAA);
8000fb0: 20aa movs r0, #170 @ 0xaa
8000fb2: f7ff ff4d bl 8000e50 <send_ack>
write_param(firmw, 0); // Reset firmware update
8000fb6: 2100 movs r1, #0
8000fb8: 2004 movs r0, #4
8000fba: f7ff fda1 bl 8000b00 <write_param>
fw_update = false;
8000fbe: 4b13 ldr r3, [pc, #76] @ (800100c <process_can_message+0x134>)
8000fc0: 2200 movs r2, #0
8000fc2: 701a strb r2, [r3, #0]
HAL_Delay(500);
8000fc4: f44f 70fa mov.w r0, #500 @ 0x1f4
8000fc8: f000 fe4c bl 8001c64 <HAL_Delay>
NVIC_SystemReset();
8000fcc: f7ff ff2a bl 8000e24 <__NVIC_SystemReset>
send_ack(0x55); // Error
8000fd0: 2055 movs r0, #85 @ 0x55
8000fd2: f7ff ff3d bl 8000e50 <send_ack>
erase_flash_pages(); // Erase error firwmare
8000fd6: f7ff fe0d bl 8000bf4 <erase_flash_pages>
break;
8000fda: e002 b.n 8000fe2 <process_can_message+0x10a>
break;
8000fdc: bf00 nop
8000fde: e000 b.n 8000fe2 <process_can_message+0x10a>
break;
8000fe0: bf00 nop
}
8000fe2: bf00 nop
8000fe4: 3710 adds r7, #16
8000fe6: 46bd mov sp, r7
8000fe8: bd80 pop {r7, pc}
8000fea: bf00 nop
8000fec: 200000e0 .word 0x200000e0
8000ff0: 200000e4 .word 0x200000e4
8000ff4: 200000e6 .word 0x200000e6
8000ff8: 200000d8 .word 0x200000d8
8000ffc: 200000cc .word 0x200000cc
8001000: 200000d0 .word 0x200000d0
8001004: 200000dc .word 0x200000dc
8001008: 08008000 .word 0x08008000
800100c: 200000c8 .word 0x200000c8
08001010 <jump_to_app>:
void jump_to_app() {
8001010: b580 push {r7, lr}
8001012: b084 sub sp, #16
8001014: af00 add r7, sp, #0
__ASM volatile ("cpsid i" : : : "memory");
8001016: b672 cpsid i
}
8001018: bf00 nop
__disable_irq();
jump = *(volatile uint32_t*)(APP_ADDRESS + 4);
800101a: 4b12 ldr r3, [pc, #72] @ (8001064 <jump_to_app+0x54>)
800101c: 681b ldr r3, [r3, #0]
800101e: 4a12 ldr r2, [pc, #72] @ (8001068 <jump_to_app+0x58>)
8001020: 6013 str r3, [r2, #0]
void (*app_entry)(void);
app_entry = (void (*)(void))jump;
8001022: 4b11 ldr r3, [pc, #68] @ (8001068 <jump_to_app+0x58>)
8001024: 681b ldr r3, [r3, #0]
8001026: 60bb str r3, [r7, #8]
for (uint32_t i = 0; i < 8; i++) {
8001028: 2300 movs r3, #0
800102a: 60fb str r3, [r7, #12]
800102c: e009 b.n 8001042 <jump_to_app+0x32>
NVIC->ICPR[i] = 0xFFFFFFFF;
800102e: 4a0f ldr r2, [pc, #60] @ (800106c <jump_to_app+0x5c>)
8001030: 68fb ldr r3, [r7, #12]
8001032: 3360 adds r3, #96 @ 0x60
8001034: f04f 31ff mov.w r1, #4294967295
8001038: f842 1023 str.w r1, [r2, r3, lsl #2]
for (uint32_t i = 0; i < 8; i++) {
800103c: 68fb ldr r3, [r7, #12]
800103e: 3301 adds r3, #1
8001040: 60fb str r3, [r7, #12]
8001042: 68fb ldr r3, [r7, #12]
8001044: 2b07 cmp r3, #7
8001046: d9f2 bls.n 800102e <jump_to_app+0x1e>
}
__set_MSP(*(volatile uint32_t*)APP_ADDRESS);
8001048: 4b09 ldr r3, [pc, #36] @ (8001070 <jump_to_app+0x60>)
800104a: 681b ldr r3, [r3, #0]
800104c: 607b str r3, [r7, #4]
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
800104e: 687b ldr r3, [r7, #4]
8001050: f383 8808 msr MSP, r3
}
8001054: bf00 nop
// SCB->VTOR = (uint32_t)0x08008004;
app_entry();
8001056: 68bb ldr r3, [r7, #8]
8001058: 4798 blx r3
}
800105a: bf00 nop
800105c: 3710 adds r7, #16
800105e: 46bd mov sp, r7
8001060: bd80 pop {r7, pc}
8001062: bf00 nop
8001064: 08008004 .word 0x08008004
8001068: 200000d4 .word 0x200000d4
800106c: e000e100 .word 0xe000e100
8001070: 08008000 .word 0x08008000
08001074 <is_app_valid>:
bool is_app_valid() {
8001074: b480 push {r7}
8001076: b083 sub sp, #12
8001078: af00 add r7, sp, #0
volatile uint32_t* app_vector = (volatile uint32_t*)APP_ADDRESS;
800107a: 4b28 ldr r3, [pc, #160] @ (800111c <is_app_valid+0xa8>)
800107c: 607b str r3, [r7, #4]
// Check stack pointer
bool sp_valid = (app_vector[0] >= 0x20000000) &&
800107e: 687b ldr r3, [r7, #4]
8001080: 681b ldr r3, [r3, #0]
8001082: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8001086: d306 bcc.n 8001096 <is_app_valid+0x22>
(app_vector[0] <= (0x20000000 + 128*1024)); // Для STM32 с 128K RAM
8001088: 687b ldr r3, [r7, #4]
800108a: 681b ldr r3, [r3, #0]
bool sp_valid = (app_vector[0] >= 0x20000000) &&
800108c: 4a24 ldr r2, [pc, #144] @ (8001120 <is_app_valid+0xac>)
800108e: 4293 cmp r3, r2
8001090: d801 bhi.n 8001096 <is_app_valid+0x22>
8001092: 2301 movs r3, #1
8001094: e000 b.n 8001098 <is_app_valid+0x24>
8001096: 2300 movs r3, #0
8001098: 70fb strb r3, [r7, #3]
800109a: 78fb ldrb r3, [r7, #3]
800109c: f003 0301 and.w r3, r3, #1
80010a0: 70fb strb r3, [r7, #3]
// check reset_handler
bool pc_valid = (app_vector[1] >= 0x08000000) &&
80010a2: 687b ldr r3, [r7, #4]
80010a4: 3304 adds r3, #4
80010a6: 681b ldr r3, [r3, #0]
80010a8: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
80010ac: d307 bcc.n 80010be <is_app_valid+0x4a>
(app_vector[1] <= (0x08000000 + 1024*1024)); // Для 1MB Flash
80010ae: 687b ldr r3, [r7, #4]
80010b0: 3304 adds r3, #4
80010b2: 681b ldr r3, [r3, #0]
bool pc_valid = (app_vector[1] >= 0x08000000) &&
80010b4: f1b3 6f01 cmp.w r3, #135266304 @ 0x8100000
80010b8: d801 bhi.n 80010be <is_app_valid+0x4a>
80010ba: 2301 movs r3, #1
80010bc: e000 b.n 80010c0 <is_app_valid+0x4c>
80010be: 2300 movs r3, #0
80010c0: 70bb strb r3, [r7, #2]
80010c2: 78bb ldrb r3, [r7, #2]
80010c4: f003 0301 and.w r3, r3, #1
80010c8: 70bb strb r3, [r7, #2]
// check two words on reset value
bool not_erased = (app_vector[0] != 0xFFFFFFFF) &&
80010ca: 687b ldr r3, [r7, #4]
80010cc: 681b ldr r3, [r3, #0]
80010ce: f1b3 3fff cmp.w r3, #4294967295
80010d2: d007 beq.n 80010e4 <is_app_valid+0x70>
(app_vector[1] != 0xFFFFFFFF);
80010d4: 687b ldr r3, [r7, #4]
80010d6: 3304 adds r3, #4
80010d8: 681b ldr r3, [r3, #0]
bool not_erased = (app_vector[0] != 0xFFFFFFFF) &&
80010da: f1b3 3fff cmp.w r3, #4294967295
80010de: d001 beq.n 80010e4 <is_app_valid+0x70>
80010e0: 2301 movs r3, #1
80010e2: e000 b.n 80010e6 <is_app_valid+0x72>
80010e4: 2300 movs r3, #0
80010e6: 707b strb r3, [r7, #1]
80010e8: 787b ldrb r3, [r7, #1]
80010ea: f003 0301 and.w r3, r3, #1
80010ee: 707b strb r3, [r7, #1]
return sp_valid && pc_valid && not_erased;
80010f0: 78fb ldrb r3, [r7, #3]
80010f2: 2b00 cmp r3, #0
80010f4: d007 beq.n 8001106 <is_app_valid+0x92>
80010f6: 78bb ldrb r3, [r7, #2]
80010f8: 2b00 cmp r3, #0
80010fa: d004 beq.n 8001106 <is_app_valid+0x92>
80010fc: 787b ldrb r3, [r7, #1]
80010fe: 2b00 cmp r3, #0
8001100: d001 beq.n 8001106 <is_app_valid+0x92>
8001102: 2301 movs r3, #1
8001104: e000 b.n 8001108 <is_app_valid+0x94>
8001106: 2300 movs r3, #0
8001108: f003 0301 and.w r3, r3, #1
800110c: b2db uxtb r3, r3
}
800110e: 4618 mov r0, r3
8001110: 370c adds r7, #12
8001112: 46bd mov sp, r7
8001114: f85d 7b04 ldr.w r7, [sp], #4
8001118: 4770 bx lr
800111a: bf00 nop
800111c: 08008000 .word 0x08008000
8001120: 20020000 .word 0x20020000
08001124 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8001124: b580 push {r7, lr}
8001126: b08c sub sp, #48 @ 0x30
8001128: af00 add r7, sp, #0
/* USER CODE BEGIN 1 */
// Настройка GPIO
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN;
800112a: 4b44 ldr r3, [pc, #272] @ (800123c <main+0x118>)
800112c: 6b1b ldr r3, [r3, #48] @ 0x30
800112e: 4a43 ldr r2, [pc, #268] @ (800123c <main+0x118>)
8001130: f043 0304 orr.w r3, r3, #4
8001134: 6313 str r3, [r2, #48] @ 0x30
GPIOC->MODER |= GPIO_MODER_MODE10_0 | GPIO_MODER_MODE11_0;
8001136: 4b42 ldr r3, [pc, #264] @ (8001240 <main+0x11c>)
8001138: 681b ldr r3, [r3, #0]
800113a: 4a41 ldr r2, [pc, #260] @ (8001240 <main+0x11c>)
800113c: f443 03a0 orr.w r3, r3, #5242880 @ 0x500000
8001140: 6013 str r3, [r2, #0]
GPIOC->ODR &= ~GPIO_ODR_OD11;
8001142: 4b3f ldr r3, [pc, #252] @ (8001240 <main+0x11c>)
8001144: 695b ldr r3, [r3, #20]
8001146: 4a3e ldr r2, [pc, #248] @ (8001240 <main+0x11c>)
8001148: f423 6300 bic.w r3, r3, #2048 @ 0x800
800114c: 6153 str r3, [r2, #20]
GPIOC->ODR |= GPIO_ODR_OD10;
800114e: 4b3c ldr r3, [pc, #240] @ (8001240 <main+0x11c>)
8001150: 695b ldr r3, [r3, #20]
8001152: 4a3b ldr r2, [pc, #236] @ (8001240 <main+0x11c>)
8001154: f443 6380 orr.w r3, r3, #1024 @ 0x400
8001158: 6153 str r3, [r2, #20]
flash_record = load_params();
800115a: f7ff fd65 bl 8000c28 <load_params>
800115e: 4603 mov r3, r0
8001160: 4a38 ldr r2, [pc, #224] @ (8001244 <main+0x120>)
8001162: 6013 str r3, [r2, #0]
if(flash_record[firmw].value == UPDATE_FLAG) {
8001164: 4b37 ldr r3, [pc, #220] @ (8001244 <main+0x120>)
8001166: 681b ldr r3, [r3, #0]
8001168: 3320 adds r3, #32
800116a: 685b ldr r3, [r3, #4]
800116c: 4a36 ldr r2, [pc, #216] @ (8001248 <main+0x124>)
800116e: 4293 cmp r3, r2
8001170: d117 bne.n 80011a2 <main+0x7e>
fw_update = true;
8001172: 4b36 ldr r3, [pc, #216] @ (800124c <main+0x128>)
8001174: 2201 movs r2, #1
8001176: 701a strb r2, [r3, #0]
for(int i = 0; i < 5;i++){
8001178: 2300 movs r3, #0
800117a: 62fb str r3, [r7, #44] @ 0x2c
800117c: e00b b.n 8001196 <main+0x72>
GPIOC->ODR ^= GPIO_ODR_OD10; // Indecate message
800117e: 4b30 ldr r3, [pc, #192] @ (8001240 <main+0x11c>)
8001180: 695b ldr r3, [r3, #20]
8001182: 4a2f ldr r2, [pc, #188] @ (8001240 <main+0x11c>)
8001184: f483 6380 eor.w r3, r3, #1024 @ 0x400
8001188: 6153 str r3, [r2, #20]
HAL_Delay(100);
800118a: 2064 movs r0, #100 @ 0x64
800118c: f000 fd6a bl 8001c64 <HAL_Delay>
for(int i = 0; i < 5;i++){
8001190: 6afb ldr r3, [r7, #44] @ 0x2c
8001192: 3301 adds r3, #1
8001194: 62fb str r3, [r7, #44] @ 0x2c
8001196: 6afb ldr r3, [r7, #44] @ 0x2c
8001198: 2b04 cmp r3, #4
800119a: ddf0 ble.n 800117e <main+0x5a>
}
// write_param(firmw,0); //reset flasg
erase_flash_pages();
800119c: f7ff fd2a bl 8000bf4 <erase_flash_pages>
80011a0: e00a b.n 80011b8 <main+0x94>
}
else{
// for st-link update, because he doesnt reset flag_update
if(is_app_valid()) jump_to_app(); //firmware exist
80011a2: f7ff ff67 bl 8001074 <is_app_valid>
80011a6: 4603 mov r3, r0
80011a8: 2b00 cmp r3, #0
80011aa: d002 beq.n 80011b2 <main+0x8e>
80011ac: f7ff ff30 bl 8001010 <jump_to_app>
80011b0: e002 b.n 80011b8 <main+0x94>
else fw_update = true; //firmware doesnt exist, but we in bootloader
80011b2: 4b26 ldr r3, [pc, #152] @ (800124c <main+0x128>)
80011b4: 2201 movs r2, #1
80011b6: 701a strb r2, [r3, #0]
}
GPIOC->ODR |= GPIO_ODR_OD10;
80011b8: 4b21 ldr r3, [pc, #132] @ (8001240 <main+0x11c>)
80011ba: 695b ldr r3, [r3, #20]
80011bc: 4a20 ldr r2, [pc, #128] @ (8001240 <main+0x11c>)
80011be: f443 6380 orr.w r3, r3, #1024 @ 0x400
80011c2: 6153 str r3, [r2, #20]
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
80011c4: f000 fd0c bl 8001be0 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
80011c8: f000 f844 bl 8001254 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
80011cc: f7ff fd6c bl 8000ca8 <MX_GPIO_Init>
MX_TIM1_Init();
80011d0: f000 fa8a bl 80016e8 <MX_TIM1_Init>
MX_USART1_UART_Init();
80011d4: f000 fc68 bl 8001aa8 <MX_USART1_UART_Init>
MX_SPI2_Init();
80011d8: f000 f8d0 bl 800137c <MX_SPI2_Init>
MX_TIM3_Init();
80011dc: f000 fb3c bl 8001858 <MX_TIM3_Init>
MX_ADC2_Init();
80011e0: f7ff f988 bl 80004f4 <MX_ADC2_Init>
MX_TIM5_Init();
80011e4: f000 fb84 bl 80018f0 <MX_TIM5_Init>
MX_CAN2_Init();
80011e8: f7ff fa52 bl 8000690 <MX_CAN2_Init>
/* Initialize interrupts */
MX_NVIC_Init();
80011ec: f000 f8a4 bl 8001338 <MX_NVIC_Init>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
while (1) {
if(fw_update) {
80011f0: 4b16 ldr r3, [pc, #88] @ (800124c <main+0x128>)
80011f2: 781b ldrb r3, [r3, #0]
80011f4: b2db uxtb r3, r3
80011f6: 2b00 cmp r3, #0
80011f8: d0fa beq.n 80011f0 <main+0xcc>
CAN_RxHeaderTypeDef rx_header;
uint8_t rx_data[8];
HAL_StatusTypeDef status;
// Check message
if(HAL_CAN_GetRxFifoFillLevel(&hcan2, CAN_RX_FIFO0) > 0) {
80011fa: 2100 movs r1, #0
80011fc: 4814 ldr r0, [pc, #80] @ (8001250 <main+0x12c>)
80011fe: f001 fbec bl 80029da <HAL_CAN_GetRxFifoFillLevel>
8001202: 4603 mov r3, r0
8001204: 2b00 cmp r3, #0
8001206: d0f3 beq.n 80011f0 <main+0xcc>
status = HAL_CAN_GetRxMessage(&hcan2, CAN_RX_FIFO0, &rx_header, rx_data);
8001208: 1d3b adds r3, r7, #4
800120a: f107 020c add.w r2, r7, #12
800120e: 2100 movs r1, #0
8001210: 480f ldr r0, [pc, #60] @ (8001250 <main+0x12c>)
8001212: f001 fac0 bl 8002796 <HAL_CAN_GetRxMessage>
8001216: 4603 mov r3, r0
8001218: f887 302b strb.w r3, [r7, #43] @ 0x2b
if(status == HAL_OK) {
800121c: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
8001220: 2b00 cmp r3, #0
8001222: d1e5 bne.n 80011f0 <main+0xcc>
// check message IDE standart
if(rx_header.IDE == CAN_ID_STD) {
8001224: 697b ldr r3, [r7, #20]
8001226: 2b00 cmp r3, #0
8001228: d1e2 bne.n 80011f0 <main+0xcc>
process_can_message(&rx_header, rx_data);
800122a: 1d3a adds r2, r7, #4
800122c: f107 030c add.w r3, r7, #12
8001230: 4611 mov r1, r2
8001232: 4618 mov r0, r3
8001234: f7ff fe50 bl 8000ed8 <process_can_message>
if(fw_update) {
8001238: e7da b.n 80011f0 <main+0xcc>
800123a: bf00 nop
800123c: 40023800 .word 0x40023800
8001240: 40020800 .word 0x40020800
8001244: 200000d8 .word 0x200000d8
8001248: deadbeef .word 0xdeadbeef
800124c: 200000c8 .word 0x200000c8
8001250: 20000078 .word 0x20000078
08001254 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8001254: b580 push {r7, lr}
8001256: b094 sub sp, #80 @ 0x50
8001258: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
800125a: f107 031c add.w r3, r7, #28
800125e: 2234 movs r2, #52 @ 0x34
8001260: 2100 movs r1, #0
8001262: 4618 mov r0, r3
8001264: f004 fba8 bl 80059b8 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8001268: f107 0308 add.w r3, r7, #8
800126c: 2200 movs r2, #0
800126e: 601a str r2, [r3, #0]
8001270: 605a str r2, [r3, #4]
8001272: 609a str r2, [r3, #8]
8001274: 60da str r2, [r3, #12]
8001276: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
__HAL_RCC_PWR_CLK_ENABLE();
8001278: 2300 movs r3, #0
800127a: 607b str r3, [r7, #4]
800127c: 4b2c ldr r3, [pc, #176] @ (8001330 <SystemClock_Config+0xdc>)
800127e: 6c1b ldr r3, [r3, #64] @ 0x40
8001280: 4a2b ldr r2, [pc, #172] @ (8001330 <SystemClock_Config+0xdc>)
8001282: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8001286: 6413 str r3, [r2, #64] @ 0x40
8001288: 4b29 ldr r3, [pc, #164] @ (8001330 <SystemClock_Config+0xdc>)
800128a: 6c1b ldr r3, [r3, #64] @ 0x40
800128c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001290: 607b str r3, [r7, #4]
8001292: 687b ldr r3, [r7, #4]
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
8001294: 2300 movs r3, #0
8001296: 603b str r3, [r7, #0]
8001298: 4b26 ldr r3, [pc, #152] @ (8001334 <SystemClock_Config+0xe0>)
800129a: 681b ldr r3, [r3, #0]
800129c: 4a25 ldr r2, [pc, #148] @ (8001334 <SystemClock_Config+0xe0>)
800129e: f443 4340 orr.w r3, r3, #49152 @ 0xc000
80012a2: 6013 str r3, [r2, #0]
80012a4: 4b23 ldr r3, [pc, #140] @ (8001334 <SystemClock_Config+0xe0>)
80012a6: 681b ldr r3, [r3, #0]
80012a8: f403 4340 and.w r3, r3, #49152 @ 0xc000
80012ac: 603b str r3, [r7, #0]
80012ae: 683b ldr r3, [r7, #0]
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
80012b0: 2302 movs r3, #2
80012b2: 61fb str r3, [r7, #28]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
80012b4: 2301 movs r3, #1
80012b6: 62bb str r3, [r7, #40] @ 0x28
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
80012b8: 2310 movs r3, #16
80012ba: 62fb str r3, [r7, #44] @ 0x2c
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
80012bc: 2302 movs r3, #2
80012be: 637b str r3, [r7, #52] @ 0x34
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
80012c0: 2300 movs r3, #0
80012c2: 63bb str r3, [r7, #56] @ 0x38
RCC_OscInitStruct.PLL.PLLM = 8;
80012c4: 2308 movs r3, #8
80012c6: 63fb str r3, [r7, #60] @ 0x3c
RCC_OscInitStruct.PLL.PLLN = 180;
80012c8: 23b4 movs r3, #180 @ 0xb4
80012ca: 643b str r3, [r7, #64] @ 0x40
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
80012cc: 2302 movs r3, #2
80012ce: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.PLL.PLLQ = 2;
80012d0: 2302 movs r3, #2
80012d2: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLR = 2;
80012d4: 2302 movs r3, #2
80012d6: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80012d8: f107 031c add.w r3, r7, #28
80012dc: 4618 mov r0, r3
80012de: f002 fcd9 bl 8003c94 <HAL_RCC_OscConfig>
80012e2: 4603 mov r3, r0
80012e4: 2b00 cmp r3, #0
80012e6: d001 beq.n 80012ec <SystemClock_Config+0x98>
{
Error_Handler();
80012e8: f000 f841 bl 800136e <Error_Handler>
}
/** Activate the Over-Drive mode
*/
if (HAL_PWREx_EnableOverDrive() != HAL_OK)
80012ec: f002 f906 bl 80034fc <HAL_PWREx_EnableOverDrive>
80012f0: 4603 mov r3, r0
80012f2: 2b00 cmp r3, #0
80012f4: d001 beq.n 80012fa <SystemClock_Config+0xa6>
{
Error_Handler();
80012f6: f000 f83a bl 800136e <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80012fa: 230f movs r3, #15
80012fc: 60bb str r3, [r7, #8]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
80012fe: 2302 movs r3, #2
8001300: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
8001302: 2300 movs r3, #0
8001304: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
8001306: f44f 53a0 mov.w r3, #5120 @ 0x1400
800130a: 617b str r3, [r7, #20]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
800130c: f44f 5380 mov.w r3, #4096 @ 0x1000
8001310: 61bb str r3, [r7, #24]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
8001312: f107 0308 add.w r3, r7, #8
8001316: 2105 movs r1, #5
8001318: 4618 mov r0, r3
800131a: f002 f93f bl 800359c <HAL_RCC_ClockConfig>
800131e: 4603 mov r3, r0
8001320: 2b00 cmp r3, #0
8001322: d001 beq.n 8001328 <SystemClock_Config+0xd4>
{
Error_Handler();
8001324: f000 f823 bl 800136e <Error_Handler>
}
}
8001328: bf00 nop
800132a: 3750 adds r7, #80 @ 0x50
800132c: 46bd mov sp, r7
800132e: bd80 pop {r7, pc}
8001330: 40023800 .word 0x40023800
8001334: 40007000 .word 0x40007000
08001338 <MX_NVIC_Init>:
/**
* @brief NVIC Configuration.
* @retval None
*/
static void MX_NVIC_Init(void)
{
8001338: b580 push {r7, lr}
800133a: af00 add r7, sp, #0
/* ADC_IRQn interrupt configuration */
HAL_NVIC_SetPriority(ADC_IRQn, 5, 0);
800133c: 2200 movs r2, #0
800133e: 2105 movs r1, #5
8001340: 2012 movs r0, #18
8001342: f001 fc2b bl 8002b9c <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(ADC_IRQn);
8001346: 2012 movs r0, #18
8001348: f001 fc44 bl 8002bd4 <HAL_NVIC_EnableIRQ>
}
800134c: bf00 nop
800134e: bd80 pop {r7, pc}
08001350 <HAL_TIM_PeriodElapsedCallback>:
* a global variable "uwTick" used as application time base.
* @param htim : TIM handle
* @retval None
*/
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
{
8001350: b580 push {r7, lr}
8001352: b082 sub sp, #8
8001354: af00 add r7, sp, #0
8001356: 6078 str r0, [r7, #4]
/* USER CODE BEGIN Callback 0 */
/* USER CODE END Callback 0 */
if (htim->Instance == TIM2) {
8001358: 687b ldr r3, [r7, #4]
800135a: 681b ldr r3, [r3, #0]
800135c: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8001360: d101 bne.n 8001366 <HAL_TIM_PeriodElapsedCallback+0x16>
HAL_IncTick();
8001362: f000 fc5f bl 8001c24 <HAL_IncTick>
}
/* USER CODE BEGIN Callback 1 */
/* USER CODE END Callback 1 */
}
8001366: bf00 nop
8001368: 3708 adds r7, #8
800136a: 46bd mov sp, r7
800136c: bd80 pop {r7, pc}
0800136e <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
800136e: b480 push {r7}
8001370: af00 add r7, sp, #0
__ASM volatile ("cpsid i" : : : "memory");
8001372: b672 cpsid i
}
8001374: bf00 nop
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
8001376: bf00 nop
8001378: e7fd b.n 8001376 <Error_Handler+0x8>
...
0800137c <MX_SPI2_Init>:
SPI_HandleTypeDef hspi2;
/* SPI2 init function */
void MX_SPI2_Init(void)
{
800137c: b580 push {r7, lr}
800137e: af00 add r7, sp, #0
/* USER CODE END SPI2_Init 0 */
/* USER CODE BEGIN SPI2_Init 1 */
/* USER CODE END SPI2_Init 1 */
hspi2.Instance = SPI2;
8001380: 4b18 ldr r3, [pc, #96] @ (80013e4 <MX_SPI2_Init+0x68>)
8001382: 4a19 ldr r2, [pc, #100] @ (80013e8 <MX_SPI2_Init+0x6c>)
8001384: 601a str r2, [r3, #0]
hspi2.Init.Mode = SPI_MODE_MASTER;
8001386: 4b17 ldr r3, [pc, #92] @ (80013e4 <MX_SPI2_Init+0x68>)
8001388: f44f 7282 mov.w r2, #260 @ 0x104
800138c: 605a str r2, [r3, #4]
hspi2.Init.Direction = SPI_DIRECTION_2LINES;
800138e: 4b15 ldr r3, [pc, #84] @ (80013e4 <MX_SPI2_Init+0x68>)
8001390: 2200 movs r2, #0
8001392: 609a str r2, [r3, #8]
hspi2.Init.DataSize = SPI_DATASIZE_16BIT;
8001394: 4b13 ldr r3, [pc, #76] @ (80013e4 <MX_SPI2_Init+0x68>)
8001396: f44f 6200 mov.w r2, #2048 @ 0x800
800139a: 60da str r2, [r3, #12]
hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
800139c: 4b11 ldr r3, [pc, #68] @ (80013e4 <MX_SPI2_Init+0x68>)
800139e: 2200 movs r2, #0
80013a0: 611a str r2, [r3, #16]
hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
80013a2: 4b10 ldr r3, [pc, #64] @ (80013e4 <MX_SPI2_Init+0x68>)
80013a4: 2200 movs r2, #0
80013a6: 615a str r2, [r3, #20]
hspi2.Init.NSS = SPI_NSS_SOFT;
80013a8: 4b0e ldr r3, [pc, #56] @ (80013e4 <MX_SPI2_Init+0x68>)
80013aa: f44f 7200 mov.w r2, #512 @ 0x200
80013ae: 619a str r2, [r3, #24]
hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;
80013b0: 4b0c ldr r3, [pc, #48] @ (80013e4 <MX_SPI2_Init+0x68>)
80013b2: 2228 movs r2, #40 @ 0x28
80013b4: 61da str r2, [r3, #28]
hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
80013b6: 4b0b ldr r3, [pc, #44] @ (80013e4 <MX_SPI2_Init+0x68>)
80013b8: 2200 movs r2, #0
80013ba: 621a str r2, [r3, #32]
hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
80013bc: 4b09 ldr r3, [pc, #36] @ (80013e4 <MX_SPI2_Init+0x68>)
80013be: 2200 movs r2, #0
80013c0: 625a str r2, [r3, #36] @ 0x24
hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
80013c2: 4b08 ldr r3, [pc, #32] @ (80013e4 <MX_SPI2_Init+0x68>)
80013c4: 2200 movs r2, #0
80013c6: 629a str r2, [r3, #40] @ 0x28
hspi2.Init.CRCPolynomial = 10;
80013c8: 4b06 ldr r3, [pc, #24] @ (80013e4 <MX_SPI2_Init+0x68>)
80013ca: 220a movs r2, #10
80013cc: 62da str r2, [r3, #44] @ 0x2c
if (HAL_SPI_Init(&hspi2) != HAL_OK)
80013ce: 4805 ldr r0, [pc, #20] @ (80013e4 <MX_SPI2_Init+0x68>)
80013d0: f002 fefe bl 80041d0 <HAL_SPI_Init>
80013d4: 4603 mov r3, r0
80013d6: 2b00 cmp r3, #0
80013d8: d001 beq.n 80013de <MX_SPI2_Init+0x62>
{
Error_Handler();
80013da: f7ff ffc8 bl 800136e <Error_Handler>
}
/* USER CODE BEGIN SPI2_Init 2 */
/* USER CODE END SPI2_Init 2 */
}
80013de: bf00 nop
80013e0: bd80 pop {r7, pc}
80013e2: bf00 nop
80013e4: 200000e8 .word 0x200000e8
80013e8: 40003800 .word 0x40003800
080013ec <HAL_SPI_MspInit>:
void HAL_SPI_MspInit(SPI_HandleTypeDef* spiHandle)
{
80013ec: b580 push {r7, lr}
80013ee: b08a sub sp, #40 @ 0x28
80013f0: af00 add r7, sp, #0
80013f2: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80013f4: f107 0314 add.w r3, r7, #20
80013f8: 2200 movs r2, #0
80013fa: 601a str r2, [r3, #0]
80013fc: 605a str r2, [r3, #4]
80013fe: 609a str r2, [r3, #8]
8001400: 60da str r2, [r3, #12]
8001402: 611a str r2, [r3, #16]
if(spiHandle->Instance==SPI2)
8001404: 687b ldr r3, [r7, #4]
8001406: 681b ldr r3, [r3, #0]
8001408: 4a2c ldr r2, [pc, #176] @ (80014bc <HAL_SPI_MspInit+0xd0>)
800140a: 4293 cmp r3, r2
800140c: d152 bne.n 80014b4 <HAL_SPI_MspInit+0xc8>
{
/* USER CODE BEGIN SPI2_MspInit 0 */
/* USER CODE END SPI2_MspInit 0 */
/* SPI2 clock enable */
__HAL_RCC_SPI2_CLK_ENABLE();
800140e: 2300 movs r3, #0
8001410: 613b str r3, [r7, #16]
8001412: 4b2b ldr r3, [pc, #172] @ (80014c0 <HAL_SPI_MspInit+0xd4>)
8001414: 6c1b ldr r3, [r3, #64] @ 0x40
8001416: 4a2a ldr r2, [pc, #168] @ (80014c0 <HAL_SPI_MspInit+0xd4>)
8001418: f443 4380 orr.w r3, r3, #16384 @ 0x4000
800141c: 6413 str r3, [r2, #64] @ 0x40
800141e: 4b28 ldr r3, [pc, #160] @ (80014c0 <HAL_SPI_MspInit+0xd4>)
8001420: 6c1b ldr r3, [r3, #64] @ 0x40
8001422: f403 4380 and.w r3, r3, #16384 @ 0x4000
8001426: 613b str r3, [r7, #16]
8001428: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOC_CLK_ENABLE();
800142a: 2300 movs r3, #0
800142c: 60fb str r3, [r7, #12]
800142e: 4b24 ldr r3, [pc, #144] @ (80014c0 <HAL_SPI_MspInit+0xd4>)
8001430: 6b1b ldr r3, [r3, #48] @ 0x30
8001432: 4a23 ldr r2, [pc, #140] @ (80014c0 <HAL_SPI_MspInit+0xd4>)
8001434: f043 0304 orr.w r3, r3, #4
8001438: 6313 str r3, [r2, #48] @ 0x30
800143a: 4b21 ldr r3, [pc, #132] @ (80014c0 <HAL_SPI_MspInit+0xd4>)
800143c: 6b1b ldr r3, [r3, #48] @ 0x30
800143e: f003 0304 and.w r3, r3, #4
8001442: 60fb str r3, [r7, #12]
8001444: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001446: 2300 movs r3, #0
8001448: 60bb str r3, [r7, #8]
800144a: 4b1d ldr r3, [pc, #116] @ (80014c0 <HAL_SPI_MspInit+0xd4>)
800144c: 6b1b ldr r3, [r3, #48] @ 0x30
800144e: 4a1c ldr r2, [pc, #112] @ (80014c0 <HAL_SPI_MspInit+0xd4>)
8001450: f043 0302 orr.w r3, r3, #2
8001454: 6313 str r3, [r2, #48] @ 0x30
8001456: 4b1a ldr r3, [pc, #104] @ (80014c0 <HAL_SPI_MspInit+0xd4>)
8001458: 6b1b ldr r3, [r3, #48] @ 0x30
800145a: f003 0302 and.w r3, r3, #2
800145e: 60bb str r3, [r7, #8]
8001460: 68bb ldr r3, [r7, #8]
/**SPI2 GPIO Configuration
PC1 ------> SPI2_MOSI
PB10 ------> SPI2_SCK
PB14 ------> SPI2_MISO
*/
GPIO_InitStruct.Pin = GPIO_PIN_1;
8001462: 2302 movs r3, #2
8001464: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001466: 2302 movs r3, #2
8001468: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800146a: 2300 movs r3, #0
800146c: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
800146e: 2303 movs r3, #3
8001470: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF7_SPI2;
8001472: 2307 movs r3, #7
8001474: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
8001476: f107 0314 add.w r3, r7, #20
800147a: 4619 mov r1, r3
800147c: 4811 ldr r0, [pc, #68] @ (80014c4 <HAL_SPI_MspInit+0xd8>)
800147e: f001 fe8f bl 80031a0 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_14;
8001482: f44f 4388 mov.w r3, #17408 @ 0x4400
8001486: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001488: 2302 movs r3, #2
800148a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800148c: 2300 movs r3, #0
800148e: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001490: 2303 movs r3, #3
8001492: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
8001494: 2305 movs r3, #5
8001496: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001498: f107 0314 add.w r3, r7, #20
800149c: 4619 mov r1, r3
800149e: 480a ldr r0, [pc, #40] @ (80014c8 <HAL_SPI_MspInit+0xdc>)
80014a0: f001 fe7e bl 80031a0 <HAL_GPIO_Init>
/* SPI2 interrupt Init */
HAL_NVIC_SetPriority(SPI2_IRQn, 0, 0);
80014a4: 2200 movs r2, #0
80014a6: 2100 movs r1, #0
80014a8: 2024 movs r0, #36 @ 0x24
80014aa: f001 fb77 bl 8002b9c <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(SPI2_IRQn);
80014ae: 2024 movs r0, #36 @ 0x24
80014b0: f001 fb90 bl 8002bd4 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN SPI2_MspInit 1 */
/* USER CODE END SPI2_MspInit 1 */
}
}
80014b4: bf00 nop
80014b6: 3728 adds r7, #40 @ 0x28
80014b8: 46bd mov sp, r7
80014ba: bd80 pop {r7, pc}
80014bc: 40003800 .word 0x40003800
80014c0: 40023800 .word 0x40023800
80014c4: 40020800 .word 0x40020800
80014c8: 40020400 .word 0x40020400
080014cc <HAL_MspInit>:
/* USER CODE END 0 */
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
80014cc: b480 push {r7}
80014ce: b083 sub sp, #12
80014d0: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80014d2: 2300 movs r3, #0
80014d4: 607b str r3, [r7, #4]
80014d6: 4b10 ldr r3, [pc, #64] @ (8001518 <HAL_MspInit+0x4c>)
80014d8: 6c5b ldr r3, [r3, #68] @ 0x44
80014da: 4a0f ldr r2, [pc, #60] @ (8001518 <HAL_MspInit+0x4c>)
80014dc: f443 4380 orr.w r3, r3, #16384 @ 0x4000
80014e0: 6453 str r3, [r2, #68] @ 0x44
80014e2: 4b0d ldr r3, [pc, #52] @ (8001518 <HAL_MspInit+0x4c>)
80014e4: 6c5b ldr r3, [r3, #68] @ 0x44
80014e6: f403 4380 and.w r3, r3, #16384 @ 0x4000
80014ea: 607b str r3, [r7, #4]
80014ec: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
80014ee: 2300 movs r3, #0
80014f0: 603b str r3, [r7, #0]
80014f2: 4b09 ldr r3, [pc, #36] @ (8001518 <HAL_MspInit+0x4c>)
80014f4: 6c1b ldr r3, [r3, #64] @ 0x40
80014f6: 4a08 ldr r2, [pc, #32] @ (8001518 <HAL_MspInit+0x4c>)
80014f8: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80014fc: 6413 str r3, [r2, #64] @ 0x40
80014fe: 4b06 ldr r3, [pc, #24] @ (8001518 <HAL_MspInit+0x4c>)
8001500: 6c1b ldr r3, [r3, #64] @ 0x40
8001502: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001506: 603b str r3, [r7, #0]
8001508: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800150a: bf00 nop
800150c: 370c adds r7, #12
800150e: 46bd mov sp, r7
8001510: f85d 7b04 ldr.w r7, [sp], #4
8001514: 4770 bx lr
8001516: bf00 nop
8001518: 40023800 .word 0x40023800
0800151c <HAL_InitTick>:
* reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig().
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
800151c: b580 push {r7, lr}
800151e: b08e sub sp, #56 @ 0x38
8001520: af00 add r7, sp, #0
8001522: 6078 str r0, [r7, #4]
RCC_ClkInitTypeDef clkconfig;
uint32_t uwTimclock, uwAPB1Prescaler = 0U;
8001524: 2300 movs r3, #0
8001526: 62fb str r3, [r7, #44] @ 0x2c
uint32_t uwPrescalerValue = 0U;
8001528: 2300 movs r3, #0
800152a: 62bb str r3, [r7, #40] @ 0x28
uint32_t pFLatency;
HAL_StatusTypeDef status;
/* Enable TIM2 clock */
__HAL_RCC_TIM2_CLK_ENABLE();
800152c: 2300 movs r3, #0
800152e: 60fb str r3, [r7, #12]
8001530: 4b34 ldr r3, [pc, #208] @ (8001604 <HAL_InitTick+0xe8>)
8001532: 6c1b ldr r3, [r3, #64] @ 0x40
8001534: 4a33 ldr r2, [pc, #204] @ (8001604 <HAL_InitTick+0xe8>)
8001536: f043 0301 orr.w r3, r3, #1
800153a: 6413 str r3, [r2, #64] @ 0x40
800153c: 4b31 ldr r3, [pc, #196] @ (8001604 <HAL_InitTick+0xe8>)
800153e: 6c1b ldr r3, [r3, #64] @ 0x40
8001540: f003 0301 and.w r3, r3, #1
8001544: 60fb str r3, [r7, #12]
8001546: 68fb ldr r3, [r7, #12]
/* Get clock configuration */
HAL_RCC_GetClockConfig(&clkconfig, &pFLatency);
8001548: f107 0210 add.w r2, r7, #16
800154c: f107 0314 add.w r3, r7, #20
8001550: 4611 mov r1, r2
8001552: 4618 mov r0, r3
8001554: f002 f93c bl 80037d0 <HAL_RCC_GetClockConfig>
/* Get APB1 prescaler */
uwAPB1Prescaler = clkconfig.APB1CLKDivider;
8001558: 6a3b ldr r3, [r7, #32]
800155a: 62fb str r3, [r7, #44] @ 0x2c
/* Compute TIM2 clock */
if (uwAPB1Prescaler == RCC_HCLK_DIV1)
800155c: 6afb ldr r3, [r7, #44] @ 0x2c
800155e: 2b00 cmp r3, #0
8001560: d103 bne.n 800156a <HAL_InitTick+0x4e>
{
uwTimclock = HAL_RCC_GetPCLK1Freq();
8001562: f002 f90d bl 8003780 <HAL_RCC_GetPCLK1Freq>
8001566: 6378 str r0, [r7, #52] @ 0x34
8001568: e004 b.n 8001574 <HAL_InitTick+0x58>
}
else
{
uwTimclock = 2UL * HAL_RCC_GetPCLK1Freq();
800156a: f002 f909 bl 8003780 <HAL_RCC_GetPCLK1Freq>
800156e: 4603 mov r3, r0
8001570: 005b lsls r3, r3, #1
8001572: 637b str r3, [r7, #52] @ 0x34
}
/* Compute the prescaler value to have TIM2 counter clock equal to 1MHz */
uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U);
8001574: 6b7b ldr r3, [r7, #52] @ 0x34
8001576: 4a24 ldr r2, [pc, #144] @ (8001608 <HAL_InitTick+0xec>)
8001578: fba2 2303 umull r2, r3, r2, r3
800157c: 0c9b lsrs r3, r3, #18
800157e: 3b01 subs r3, #1
8001580: 62bb str r3, [r7, #40] @ 0x28
/* Initialize TIM2 */
htim2.Instance = TIM2;
8001582: 4b22 ldr r3, [pc, #136] @ (800160c <HAL_InitTick+0xf0>)
8001584: f04f 4280 mov.w r2, #1073741824 @ 0x40000000
8001588: 601a str r2, [r3, #0]
+ Period = [(TIM2CLK/1000) - 1]. to have a (1/1000) s time base.
+ Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock.
+ ClockDivision = 0
+ Counter direction = Up
*/
htim2.Init.Period = (1000000U / 1000U) - 1U;
800158a: 4b20 ldr r3, [pc, #128] @ (800160c <HAL_InitTick+0xf0>)
800158c: f240 32e7 movw r2, #999 @ 0x3e7
8001590: 60da str r2, [r3, #12]
htim2.Init.Prescaler = uwPrescalerValue;
8001592: 4a1e ldr r2, [pc, #120] @ (800160c <HAL_InitTick+0xf0>)
8001594: 6abb ldr r3, [r7, #40] @ 0x28
8001596: 6053 str r3, [r2, #4]
htim2.Init.ClockDivision = 0;
8001598: 4b1c ldr r3, [pc, #112] @ (800160c <HAL_InitTick+0xf0>)
800159a: 2200 movs r2, #0
800159c: 611a str r2, [r3, #16]
htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
800159e: 4b1b ldr r3, [pc, #108] @ (800160c <HAL_InitTick+0xf0>)
80015a0: 2200 movs r2, #0
80015a2: 609a str r2, [r3, #8]
htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
80015a4: 4b19 ldr r3, [pc, #100] @ (800160c <HAL_InitTick+0xf0>)
80015a6: 2200 movs r2, #0
80015a8: 619a str r2, [r3, #24]
status = HAL_TIM_Base_Init(&htim2);
80015aa: 4818 ldr r0, [pc, #96] @ (800160c <HAL_InitTick+0xf0>)
80015ac: f002 ffac bl 8004508 <HAL_TIM_Base_Init>
80015b0: 4603 mov r3, r0
80015b2: f887 3033 strb.w r3, [r7, #51] @ 0x33
if (status == HAL_OK)
80015b6: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
80015ba: 2b00 cmp r3, #0
80015bc: d11b bne.n 80015f6 <HAL_InitTick+0xda>
{
/* Start the TIM time Base generation in interrupt mode */
status = HAL_TIM_Base_Start_IT(&htim2);
80015be: 4813 ldr r0, [pc, #76] @ (800160c <HAL_InitTick+0xf0>)
80015c0: f002 fff2 bl 80045a8 <HAL_TIM_Base_Start_IT>
80015c4: 4603 mov r3, r0
80015c6: f887 3033 strb.w r3, [r7, #51] @ 0x33
if (status == HAL_OK)
80015ca: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
80015ce: 2b00 cmp r3, #0
80015d0: d111 bne.n 80015f6 <HAL_InitTick+0xda>
{
/* Enable the TIM2 global Interrupt */
HAL_NVIC_EnableIRQ(TIM2_IRQn);
80015d2: 201c movs r0, #28
80015d4: f001 fafe bl 8002bd4 <HAL_NVIC_EnableIRQ>
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
80015d8: 687b ldr r3, [r7, #4]
80015da: 2b0f cmp r3, #15
80015dc: d808 bhi.n 80015f0 <HAL_InitTick+0xd4>
{
/* Configure the TIM IRQ priority */
HAL_NVIC_SetPriority(TIM2_IRQn, TickPriority, 0U);
80015de: 2200 movs r2, #0
80015e0: 6879 ldr r1, [r7, #4]
80015e2: 201c movs r0, #28
80015e4: f001 fada bl 8002b9c <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
80015e8: 4a09 ldr r2, [pc, #36] @ (8001610 <HAL_InitTick+0xf4>)
80015ea: 687b ldr r3, [r7, #4]
80015ec: 6013 str r3, [r2, #0]
80015ee: e002 b.n 80015f6 <HAL_InitTick+0xda>
}
else
{
status = HAL_ERROR;
80015f0: 2301 movs r3, #1
80015f2: f887 3033 strb.w r3, [r7, #51] @ 0x33
}
}
}
/* Return function status */
return status;
80015f6: f897 3033 ldrb.w r3, [r7, #51] @ 0x33
}
80015fa: 4618 mov r0, r3
80015fc: 3738 adds r7, #56 @ 0x38
80015fe: 46bd mov sp, r7
8001600: bd80 pop {r7, pc}
8001602: bf00 nop
8001604: 40023800 .word 0x40023800
8001608: 431bde83 .word 0x431bde83
800160c: 20000140 .word 0x20000140
8001610: 2000000c .word 0x2000000c
08001614 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
8001614: b480 push {r7}
8001616: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8001618: bf00 nop
800161a: e7fd b.n 8001618 <NMI_Handler+0x4>
0800161c <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
800161c: b480 push {r7}
800161e: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
8001620: bf00 nop
8001622: e7fd b.n 8001620 <HardFault_Handler+0x4>
08001624 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
8001624: b480 push {r7}
8001626: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
8001628: bf00 nop
800162a: e7fd b.n 8001628 <MemManage_Handler+0x4>
0800162c <BusFault_Handler>:
/**
* @brief This function handles Pre-fetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
800162c: b480 push {r7}
800162e: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
8001630: bf00 nop
8001632: e7fd b.n 8001630 <BusFault_Handler+0x4>
08001634 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
8001634: b480 push {r7}
8001636: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
8001638: bf00 nop
800163a: e7fd b.n 8001638 <UsageFault_Handler+0x4>
0800163c <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
800163c: b480 push {r7}
800163e: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
8001640: bf00 nop
8001642: 46bd mov sp, r7
8001644: f85d 7b04 ldr.w r7, [sp], #4
8001648: 4770 bx lr
0800164a <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
800164a: b480 push {r7}
800164c: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
800164e: bf00 nop
8001650: 46bd mov sp, r7
8001652: f85d 7b04 ldr.w r7, [sp], #4
8001656: 4770 bx lr
08001658 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8001658: b480 push {r7}
800165a: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
800165c: bf00 nop
800165e: 46bd mov sp, r7
8001660: f85d 7b04 ldr.w r7, [sp], #4
8001664: 4770 bx lr
08001666 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8001666: b480 push {r7}
8001668: af00 add r7, sp, #0
/* USER CODE END SysTick_IRQn 0 */
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
800166a: bf00 nop
800166c: 46bd mov sp, r7
800166e: f85d 7b04 ldr.w r7, [sp], #4
8001672: 4770 bx lr
08001674 <ADC_IRQHandler>:
/**
* @brief This function handles ADC1, ADC2 and ADC3 interrupts.
*/
void ADC_IRQHandler(void)
{
8001674: b580 push {r7, lr}
8001676: af00 add r7, sp, #0
/* USER CODE BEGIN ADC_IRQn 0 */
/* USER CODE END ADC_IRQn 0 */
HAL_ADC_IRQHandler(&hadc2);
8001678: 4802 ldr r0, [pc, #8] @ (8001684 <ADC_IRQHandler+0x10>)
800167a: f000 fb5a bl 8001d32 <HAL_ADC_IRQHandler>
/* USER CODE BEGIN ADC_IRQn 1 */
/* USER CODE END ADC_IRQn 1 */
}
800167e: bf00 nop
8001680: bd80 pop {r7, pc}
8001682: bf00 nop
8001684: 20000030 .word 0x20000030
08001688 <TIM2_IRQHandler>:
/**
* @brief This function handles TIM2 global interrupt.
*/
void TIM2_IRQHandler(void)
{
8001688: b580 push {r7, lr}
800168a: af00 add r7, sp, #0
/* USER CODE BEGIN TIM2_IRQn 0 */
/* USER CODE END TIM2_IRQn 0 */
HAL_TIM_IRQHandler(&htim2);
800168c: 4802 ldr r0, [pc, #8] @ (8001698 <TIM2_IRQHandler+0x10>)
800168e: f003 f854 bl 800473a <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM2_IRQn 1 */
/* USER CODE END TIM2_IRQn 1 */
}
8001692: bf00 nop
8001694: bd80 pop {r7, pc}
8001696: bf00 nop
8001698: 20000140 .word 0x20000140
0800169c <TIM3_IRQHandler>:
/**
* @brief This function handles TIM3 global interrupt.
*/
void TIM3_IRQHandler(void)
{
800169c: b580 push {r7, lr}
800169e: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_IRQn 0 */
/* USER CODE END TIM3_IRQn 0 */
HAL_TIM_IRQHandler(&htim3);
80016a0: 4802 ldr r0, [pc, #8] @ (80016ac <TIM3_IRQHandler+0x10>)
80016a2: f003 f84a bl 800473a <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM3_IRQn 1 */
/* USER CODE END TIM3_IRQn 1 */
}
80016a6: bf00 nop
80016a8: bd80 pop {r7, pc}
80016aa: bf00 nop
80016ac: 200001d0 .word 0x200001d0
080016b0 <SPI2_IRQHandler>:
/**
* @brief This function handles SPI2 global interrupt.
*/
void SPI2_IRQHandler(void)
{
80016b0: b580 push {r7, lr}
80016b2: af00 add r7, sp, #0
/* USER CODE BEGIN SPI2_IRQn 0 */
/* USER CODE END SPI2_IRQn 0 */
HAL_SPI_IRQHandler(&hspi2);
80016b4: 4802 ldr r0, [pc, #8] @ (80016c0 <SPI2_IRQHandler+0x10>)
80016b6: f002 fe15 bl 80042e4 <HAL_SPI_IRQHandler>
/* USER CODE BEGIN SPI2_IRQn 1 */
/* USER CODE END SPI2_IRQn 1 */
}
80016ba: bf00 nop
80016bc: bd80 pop {r7, pc}
80016be: bf00 nop
80016c0: 200000e8 .word 0x200000e8
080016c4 <SystemInit>:
* configuration.
* @param None
* @retval None
*/
void SystemInit(void)
{
80016c4: b480 push {r7}
80016c6: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
80016c8: 4b06 ldr r3, [pc, #24] @ (80016e4 <SystemInit+0x20>)
80016ca: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80016ce: 4a05 ldr r2, [pc, #20] @ (80016e4 <SystemInit+0x20>)
80016d0: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
80016d4: f8c2 3088 str.w r3, [r2, #136] @ 0x88
/* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
80016d8: bf00 nop
80016da: 46bd mov sp, r7
80016dc: f85d 7b04 ldr.w r7, [sp], #4
80016e0: 4770 bx lr
80016e2: bf00 nop
80016e4: e000ed00 .word 0xe000ed00
080016e8 <MX_TIM1_Init>:
TIM_HandleTypeDef htim3;
TIM_HandleTypeDef htim5;
/* TIM1 init function */
void MX_TIM1_Init(void)
{
80016e8: b580 push {r7, lr}
80016ea: b096 sub sp, #88 @ 0x58
80016ec: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80016ee: f107 0348 add.w r3, r7, #72 @ 0x48
80016f2: 2200 movs r2, #0
80016f4: 601a str r2, [r3, #0]
80016f6: 605a str r2, [r3, #4]
80016f8: 609a str r2, [r3, #8]
80016fa: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
80016fc: f107 0340 add.w r3, r7, #64 @ 0x40
8001700: 2200 movs r2, #0
8001702: 601a str r2, [r3, #0]
8001704: 605a str r2, [r3, #4]
TIM_OC_InitTypeDef sConfigOC = {0};
8001706: f107 0324 add.w r3, r7, #36 @ 0x24
800170a: 2200 movs r2, #0
800170c: 601a str r2, [r3, #0]
800170e: 605a str r2, [r3, #4]
8001710: 609a str r2, [r3, #8]
8001712: 60da str r2, [r3, #12]
8001714: 611a str r2, [r3, #16]
8001716: 615a str r2, [r3, #20]
8001718: 619a str r2, [r3, #24]
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
800171a: 1d3b adds r3, r7, #4
800171c: 2220 movs r2, #32
800171e: 2100 movs r1, #0
8001720: 4618 mov r0, r3
8001722: f004 f949 bl 80059b8 <memset>
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1;
8001726: 4b4a ldr r3, [pc, #296] @ (8001850 <MX_TIM1_Init+0x168>)
8001728: 4a4a ldr r2, [pc, #296] @ (8001854 <MX_TIM1_Init+0x16c>)
800172a: 601a str r2, [r3, #0]
htim1.Init.Prescaler = 0;
800172c: 4b48 ldr r3, [pc, #288] @ (8001850 <MX_TIM1_Init+0x168>)
800172e: 2200 movs r2, #0
8001730: 605a str r2, [r3, #4]
htim1.Init.CounterMode = TIM_COUNTERMODE_CENTERALIGNED1;
8001732: 4b47 ldr r3, [pc, #284] @ (8001850 <MX_TIM1_Init+0x168>)
8001734: 2220 movs r2, #32
8001736: 609a str r2, [r3, #8]
htim1.Init.Period = 2399;
8001738: 4b45 ldr r3, [pc, #276] @ (8001850 <MX_TIM1_Init+0x168>)
800173a: f640 125f movw r2, #2399 @ 0x95f
800173e: 60da str r2, [r3, #12]
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001740: 4b43 ldr r3, [pc, #268] @ (8001850 <MX_TIM1_Init+0x168>)
8001742: 2200 movs r2, #0
8001744: 611a str r2, [r3, #16]
htim1.Init.RepetitionCounter = 0;
8001746: 4b42 ldr r3, [pc, #264] @ (8001850 <MX_TIM1_Init+0x168>)
8001748: 2200 movs r2, #0
800174a: 615a str r2, [r3, #20]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE;
800174c: 4b40 ldr r3, [pc, #256] @ (8001850 <MX_TIM1_Init+0x168>)
800174e: 2280 movs r2, #128 @ 0x80
8001750: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
8001752: 483f ldr r0, [pc, #252] @ (8001850 <MX_TIM1_Init+0x168>)
8001754: f002 fed8 bl 8004508 <HAL_TIM_Base_Init>
8001758: 4603 mov r3, r0
800175a: 2b00 cmp r3, #0
800175c: d001 beq.n 8001762 <MX_TIM1_Init+0x7a>
{
Error_Handler();
800175e: f7ff fe06 bl 800136e <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8001762: f44f 5380 mov.w r3, #4096 @ 0x1000
8001766: 64bb str r3, [r7, #72] @ 0x48
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
8001768: f107 0348 add.w r3, r7, #72 @ 0x48
800176c: 4619 mov r1, r3
800176e: 4838 ldr r0, [pc, #224] @ (8001850 <MX_TIM1_Init+0x168>)
8001770: f003 f996 bl 8004aa0 <HAL_TIM_ConfigClockSource>
8001774: 4603 mov r3, r0
8001776: 2b00 cmp r3, #0
8001778: d001 beq.n 800177e <MX_TIM1_Init+0x96>
{
Error_Handler();
800177a: f7ff fdf8 bl 800136e <Error_Handler>
}
if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
800177e: 4834 ldr r0, [pc, #208] @ (8001850 <MX_TIM1_Init+0x168>)
8001780: f002 ff82 bl 8004688 <HAL_TIM_PWM_Init>
8001784: 4603 mov r3, r0
8001786: 2b00 cmp r3, #0
8001788: d001 beq.n 800178e <MX_TIM1_Init+0xa6>
{
Error_Handler();
800178a: f7ff fdf0 bl 800136e <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
800178e: 2300 movs r3, #0
8001790: 643b str r3, [r7, #64] @ 0x40
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8001792: 2300 movs r3, #0
8001794: 647b str r3, [r7, #68] @ 0x44
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
8001796: f107 0340 add.w r3, r7, #64 @ 0x40
800179a: 4619 mov r1, r3
800179c: 482c ldr r0, [pc, #176] @ (8001850 <MX_TIM1_Init+0x168>)
800179e: f003 fd65 bl 800526c <HAL_TIMEx_MasterConfigSynchronization>
80017a2: 4603 mov r3, r0
80017a4: 2b00 cmp r3, #0
80017a6: d001 beq.n 80017ac <MX_TIM1_Init+0xc4>
{
Error_Handler();
80017a8: f7ff fde1 bl 800136e <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_PWM1;
80017ac: 2360 movs r3, #96 @ 0x60
80017ae: 627b str r3, [r7, #36] @ 0x24
sConfigOC.Pulse = 0;
80017b0: 2300 movs r3, #0
80017b2: 62bb str r3, [r7, #40] @ 0x28
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
80017b4: 2300 movs r3, #0
80017b6: 62fb str r3, [r7, #44] @ 0x2c
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
80017b8: 2300 movs r3, #0
80017ba: 633b str r3, [r7, #48] @ 0x30
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
80017bc: 2300 movs r3, #0
80017be: 637b str r3, [r7, #52] @ 0x34
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
80017c0: 2300 movs r3, #0
80017c2: 63bb str r3, [r7, #56] @ 0x38
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
80017c4: 2300 movs r3, #0
80017c6: 63fb str r3, [r7, #60] @ 0x3c
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
80017c8: f107 0324 add.w r3, r7, #36 @ 0x24
80017cc: 2200 movs r2, #0
80017ce: 4619 mov r1, r3
80017d0: 481f ldr r0, [pc, #124] @ (8001850 <MX_TIM1_Init+0x168>)
80017d2: f003 f8a3 bl 800491c <HAL_TIM_PWM_ConfigChannel>
80017d6: 4603 mov r3, r0
80017d8: 2b00 cmp r3, #0
80017da: d001 beq.n 80017e0 <MX_TIM1_Init+0xf8>
{
Error_Handler();
80017dc: f7ff fdc7 bl 800136e <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
80017e0: f107 0324 add.w r3, r7, #36 @ 0x24
80017e4: 2204 movs r2, #4
80017e6: 4619 mov r1, r3
80017e8: 4819 ldr r0, [pc, #100] @ (8001850 <MX_TIM1_Init+0x168>)
80017ea: f003 f897 bl 800491c <HAL_TIM_PWM_ConfigChannel>
80017ee: 4603 mov r3, r0
80017f0: 2b00 cmp r3, #0
80017f2: d001 beq.n 80017f8 <MX_TIM1_Init+0x110>
{
Error_Handler();
80017f4: f7ff fdbb bl 800136e <Error_Handler>
}
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
80017f8: f107 0324 add.w r3, r7, #36 @ 0x24
80017fc: 2208 movs r2, #8
80017fe: 4619 mov r1, r3
8001800: 4813 ldr r0, [pc, #76] @ (8001850 <MX_TIM1_Init+0x168>)
8001802: f003 f88b bl 800491c <HAL_TIM_PWM_ConfigChannel>
8001806: 4603 mov r3, r0
8001808: 2b00 cmp r3, #0
800180a: d001 beq.n 8001810 <MX_TIM1_Init+0x128>
{
Error_Handler();
800180c: f7ff fdaf bl 800136e <Error_Handler>
}
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
8001810: 2300 movs r3, #0
8001812: 607b str r3, [r7, #4]
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
8001814: 2300 movs r3, #0
8001816: 60bb str r3, [r7, #8]
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
8001818: 2300 movs r3, #0
800181a: 60fb str r3, [r7, #12]
sBreakDeadTimeConfig.DeadTime = 0;
800181c: 2300 movs r3, #0
800181e: 613b str r3, [r7, #16]
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
8001820: 2300 movs r3, #0
8001822: 617b str r3, [r7, #20]
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
8001824: f44f 5300 mov.w r3, #8192 @ 0x2000
8001828: 61bb str r3, [r7, #24]
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
800182a: 2300 movs r3, #0
800182c: 623b str r3, [r7, #32]
if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
800182e: 1d3b adds r3, r7, #4
8001830: 4619 mov r1, r3
8001832: 4807 ldr r0, [pc, #28] @ (8001850 <MX_TIM1_Init+0x168>)
8001834: f003 fd96 bl 8005364 <HAL_TIMEx_ConfigBreakDeadTime>
8001838: 4603 mov r3, r0
800183a: 2b00 cmp r3, #0
800183c: d001 beq.n 8001842 <MX_TIM1_Init+0x15a>
{
Error_Handler();
800183e: f7ff fd96 bl 800136e <Error_Handler>
}
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
HAL_TIM_MspPostInit(&htim1);
8001842: 4803 ldr r0, [pc, #12] @ (8001850 <MX_TIM1_Init+0x168>)
8001844: f000 f8f6 bl 8001a34 <HAL_TIM_MspPostInit>
}
8001848: bf00 nop
800184a: 3758 adds r7, #88 @ 0x58
800184c: 46bd mov sp, r7
800184e: bd80 pop {r7, pc}
8001850: 20000188 .word 0x20000188
8001854: 40010000 .word 0x40010000
08001858 <MX_TIM3_Init>:
/* TIM3 init function */
void MX_TIM3_Init(void)
{
8001858: b580 push {r7, lr}
800185a: b086 sub sp, #24
800185c: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
800185e: f107 0308 add.w r3, r7, #8
8001862: 2200 movs r2, #0
8001864: 601a str r2, [r3, #0]
8001866: 605a str r2, [r3, #4]
8001868: 609a str r2, [r3, #8]
800186a: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
800186c: 463b mov r3, r7
800186e: 2200 movs r2, #0
8001870: 601a str r2, [r3, #0]
8001872: 605a str r2, [r3, #4]
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
8001874: 4b1c ldr r3, [pc, #112] @ (80018e8 <MX_TIM3_Init+0x90>)
8001876: 4a1d ldr r2, [pc, #116] @ (80018ec <MX_TIM3_Init+0x94>)
8001878: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 89;
800187a: 4b1b ldr r3, [pc, #108] @ (80018e8 <MX_TIM3_Init+0x90>)
800187c: 2259 movs r2, #89 @ 0x59
800187e: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
8001880: 4b19 ldr r3, [pc, #100] @ (80018e8 <MX_TIM3_Init+0x90>)
8001882: 2200 movs r2, #0
8001884: 609a str r2, [r3, #8]
htim3.Init.Period = 99;
8001886: 4b18 ldr r3, [pc, #96] @ (80018e8 <MX_TIM3_Init+0x90>)
8001888: 2263 movs r2, #99 @ 0x63
800188a: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
800188c: 4b16 ldr r3, [pc, #88] @ (80018e8 <MX_TIM3_Init+0x90>)
800188e: 2200 movs r2, #0
8001890: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8001892: 4b15 ldr r3, [pc, #84] @ (80018e8 <MX_TIM3_Init+0x90>)
8001894: 2200 movs r2, #0
8001896: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
8001898: 4813 ldr r0, [pc, #76] @ (80018e8 <MX_TIM3_Init+0x90>)
800189a: f002 fe35 bl 8004508 <HAL_TIM_Base_Init>
800189e: 4603 mov r3, r0
80018a0: 2b00 cmp r3, #0
80018a2: d001 beq.n 80018a8 <MX_TIM3_Init+0x50>
{
Error_Handler();
80018a4: f7ff fd63 bl 800136e <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
80018a8: f44f 5380 mov.w r3, #4096 @ 0x1000
80018ac: 60bb str r3, [r7, #8]
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
80018ae: f107 0308 add.w r3, r7, #8
80018b2: 4619 mov r1, r3
80018b4: 480c ldr r0, [pc, #48] @ (80018e8 <MX_TIM3_Init+0x90>)
80018b6: f003 f8f3 bl 8004aa0 <HAL_TIM_ConfigClockSource>
80018ba: 4603 mov r3, r0
80018bc: 2b00 cmp r3, #0
80018be: d001 beq.n 80018c4 <MX_TIM3_Init+0x6c>
{
Error_Handler();
80018c0: f7ff fd55 bl 800136e <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
80018c4: 2300 movs r3, #0
80018c6: 603b str r3, [r7, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
80018c8: 2300 movs r3, #0
80018ca: 607b str r3, [r7, #4]
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
80018cc: 463b mov r3, r7
80018ce: 4619 mov r1, r3
80018d0: 4805 ldr r0, [pc, #20] @ (80018e8 <MX_TIM3_Init+0x90>)
80018d2: f003 fccb bl 800526c <HAL_TIMEx_MasterConfigSynchronization>
80018d6: 4603 mov r3, r0
80018d8: 2b00 cmp r3, #0
80018da: d001 beq.n 80018e0 <MX_TIM3_Init+0x88>
{
Error_Handler();
80018dc: f7ff fd47 bl 800136e <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
}
80018e0: bf00 nop
80018e2: 3718 adds r7, #24
80018e4: 46bd mov sp, r7
80018e6: bd80 pop {r7, pc}
80018e8: 200001d0 .word 0x200001d0
80018ec: 40000400 .word 0x40000400
080018f0 <MX_TIM5_Init>:
/* TIM5 init function */
void MX_TIM5_Init(void)
{
80018f0: b580 push {r7, lr}
80018f2: b086 sub sp, #24
80018f4: af00 add r7, sp, #0
/* USER CODE BEGIN TIM5_Init 0 */
/* USER CODE END TIM5_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
80018f6: f107 0308 add.w r3, r7, #8
80018fa: 2200 movs r2, #0
80018fc: 601a str r2, [r3, #0]
80018fe: 605a str r2, [r3, #4]
8001900: 609a str r2, [r3, #8]
8001902: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8001904: 463b mov r3, r7
8001906: 2200 movs r2, #0
8001908: 601a str r2, [r3, #0]
800190a: 605a str r2, [r3, #4]
/* USER CODE BEGIN TIM5_Init 1 */
/* USER CODE END TIM5_Init 1 */
htim5.Instance = TIM5;
800190c: 4b1d ldr r3, [pc, #116] @ (8001984 <MX_TIM5_Init+0x94>)
800190e: 4a1e ldr r2, [pc, #120] @ (8001988 <MX_TIM5_Init+0x98>)
8001910: 601a str r2, [r3, #0]
htim5.Init.Prescaler = 0;
8001912: 4b1c ldr r3, [pc, #112] @ (8001984 <MX_TIM5_Init+0x94>)
8001914: 2200 movs r2, #0
8001916: 605a str r2, [r3, #4]
htim5.Init.CounterMode = TIM_COUNTERMODE_UP;
8001918: 4b1a ldr r3, [pc, #104] @ (8001984 <MX_TIM5_Init+0x94>)
800191a: 2200 movs r2, #0
800191c: 609a str r2, [r3, #8]
htim5.Init.Period = 4294967295;
800191e: 4b19 ldr r3, [pc, #100] @ (8001984 <MX_TIM5_Init+0x94>)
8001920: f04f 32ff mov.w r2, #4294967295
8001924: 60da str r2, [r3, #12]
htim5.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001926: 4b17 ldr r3, [pc, #92] @ (8001984 <MX_TIM5_Init+0x94>)
8001928: 2200 movs r2, #0
800192a: 611a str r2, [r3, #16]
htim5.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
800192c: 4b15 ldr r3, [pc, #84] @ (8001984 <MX_TIM5_Init+0x94>)
800192e: 2200 movs r2, #0
8001930: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim5) != HAL_OK)
8001932: 4814 ldr r0, [pc, #80] @ (8001984 <MX_TIM5_Init+0x94>)
8001934: f002 fde8 bl 8004508 <HAL_TIM_Base_Init>
8001938: 4603 mov r3, r0
800193a: 2b00 cmp r3, #0
800193c: d001 beq.n 8001942 <MX_TIM5_Init+0x52>
{
Error_Handler();
800193e: f7ff fd16 bl 800136e <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8001942: f44f 5380 mov.w r3, #4096 @ 0x1000
8001946: 60bb str r3, [r7, #8]
if (HAL_TIM_ConfigClockSource(&htim5, &sClockSourceConfig) != HAL_OK)
8001948: f107 0308 add.w r3, r7, #8
800194c: 4619 mov r1, r3
800194e: 480d ldr r0, [pc, #52] @ (8001984 <MX_TIM5_Init+0x94>)
8001950: f003 f8a6 bl 8004aa0 <HAL_TIM_ConfigClockSource>
8001954: 4603 mov r3, r0
8001956: 2b00 cmp r3, #0
8001958: d001 beq.n 800195e <MX_TIM5_Init+0x6e>
{
Error_Handler();
800195a: f7ff fd08 bl 800136e <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
800195e: 2300 movs r3, #0
8001960: 603b str r3, [r7, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8001962: 2300 movs r3, #0
8001964: 607b str r3, [r7, #4]
if (HAL_TIMEx_MasterConfigSynchronization(&htim5, &sMasterConfig) != HAL_OK)
8001966: 463b mov r3, r7
8001968: 4619 mov r1, r3
800196a: 4806 ldr r0, [pc, #24] @ (8001984 <MX_TIM5_Init+0x94>)
800196c: f003 fc7e bl 800526c <HAL_TIMEx_MasterConfigSynchronization>
8001970: 4603 mov r3, r0
8001972: 2b00 cmp r3, #0
8001974: d001 beq.n 800197a <MX_TIM5_Init+0x8a>
{
Error_Handler();
8001976: f7ff fcfa bl 800136e <Error_Handler>
}
/* USER CODE BEGIN TIM5_Init 2 */
/* USER CODE END TIM5_Init 2 */
}
800197a: bf00 nop
800197c: 3718 adds r7, #24
800197e: 46bd mov sp, r7
8001980: bd80 pop {r7, pc}
8001982: bf00 nop
8001984: 20000218 .word 0x20000218
8001988: 40000c00 .word 0x40000c00
0800198c <HAL_TIM_Base_MspInit>:
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
{
800198c: b580 push {r7, lr}
800198e: b086 sub sp, #24
8001990: af00 add r7, sp, #0
8001992: 6078 str r0, [r7, #4]
if(tim_baseHandle->Instance==TIM1)
8001994: 687b ldr r3, [r7, #4]
8001996: 681b ldr r3, [r3, #0]
8001998: 4a22 ldr r2, [pc, #136] @ (8001a24 <HAL_TIM_Base_MspInit+0x98>)
800199a: 4293 cmp r3, r2
800199c: d10e bne.n 80019bc <HAL_TIM_Base_MspInit+0x30>
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* TIM1 clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
800199e: 2300 movs r3, #0
80019a0: 617b str r3, [r7, #20]
80019a2: 4b21 ldr r3, [pc, #132] @ (8001a28 <HAL_TIM_Base_MspInit+0x9c>)
80019a4: 6c5b ldr r3, [r3, #68] @ 0x44
80019a6: 4a20 ldr r2, [pc, #128] @ (8001a28 <HAL_TIM_Base_MspInit+0x9c>)
80019a8: f043 0301 orr.w r3, r3, #1
80019ac: 6453 str r3, [r2, #68] @ 0x44
80019ae: 4b1e ldr r3, [pc, #120] @ (8001a28 <HAL_TIM_Base_MspInit+0x9c>)
80019b0: 6c5b ldr r3, [r3, #68] @ 0x44
80019b2: f003 0301 and.w r3, r3, #1
80019b6: 617b str r3, [r7, #20]
80019b8: 697b ldr r3, [r7, #20]
__HAL_RCC_TIM5_CLK_ENABLE();
/* USER CODE BEGIN TIM5_MspInit 1 */
/* USER CODE END TIM5_MspInit 1 */
}
}
80019ba: e02e b.n 8001a1a <HAL_TIM_Base_MspInit+0x8e>
else if(tim_baseHandle->Instance==TIM3)
80019bc: 687b ldr r3, [r7, #4]
80019be: 681b ldr r3, [r3, #0]
80019c0: 4a1a ldr r2, [pc, #104] @ (8001a2c <HAL_TIM_Base_MspInit+0xa0>)
80019c2: 4293 cmp r3, r2
80019c4: d116 bne.n 80019f4 <HAL_TIM_Base_MspInit+0x68>
__HAL_RCC_TIM3_CLK_ENABLE();
80019c6: 2300 movs r3, #0
80019c8: 613b str r3, [r7, #16]
80019ca: 4b17 ldr r3, [pc, #92] @ (8001a28 <HAL_TIM_Base_MspInit+0x9c>)
80019cc: 6c1b ldr r3, [r3, #64] @ 0x40
80019ce: 4a16 ldr r2, [pc, #88] @ (8001a28 <HAL_TIM_Base_MspInit+0x9c>)
80019d0: f043 0302 orr.w r3, r3, #2
80019d4: 6413 str r3, [r2, #64] @ 0x40
80019d6: 4b14 ldr r3, [pc, #80] @ (8001a28 <HAL_TIM_Base_MspInit+0x9c>)
80019d8: 6c1b ldr r3, [r3, #64] @ 0x40
80019da: f003 0302 and.w r3, r3, #2
80019de: 613b str r3, [r7, #16]
80019e0: 693b ldr r3, [r7, #16]
HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0);
80019e2: 2200 movs r2, #0
80019e4: 2100 movs r1, #0
80019e6: 201d movs r0, #29
80019e8: f001 f8d8 bl 8002b9c <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM3_IRQn);
80019ec: 201d movs r0, #29
80019ee: f001 f8f1 bl 8002bd4 <HAL_NVIC_EnableIRQ>
}
80019f2: e012 b.n 8001a1a <HAL_TIM_Base_MspInit+0x8e>
else if(tim_baseHandle->Instance==TIM5)
80019f4: 687b ldr r3, [r7, #4]
80019f6: 681b ldr r3, [r3, #0]
80019f8: 4a0d ldr r2, [pc, #52] @ (8001a30 <HAL_TIM_Base_MspInit+0xa4>)
80019fa: 4293 cmp r3, r2
80019fc: d10d bne.n 8001a1a <HAL_TIM_Base_MspInit+0x8e>
__HAL_RCC_TIM5_CLK_ENABLE();
80019fe: 2300 movs r3, #0
8001a00: 60fb str r3, [r7, #12]
8001a02: 4b09 ldr r3, [pc, #36] @ (8001a28 <HAL_TIM_Base_MspInit+0x9c>)
8001a04: 6c1b ldr r3, [r3, #64] @ 0x40
8001a06: 4a08 ldr r2, [pc, #32] @ (8001a28 <HAL_TIM_Base_MspInit+0x9c>)
8001a08: f043 0308 orr.w r3, r3, #8
8001a0c: 6413 str r3, [r2, #64] @ 0x40
8001a0e: 4b06 ldr r3, [pc, #24] @ (8001a28 <HAL_TIM_Base_MspInit+0x9c>)
8001a10: 6c1b ldr r3, [r3, #64] @ 0x40
8001a12: f003 0308 and.w r3, r3, #8
8001a16: 60fb str r3, [r7, #12]
8001a18: 68fb ldr r3, [r7, #12]
}
8001a1a: bf00 nop
8001a1c: 3718 adds r7, #24
8001a1e: 46bd mov sp, r7
8001a20: bd80 pop {r7, pc}
8001a22: bf00 nop
8001a24: 40010000 .word 0x40010000
8001a28: 40023800 .word 0x40023800
8001a2c: 40000400 .word 0x40000400
8001a30: 40000c00 .word 0x40000c00
08001a34 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle)
{
8001a34: b580 push {r7, lr}
8001a36: b088 sub sp, #32
8001a38: af00 add r7, sp, #0
8001a3a: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001a3c: f107 030c add.w r3, r7, #12
8001a40: 2200 movs r2, #0
8001a42: 601a str r2, [r3, #0]
8001a44: 605a str r2, [r3, #4]
8001a46: 609a str r2, [r3, #8]
8001a48: 60da str r2, [r3, #12]
8001a4a: 611a str r2, [r3, #16]
if(timHandle->Instance==TIM1)
8001a4c: 687b ldr r3, [r7, #4]
8001a4e: 681b ldr r3, [r3, #0]
8001a50: 4a12 ldr r2, [pc, #72] @ (8001a9c <HAL_TIM_MspPostInit+0x68>)
8001a52: 4293 cmp r3, r2
8001a54: d11e bne.n 8001a94 <HAL_TIM_MspPostInit+0x60>
{
/* USER CODE BEGIN TIM1_MspPostInit 0 */
/* USER CODE END TIM1_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
8001a56: 2300 movs r3, #0
8001a58: 60bb str r3, [r7, #8]
8001a5a: 4b11 ldr r3, [pc, #68] @ (8001aa0 <HAL_TIM_MspPostInit+0x6c>)
8001a5c: 6b1b ldr r3, [r3, #48] @ 0x30
8001a5e: 4a10 ldr r2, [pc, #64] @ (8001aa0 <HAL_TIM_MspPostInit+0x6c>)
8001a60: f043 0301 orr.w r3, r3, #1
8001a64: 6313 str r3, [r2, #48] @ 0x30
8001a66: 4b0e ldr r3, [pc, #56] @ (8001aa0 <HAL_TIM_MspPostInit+0x6c>)
8001a68: 6b1b ldr r3, [r3, #48] @ 0x30
8001a6a: f003 0301 and.w r3, r3, #1
8001a6e: 60bb str r3, [r7, #8]
8001a70: 68bb ldr r3, [r7, #8]
/**TIM1 GPIO Configuration
PA8 ------> TIM1_CH1
PA9 ------> TIM1_CH2
PA10 ------> TIM1_CH3
*/
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10;
8001a72: f44f 63e0 mov.w r3, #1792 @ 0x700
8001a76: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001a78: 2302 movs r3, #2
8001a7a: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001a7c: 2300 movs r3, #0
8001a7e: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001a80: 2300 movs r3, #0
8001a82: 61bb str r3, [r7, #24]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;
8001a84: 2301 movs r3, #1
8001a86: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8001a88: f107 030c add.w r3, r7, #12
8001a8c: 4619 mov r1, r3
8001a8e: 4805 ldr r0, [pc, #20] @ (8001aa4 <HAL_TIM_MspPostInit+0x70>)
8001a90: f001 fb86 bl 80031a0 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM1_MspPostInit 1 */
/* USER CODE END TIM1_MspPostInit 1 */
}
}
8001a94: bf00 nop
8001a96: 3720 adds r7, #32
8001a98: 46bd mov sp, r7
8001a9a: bd80 pop {r7, pc}
8001a9c: 40010000 .word 0x40010000
8001aa0: 40023800 .word 0x40023800
8001aa4: 40020000 .word 0x40020000
08001aa8 <MX_USART1_UART_Init>:
UART_HandleTypeDef huart1;
/* USART1 init function */
void MX_USART1_UART_Init(void)
{
8001aa8: b580 push {r7, lr}
8001aaa: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
8001aac: 4b11 ldr r3, [pc, #68] @ (8001af4 <MX_USART1_UART_Init+0x4c>)
8001aae: 4a12 ldr r2, [pc, #72] @ (8001af8 <MX_USART1_UART_Init+0x50>)
8001ab0: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 115200;
8001ab2: 4b10 ldr r3, [pc, #64] @ (8001af4 <MX_USART1_UART_Init+0x4c>)
8001ab4: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8001ab8: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
8001aba: 4b0e ldr r3, [pc, #56] @ (8001af4 <MX_USART1_UART_Init+0x4c>)
8001abc: 2200 movs r2, #0
8001abe: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8001ac0: 4b0c ldr r3, [pc, #48] @ (8001af4 <MX_USART1_UART_Init+0x4c>)
8001ac2: 2200 movs r2, #0
8001ac4: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
8001ac6: 4b0b ldr r3, [pc, #44] @ (8001af4 <MX_USART1_UART_Init+0x4c>)
8001ac8: 2200 movs r2, #0
8001aca: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
8001acc: 4b09 ldr r3, [pc, #36] @ (8001af4 <MX_USART1_UART_Init+0x4c>)
8001ace: 220c movs r2, #12
8001ad0: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8001ad2: 4b08 ldr r3, [pc, #32] @ (8001af4 <MX_USART1_UART_Init+0x4c>)
8001ad4: 2200 movs r2, #0
8001ad6: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
8001ad8: 4b06 ldr r3, [pc, #24] @ (8001af4 <MX_USART1_UART_Init+0x4c>)
8001ada: 2200 movs r2, #0
8001adc: 61da str r2, [r3, #28]
if (HAL_UART_Init(&huart1) != HAL_OK)
8001ade: 4805 ldr r0, [pc, #20] @ (8001af4 <MX_USART1_UART_Init+0x4c>)
8001ae0: f003 fca6 bl 8005430 <HAL_UART_Init>
8001ae4: 4603 mov r3, r0
8001ae6: 2b00 cmp r3, #0
8001ae8: d001 beq.n 8001aee <MX_USART1_UART_Init+0x46>
{
Error_Handler();
8001aea: f7ff fc40 bl 800136e <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
8001aee: bf00 nop
8001af0: bd80 pop {r7, pc}
8001af2: bf00 nop
8001af4: 20000260 .word 0x20000260
8001af8: 40011000 .word 0x40011000
08001afc <HAL_UART_MspInit>:
void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
{
8001afc: b580 push {r7, lr}
8001afe: b08a sub sp, #40 @ 0x28
8001b00: af00 add r7, sp, #0
8001b02: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001b04: f107 0314 add.w r3, r7, #20
8001b08: 2200 movs r2, #0
8001b0a: 601a str r2, [r3, #0]
8001b0c: 605a str r2, [r3, #4]
8001b0e: 609a str r2, [r3, #8]
8001b10: 60da str r2, [r3, #12]
8001b12: 611a str r2, [r3, #16]
if(uartHandle->Instance==USART1)
8001b14: 687b ldr r3, [r7, #4]
8001b16: 681b ldr r3, [r3, #0]
8001b18: 4a19 ldr r2, [pc, #100] @ (8001b80 <HAL_UART_MspInit+0x84>)
8001b1a: 4293 cmp r3, r2
8001b1c: d12b bne.n 8001b76 <HAL_UART_MspInit+0x7a>
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/* USART1 clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
8001b1e: 2300 movs r3, #0
8001b20: 613b str r3, [r7, #16]
8001b22: 4b18 ldr r3, [pc, #96] @ (8001b84 <HAL_UART_MspInit+0x88>)
8001b24: 6c5b ldr r3, [r3, #68] @ 0x44
8001b26: 4a17 ldr r2, [pc, #92] @ (8001b84 <HAL_UART_MspInit+0x88>)
8001b28: f043 0310 orr.w r3, r3, #16
8001b2c: 6453 str r3, [r2, #68] @ 0x44
8001b2e: 4b15 ldr r3, [pc, #84] @ (8001b84 <HAL_UART_MspInit+0x88>)
8001b30: 6c5b ldr r3, [r3, #68] @ 0x44
8001b32: f003 0310 and.w r3, r3, #16
8001b36: 613b str r3, [r7, #16]
8001b38: 693b ldr r3, [r7, #16]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001b3a: 2300 movs r3, #0
8001b3c: 60fb str r3, [r7, #12]
8001b3e: 4b11 ldr r3, [pc, #68] @ (8001b84 <HAL_UART_MspInit+0x88>)
8001b40: 6b1b ldr r3, [r3, #48] @ 0x30
8001b42: 4a10 ldr r2, [pc, #64] @ (8001b84 <HAL_UART_MspInit+0x88>)
8001b44: f043 0302 orr.w r3, r3, #2
8001b48: 6313 str r3, [r2, #48] @ 0x30
8001b4a: 4b0e ldr r3, [pc, #56] @ (8001b84 <HAL_UART_MspInit+0x88>)
8001b4c: 6b1b ldr r3, [r3, #48] @ 0x30
8001b4e: f003 0302 and.w r3, r3, #2
8001b52: 60fb str r3, [r7, #12]
8001b54: 68fb ldr r3, [r7, #12]
/**USART1 GPIO Configuration
PB6 ------> USART1_TX
PB7 ------> USART1_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
8001b56: 23c0 movs r3, #192 @ 0xc0
8001b58: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001b5a: 2302 movs r3, #2
8001b5c: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b5e: 2300 movs r3, #0
8001b60: 61fb str r3, [r7, #28]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001b62: 2303 movs r3, #3
8001b64: 623b str r3, [r7, #32]
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
8001b66: 2307 movs r3, #7
8001b68: 627b str r3, [r7, #36] @ 0x24
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001b6a: f107 0314 add.w r3, r7, #20
8001b6e: 4619 mov r1, r3
8001b70: 4805 ldr r0, [pc, #20] @ (8001b88 <HAL_UART_MspInit+0x8c>)
8001b72: f001 fb15 bl 80031a0 <HAL_GPIO_Init>
/* USER CODE BEGIN USART1_MspInit 1 */
/* USER CODE END USART1_MspInit 1 */
}
}
8001b76: bf00 nop
8001b78: 3728 adds r7, #40 @ 0x28
8001b7a: 46bd mov sp, r7
8001b7c: bd80 pop {r7, pc}
8001b7e: bf00 nop
8001b80: 40011000 .word 0x40011000
8001b84: 40023800 .word 0x40023800
8001b88: 40020400 .word 0x40020400
08001b8c <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr sp, =_estack /* set stack pointer */
8001b8c: f8df d034 ldr.w sp, [pc, #52] @ 8001bc4 <LoopFillZerobss+0xe>
/* Call the clock system initialization function.*/
bl SystemInit
8001b90: f7ff fd98 bl 80016c4 <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
8001b94: 480c ldr r0, [pc, #48] @ (8001bc8 <LoopFillZerobss+0x12>)
ldr r1, =_edata
8001b96: 490d ldr r1, [pc, #52] @ (8001bcc <LoopFillZerobss+0x16>)
ldr r2, =_sidata
8001b98: 4a0d ldr r2, [pc, #52] @ (8001bd0 <LoopFillZerobss+0x1a>)
movs r3, #0
8001b9a: 2300 movs r3, #0
b LoopCopyDataInit
8001b9c: e002 b.n 8001ba4 <LoopCopyDataInit>
08001b9e <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
8001b9e: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
8001ba0: 50c4 str r4, [r0, r3]
adds r3, r3, #4
8001ba2: 3304 adds r3, #4
08001ba4 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
8001ba4: 18c4 adds r4, r0, r3
cmp r4, r1
8001ba6: 428c cmp r4, r1
bcc CopyDataInit
8001ba8: d3f9 bcc.n 8001b9e <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
8001baa: 4a0a ldr r2, [pc, #40] @ (8001bd4 <LoopFillZerobss+0x1e>)
ldr r4, =_ebss
8001bac: 4c0a ldr r4, [pc, #40] @ (8001bd8 <LoopFillZerobss+0x22>)
movs r3, #0
8001bae: 2300 movs r3, #0
b LoopFillZerobss
8001bb0: e001 b.n 8001bb6 <LoopFillZerobss>
08001bb2 <FillZerobss>:
FillZerobss:
str r3, [r2]
8001bb2: 6013 str r3, [r2, #0]
adds r2, r2, #4
8001bb4: 3204 adds r2, #4
08001bb6 <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
8001bb6: 42a2 cmp r2, r4
bcc FillZerobss
8001bb8: d3fb bcc.n 8001bb2 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
8001bba: f003 ff05 bl 80059c8 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8001bbe: f7ff fab1 bl 8001124 <main>
bx lr
8001bc2: 4770 bx lr
ldr sp, =_estack /* set stack pointer */
8001bc4: 20020000 .word 0x20020000
ldr r0, =_sdata
8001bc8: 20000000 .word 0x20000000
ldr r1, =_edata
8001bcc: 20000014 .word 0x20000014
ldr r2, =_sidata
8001bd0: 08005a6c .word 0x08005a6c
ldr r2, =_sbss
8001bd4: 20000014 .word 0x20000014
ldr r4, =_ebss
8001bd8: 200002cc .word 0x200002cc
08001bdc <CAN1_RX0_IRQHandler>:
* @retval None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001bdc: e7fe b.n 8001bdc <CAN1_RX0_IRQHandler>
...
08001be0 <HAL_Init>:
* need to ensure that the SysTick time base is always set to 1 millisecond
* to have correct HAL operation.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8001be0: b580 push {r7, lr}
8001be2: af00 add r7, sp, #0
/* Configure Flash prefetch, Instruction cache, Data cache */
#if (INSTRUCTION_CACHE_ENABLE != 0U)
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
8001be4: 4b0e ldr r3, [pc, #56] @ (8001c20 <HAL_Init+0x40>)
8001be6: 681b ldr r3, [r3, #0]
8001be8: 4a0d ldr r2, [pc, #52] @ (8001c20 <HAL_Init+0x40>)
8001bea: f443 7300 orr.w r3, r3, #512 @ 0x200
8001bee: 6013 str r3, [r2, #0]
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE != 0U)
__HAL_FLASH_DATA_CACHE_ENABLE();
8001bf0: 4b0b ldr r3, [pc, #44] @ (8001c20 <HAL_Init+0x40>)
8001bf2: 681b ldr r3, [r3, #0]
8001bf4: 4a0a ldr r2, [pc, #40] @ (8001c20 <HAL_Init+0x40>)
8001bf6: f443 6380 orr.w r3, r3, #1024 @ 0x400
8001bfa: 6013 str r3, [r2, #0]
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
8001bfc: 4b08 ldr r3, [pc, #32] @ (8001c20 <HAL_Init+0x40>)
8001bfe: 681b ldr r3, [r3, #0]
8001c00: 4a07 ldr r2, [pc, #28] @ (8001c20 <HAL_Init+0x40>)
8001c02: f443 7380 orr.w r3, r3, #256 @ 0x100
8001c06: 6013 str r3, [r2, #0]
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8001c08: 2003 movs r0, #3
8001c0a: f000 ffbc bl 8002b86 <HAL_NVIC_SetPriorityGrouping>
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
8001c0e: 200f movs r0, #15
8001c10: f7ff fc84 bl 800151c <HAL_InitTick>
/* Init the low level hardware */
HAL_MspInit();
8001c14: f7ff fc5a bl 80014cc <HAL_MspInit>
/* Return function status */
return HAL_OK;
8001c18: 2300 movs r3, #0
}
8001c1a: 4618 mov r0, r3
8001c1c: bd80 pop {r7, pc}
8001c1e: bf00 nop
8001c20: 40023c00 .word 0x40023c00
08001c24 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001c24: b480 push {r7}
8001c26: af00 add r7, sp, #0
uwTick += uwTickFreq;
8001c28: 4b06 ldr r3, [pc, #24] @ (8001c44 <HAL_IncTick+0x20>)
8001c2a: 781b ldrb r3, [r3, #0]
8001c2c: 461a mov r2, r3
8001c2e: 4b06 ldr r3, [pc, #24] @ (8001c48 <HAL_IncTick+0x24>)
8001c30: 681b ldr r3, [r3, #0]
8001c32: 4413 add r3, r2
8001c34: 4a04 ldr r2, [pc, #16] @ (8001c48 <HAL_IncTick+0x24>)
8001c36: 6013 str r3, [r2, #0]
}
8001c38: bf00 nop
8001c3a: 46bd mov sp, r7
8001c3c: f85d 7b04 ldr.w r7, [sp], #4
8001c40: 4770 bx lr
8001c42: bf00 nop
8001c44: 20000010 .word 0x20000010
8001c48: 200002a8 .word 0x200002a8
08001c4c <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8001c4c: b480 push {r7}
8001c4e: af00 add r7, sp, #0
return uwTick;
8001c50: 4b03 ldr r3, [pc, #12] @ (8001c60 <HAL_GetTick+0x14>)
8001c52: 681b ldr r3, [r3, #0]
}
8001c54: 4618 mov r0, r3
8001c56: 46bd mov sp, r7
8001c58: f85d 7b04 ldr.w r7, [sp], #4
8001c5c: 4770 bx lr
8001c5e: bf00 nop
8001c60: 200002a8 .word 0x200002a8
08001c64 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8001c64: b580 push {r7, lr}
8001c66: b084 sub sp, #16
8001c68: af00 add r7, sp, #0
8001c6a: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8001c6c: f7ff ffee bl 8001c4c <HAL_GetTick>
8001c70: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8001c72: 687b ldr r3, [r7, #4]
8001c74: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
8001c76: 68fb ldr r3, [r7, #12]
8001c78: f1b3 3fff cmp.w r3, #4294967295
8001c7c: d005 beq.n 8001c8a <HAL_Delay+0x26>
{
wait += (uint32_t)(uwTickFreq);
8001c7e: 4b0a ldr r3, [pc, #40] @ (8001ca8 <HAL_Delay+0x44>)
8001c80: 781b ldrb r3, [r3, #0]
8001c82: 461a mov r2, r3
8001c84: 68fb ldr r3, [r7, #12]
8001c86: 4413 add r3, r2
8001c88: 60fb str r3, [r7, #12]
}
while((HAL_GetTick() - tickstart) < wait)
8001c8a: bf00 nop
8001c8c: f7ff ffde bl 8001c4c <HAL_GetTick>
8001c90: 4602 mov r2, r0
8001c92: 68bb ldr r3, [r7, #8]
8001c94: 1ad3 subs r3, r2, r3
8001c96: 68fa ldr r2, [r7, #12]
8001c98: 429a cmp r2, r3
8001c9a: d8f7 bhi.n 8001c8c <HAL_Delay+0x28>
{
}
}
8001c9c: bf00 nop
8001c9e: bf00 nop
8001ca0: 3710 adds r7, #16
8001ca2: 46bd mov sp, r7
8001ca4: bd80 pop {r7, pc}
8001ca6: bf00 nop
8001ca8: 20000010 .word 0x20000010
08001cac <HAL_ADC_Init>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
{
8001cac: b580 push {r7, lr}
8001cae: b084 sub sp, #16
8001cb0: af00 add r7, sp, #0
8001cb2: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8001cb4: 2300 movs r3, #0
8001cb6: 73fb strb r3, [r7, #15]
/* Check ADC handle */
if (hadc == NULL)
8001cb8: 687b ldr r3, [r7, #4]
8001cba: 2b00 cmp r3, #0
8001cbc: d101 bne.n 8001cc2 <HAL_ADC_Init+0x16>
{
return HAL_ERROR;
8001cbe: 2301 movs r3, #1
8001cc0: e033 b.n 8001d2a <HAL_ADC_Init+0x7e>
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
{
assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
}
if (hadc->State == HAL_ADC_STATE_RESET)
8001cc2: 687b ldr r3, [r7, #4]
8001cc4: 6c1b ldr r3, [r3, #64] @ 0x40
8001cc6: 2b00 cmp r3, #0
8001cc8: d109 bne.n 8001cde <HAL_ADC_Init+0x32>
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
8001cca: 6878 ldr r0, [r7, #4]
8001ccc: f7fe fc80 bl 80005d0 <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Initialize ADC error code */
ADC_CLEAR_ERRORCODE(hadc);
8001cd0: 687b ldr r3, [r7, #4]
8001cd2: 2200 movs r2, #0
8001cd4: 645a str r2, [r3, #68] @ 0x44
/* Allocate lock resource and initialize it */
hadc->Lock = HAL_UNLOCKED;
8001cd6: 687b ldr r3, [r7, #4]
8001cd8: 2200 movs r2, #0
8001cda: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed. */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
8001cde: 687b ldr r3, [r7, #4]
8001ce0: 6c1b ldr r3, [r3, #64] @ 0x40
8001ce2: f003 0310 and.w r3, r3, #16
8001ce6: 2b00 cmp r3, #0
8001ce8: d118 bne.n 8001d1c <HAL_ADC_Init+0x70>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8001cea: 687b ldr r3, [r7, #4]
8001cec: 6c1b ldr r3, [r3, #64] @ 0x40
8001cee: f423 5388 bic.w r3, r3, #4352 @ 0x1100
8001cf2: f023 0302 bic.w r3, r3, #2
8001cf6: f043 0202 orr.w r2, r3, #2
8001cfa: 687b ldr r3, [r7, #4]
8001cfc: 641a str r2, [r3, #64] @ 0x40
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
/* Set ADC parameters */
ADC_Init(hadc);
8001cfe: 6878 ldr r0, [r7, #4]
8001d00: f000 fa78 bl 80021f4 <ADC_Init>
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8001d04: 687b ldr r3, [r7, #4]
8001d06: 2200 movs r2, #0
8001d08: 645a str r2, [r3, #68] @ 0x44
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
8001d0a: 687b ldr r3, [r7, #4]
8001d0c: 6c1b ldr r3, [r3, #64] @ 0x40
8001d0e: f023 0303 bic.w r3, r3, #3
8001d12: f043 0201 orr.w r2, r3, #1
8001d16: 687b ldr r3, [r7, #4]
8001d18: 641a str r2, [r3, #64] @ 0x40
8001d1a: e001 b.n 8001d20 <HAL_ADC_Init+0x74>
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_READY);
}
else
{
tmp_hal_status = HAL_ERROR;
8001d1c: 2301 movs r3, #1
8001d1e: 73fb strb r3, [r7, #15]
}
/* Release Lock */
__HAL_UNLOCK(hadc);
8001d20: 687b ldr r3, [r7, #4]
8001d22: 2200 movs r2, #0
8001d24: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Return function status */
return tmp_hal_status;
8001d28: 7bfb ldrb r3, [r7, #15]
}
8001d2a: 4618 mov r0, r3
8001d2c: 3710 adds r7, #16
8001d2e: 46bd mov sp, r7
8001d30: bd80 pop {r7, pc}
08001d32 <HAL_ADC_IRQHandler>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
{
8001d32: b580 push {r7, lr}
8001d34: b086 sub sp, #24
8001d36: af00 add r7, sp, #0
8001d38: 6078 str r0, [r7, #4]
uint32_t tmp1 = 0U, tmp2 = 0U;
8001d3a: 2300 movs r3, #0
8001d3c: 617b str r3, [r7, #20]
8001d3e: 2300 movs r3, #0
8001d40: 613b str r3, [r7, #16]
uint32_t tmp_sr = hadc->Instance->SR;
8001d42: 687b ldr r3, [r7, #4]
8001d44: 681b ldr r3, [r3, #0]
8001d46: 681b ldr r3, [r3, #0]
8001d48: 60fb str r3, [r7, #12]
uint32_t tmp_cr1 = hadc->Instance->CR1;
8001d4a: 687b ldr r3, [r7, #4]
8001d4c: 681b ldr r3, [r3, #0]
8001d4e: 685b ldr r3, [r3, #4]
8001d50: 60bb str r3, [r7, #8]
/* Check the parameters */
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion));
assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection));
tmp1 = tmp_sr & ADC_FLAG_EOC;
8001d52: 68fb ldr r3, [r7, #12]
8001d54: f003 0302 and.w r3, r3, #2
8001d58: 617b str r3, [r7, #20]
tmp2 = tmp_cr1 & ADC_IT_EOC;
8001d5a: 68bb ldr r3, [r7, #8]
8001d5c: f003 0320 and.w r3, r3, #32
8001d60: 613b str r3, [r7, #16]
/* Check End of conversion flag for regular channels */
if (tmp1 && tmp2)
8001d62: 697b ldr r3, [r7, #20]
8001d64: 2b00 cmp r3, #0
8001d66: d049 beq.n 8001dfc <HAL_ADC_IRQHandler+0xca>
8001d68: 693b ldr r3, [r7, #16]
8001d6a: 2b00 cmp r3, #0
8001d6c: d046 beq.n 8001dfc <HAL_ADC_IRQHandler+0xca>
{
/* Update state machine on conversion status if not in error state */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
8001d6e: 687b ldr r3, [r7, #4]
8001d70: 6c1b ldr r3, [r3, #64] @ 0x40
8001d72: f003 0310 and.w r3, r3, #16
8001d76: 2b00 cmp r3, #0
8001d78: d105 bne.n 8001d86 <HAL_ADC_IRQHandler+0x54>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
8001d7a: 687b ldr r3, [r7, #4]
8001d7c: 6c1b ldr r3, [r3, #64] @ 0x40
8001d7e: f443 7200 orr.w r2, r3, #512 @ 0x200
8001d82: 687b ldr r3, [r7, #4]
8001d84: 641a str r2, [r3, #64] @ 0x40
/* by external trigger, continuous mode or scan sequence on going. */
/* Note: On STM32F4, there is no independent flag of end of sequence. */
/* The test of scan sequence on going is done either with scan */
/* sequence disabled or with end of conversion flag set to */
/* of end of sequence. */
if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
8001d86: 687b ldr r3, [r7, #4]
8001d88: 681b ldr r3, [r3, #0]
8001d8a: 689b ldr r3, [r3, #8]
8001d8c: f003 5340 and.w r3, r3, #805306368 @ 0x30000000
8001d90: 2b00 cmp r3, #0
8001d92: d12b bne.n 8001dec <HAL_ADC_IRQHandler+0xba>
(hadc->Init.ContinuousConvMode == DISABLE) &&
8001d94: 687b ldr r3, [r7, #4]
8001d96: 7e1b ldrb r3, [r3, #24]
if (ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
8001d98: 2b00 cmp r3, #0
8001d9a: d127 bne.n 8001dec <HAL_ADC_IRQHandler+0xba>
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
8001d9c: 687b ldr r3, [r7, #4]
8001d9e: 681b ldr r3, [r3, #0]
8001da0: 6adb ldr r3, [r3, #44] @ 0x2c
8001da2: f403 0370 and.w r3, r3, #15728640 @ 0xf00000
(hadc->Init.ContinuousConvMode == DISABLE) &&
8001da6: 2b00 cmp r3, #0
8001da8: d006 beq.n 8001db8 <HAL_ADC_IRQHandler+0x86>
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)))
8001daa: 687b ldr r3, [r7, #4]
8001dac: 681b ldr r3, [r3, #0]
8001dae: 689b ldr r3, [r3, #8]
8001db0: f403 6380 and.w r3, r3, #1024 @ 0x400
(HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) ||
8001db4: 2b00 cmp r3, #0
8001db6: d119 bne.n 8001dec <HAL_ADC_IRQHandler+0xba>
{
/* Disable ADC end of single conversion interrupt on group regular */
/* Note: Overrun interrupt was enabled with EOC interrupt in */
/* HAL_ADC_Start_IT(), but is not disabled here because can be used */
/* by overrun IRQ process below. */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
8001db8: 687b ldr r3, [r7, #4]
8001dba: 681b ldr r3, [r3, #0]
8001dbc: 685a ldr r2, [r3, #4]
8001dbe: 687b ldr r3, [r7, #4]
8001dc0: 681b ldr r3, [r3, #0]
8001dc2: f022 0220 bic.w r2, r2, #32
8001dc6: 605a str r2, [r3, #4]
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
8001dc8: 687b ldr r3, [r7, #4]
8001dca: 6c1b ldr r3, [r3, #64] @ 0x40
8001dcc: f423 7280 bic.w r2, r3, #256 @ 0x100
8001dd0: 687b ldr r3, [r7, #4]
8001dd2: 641a str r2, [r3, #64] @ 0x40
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY))
8001dd4: 687b ldr r3, [r7, #4]
8001dd6: 6c1b ldr r3, [r3, #64] @ 0x40
8001dd8: f403 5380 and.w r3, r3, #4096 @ 0x1000
8001ddc: 2b00 cmp r3, #0
8001dde: d105 bne.n 8001dec <HAL_ADC_IRQHandler+0xba>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
8001de0: 687b ldr r3, [r7, #4]
8001de2: 6c1b ldr r3, [r3, #64] @ 0x40
8001de4: f043 0201 orr.w r2, r3, #1
8001de8: 687b ldr r3, [r7, #4]
8001dea: 641a str r2, [r3, #64] @ 0x40
/* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvCpltCallback(hadc);
#else
HAL_ADC_ConvCpltCallback(hadc);
8001dec: 6878 ldr r0, [r7, #4]
8001dee: f000 f8b0 bl 8001f52 <HAL_ADC_ConvCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear regular group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
8001df2: 687b ldr r3, [r7, #4]
8001df4: 681b ldr r3, [r3, #0]
8001df6: f06f 0212 mvn.w r2, #18
8001dfa: 601a str r2, [r3, #0]
}
tmp1 = tmp_sr & ADC_FLAG_JEOC;
8001dfc: 68fb ldr r3, [r7, #12]
8001dfe: f003 0304 and.w r3, r3, #4
8001e02: 617b str r3, [r7, #20]
tmp2 = tmp_cr1 & ADC_IT_JEOC;
8001e04: 68bb ldr r3, [r7, #8]
8001e06: f003 0380 and.w r3, r3, #128 @ 0x80
8001e0a: 613b str r3, [r7, #16]
/* Check End of conversion flag for injected channels */
if (tmp1 && tmp2)
8001e0c: 697b ldr r3, [r7, #20]
8001e0e: 2b00 cmp r3, #0
8001e10: d057 beq.n 8001ec2 <HAL_ADC_IRQHandler+0x190>
8001e12: 693b ldr r3, [r7, #16]
8001e14: 2b00 cmp r3, #0
8001e16: d054 beq.n 8001ec2 <HAL_ADC_IRQHandler+0x190>
{
/* Update state machine on conversion status if not in error state */
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL))
8001e18: 687b ldr r3, [r7, #4]
8001e1a: 6c1b ldr r3, [r3, #64] @ 0x40
8001e1c: f003 0310 and.w r3, r3, #16
8001e20: 2b00 cmp r3, #0
8001e22: d105 bne.n 8001e30 <HAL_ADC_IRQHandler+0xfe>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
8001e24: 687b ldr r3, [r7, #4]
8001e26: 6c1b ldr r3, [r3, #64] @ 0x40
8001e28: f443 5200 orr.w r2, r3, #8192 @ 0x2000
8001e2c: 687b ldr r3, [r7, #4]
8001e2e: 641a str r2, [r3, #64] @ 0x40
/* Determine whether any further conversion upcoming on group injected */
/* by external trigger, scan sequence on going or by automatic injected */
/* conversion from group regular (same conditions as group regular */
/* interruption disabling above). */
if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
8001e30: 687b ldr r3, [r7, #4]
8001e32: 681b ldr r3, [r3, #0]
8001e34: 689b ldr r3, [r3, #8]
8001e36: f403 1340 and.w r3, r3, #3145728 @ 0x300000
8001e3a: 2b00 cmp r3, #0
8001e3c: d139 bne.n 8001eb2 <HAL_ADC_IRQHandler+0x180>
(HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
8001e3e: 687b ldr r3, [r7, #4]
8001e40: 681b ldr r3, [r3, #0]
8001e42: 6b9b ldr r3, [r3, #56] @ 0x38
8001e44: f403 1340 and.w r3, r3, #3145728 @ 0x300000
if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
8001e48: 2b00 cmp r3, #0
8001e4a: d006 beq.n 8001e5a <HAL_ADC_IRQHandler+0x128>
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) &&
8001e4c: 687b ldr r3, [r7, #4]
8001e4e: 681b ldr r3, [r3, #0]
8001e50: 689b ldr r3, [r3, #8]
8001e52: f403 6380 and.w r3, r3, #1024 @ 0x400
(HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) ||
8001e56: 2b00 cmp r3, #0
8001e58: d12b bne.n 8001eb2 <HAL_ADC_IRQHandler+0x180>
(HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
8001e5a: 687b ldr r3, [r7, #4]
8001e5c: 681b ldr r3, [r3, #0]
8001e5e: 685b ldr r3, [r3, #4]
8001e60: f403 6380 and.w r3, r3, #1024 @ 0x400
HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS)) &&
8001e64: 2b00 cmp r3, #0
8001e66: d124 bne.n 8001eb2 <HAL_ADC_IRQHandler+0x180>
(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
8001e68: 687b ldr r3, [r7, #4]
8001e6a: 681b ldr r3, [r3, #0]
8001e6c: 689b ldr r3, [r3, #8]
8001e6e: f003 5340 and.w r3, r3, #805306368 @ 0x30000000
(HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
8001e72: 2b00 cmp r3, #0
8001e74: d11d bne.n 8001eb2 <HAL_ADC_IRQHandler+0x180>
(hadc->Init.ContinuousConvMode == DISABLE))))
8001e76: 687b ldr r3, [r7, #4]
8001e78: 7e1b ldrb r3, [r3, #24]
(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
8001e7a: 2b00 cmp r3, #0
8001e7c: d119 bne.n 8001eb2 <HAL_ADC_IRQHandler+0x180>
{
/* Disable ADC end of single conversion interrupt on group injected */
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
8001e7e: 687b ldr r3, [r7, #4]
8001e80: 681b ldr r3, [r3, #0]
8001e82: 685a ldr r2, [r3, #4]
8001e84: 687b ldr r3, [r7, #4]
8001e86: 681b ldr r3, [r3, #0]
8001e88: f022 0280 bic.w r2, r2, #128 @ 0x80
8001e8c: 605a str r2, [r3, #4]
/* Set ADC state */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
8001e8e: 687b ldr r3, [r7, #4]
8001e90: 6c1b ldr r3, [r3, #64] @ 0x40
8001e92: f423 5280 bic.w r2, r3, #4096 @ 0x1000
8001e96: 687b ldr r3, [r7, #4]
8001e98: 641a str r2, [r3, #64] @ 0x40
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
8001e9a: 687b ldr r3, [r7, #4]
8001e9c: 6c1b ldr r3, [r3, #64] @ 0x40
8001e9e: f403 7380 and.w r3, r3, #256 @ 0x100
8001ea2: 2b00 cmp r3, #0
8001ea4: d105 bne.n 8001eb2 <HAL_ADC_IRQHandler+0x180>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
8001ea6: 687b ldr r3, [r7, #4]
8001ea8: 6c1b ldr r3, [r3, #64] @ 0x40
8001eaa: f043 0201 orr.w r2, r3, #1
8001eae: 687b ldr r3, [r7, #4]
8001eb0: 641a str r2, [r3, #64] @ 0x40
/* Conversion complete callback */
/* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->InjectedConvCpltCallback(hadc);
#else
HAL_ADCEx_InjectedConvCpltCallback(hadc);
8001eb2: 6878 ldr r0, [r7, #4]
8001eb4: f000 fa9a bl 80023ec <HAL_ADCEx_InjectedConvCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear injected group conversion flag */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
8001eb8: 687b ldr r3, [r7, #4]
8001eba: 681b ldr r3, [r3, #0]
8001ebc: f06f 020c mvn.w r2, #12
8001ec0: 601a str r2, [r3, #0]
}
tmp1 = tmp_sr & ADC_FLAG_AWD;
8001ec2: 68fb ldr r3, [r7, #12]
8001ec4: f003 0301 and.w r3, r3, #1
8001ec8: 617b str r3, [r7, #20]
tmp2 = tmp_cr1 & ADC_IT_AWD;
8001eca: 68bb ldr r3, [r7, #8]
8001ecc: f003 0340 and.w r3, r3, #64 @ 0x40
8001ed0: 613b str r3, [r7, #16]
/* Check Analog watchdog flag */
if (tmp1 && tmp2)
8001ed2: 697b ldr r3, [r7, #20]
8001ed4: 2b00 cmp r3, #0
8001ed6: d017 beq.n 8001f08 <HAL_ADC_IRQHandler+0x1d6>
8001ed8: 693b ldr r3, [r7, #16]
8001eda: 2b00 cmp r3, #0
8001edc: d014 beq.n 8001f08 <HAL_ADC_IRQHandler+0x1d6>
{
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
8001ede: 687b ldr r3, [r7, #4]
8001ee0: 681b ldr r3, [r3, #0]
8001ee2: 681b ldr r3, [r3, #0]
8001ee4: f003 0301 and.w r3, r3, #1
8001ee8: 2b01 cmp r3, #1
8001eea: d10d bne.n 8001f08 <HAL_ADC_IRQHandler+0x1d6>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
8001eec: 687b ldr r3, [r7, #4]
8001eee: 6c1b ldr r3, [r3, #64] @ 0x40
8001ef0: f443 3280 orr.w r2, r3, #65536 @ 0x10000
8001ef4: 687b ldr r3, [r7, #4]
8001ef6: 641a str r2, [r3, #64] @ 0x40
/* Level out of window callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->LevelOutOfWindowCallback(hadc);
#else
HAL_ADC_LevelOutOfWindowCallback(hadc);
8001ef8: 6878 ldr r0, [r7, #4]
8001efa: f000 f834 bl 8001f66 <HAL_ADC_LevelOutOfWindowCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear the ADC analog watchdog flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
8001efe: 687b ldr r3, [r7, #4]
8001f00: 681b ldr r3, [r3, #0]
8001f02: f06f 0201 mvn.w r2, #1
8001f06: 601a str r2, [r3, #0]
}
}
tmp1 = tmp_sr & ADC_FLAG_OVR;
8001f08: 68fb ldr r3, [r7, #12]
8001f0a: f003 0320 and.w r3, r3, #32
8001f0e: 617b str r3, [r7, #20]
tmp2 = tmp_cr1 & ADC_IT_OVR;
8001f10: 68bb ldr r3, [r7, #8]
8001f12: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
8001f16: 613b str r3, [r7, #16]
/* Check Overrun flag */
if (tmp1 && tmp2)
8001f18: 697b ldr r3, [r7, #20]
8001f1a: 2b00 cmp r3, #0
8001f1c: d015 beq.n 8001f4a <HAL_ADC_IRQHandler+0x218>
8001f1e: 693b ldr r3, [r7, #16]
8001f20: 2b00 cmp r3, #0
8001f22: d012 beq.n 8001f4a <HAL_ADC_IRQHandler+0x218>
/* Note: On STM32F4, ADC overrun can be set through other parameters */
/* refer to description of parameter "EOCSelection" for more */
/* details. */
/* Set ADC error code to overrun */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
8001f24: 687b ldr r3, [r7, #4]
8001f26: 6c5b ldr r3, [r3, #68] @ 0x44
8001f28: f043 0202 orr.w r2, r3, #2
8001f2c: 687b ldr r3, [r7, #4]
8001f2e: 645a str r2, [r3, #68] @ 0x44
/* Clear ADC overrun flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
8001f30: 687b ldr r3, [r7, #4]
8001f32: 681b ldr r3, [r3, #0]
8001f34: f06f 0220 mvn.w r2, #32
8001f38: 601a str r2, [r3, #0]
/* Error callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ErrorCallback(hadc);
#else
HAL_ADC_ErrorCallback(hadc);
8001f3a: 6878 ldr r0, [r7, #4]
8001f3c: f000 f81d bl 8001f7a <HAL_ADC_ErrorCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Clear the Overrun flag */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
8001f40: 687b ldr r3, [r7, #4]
8001f42: 681b ldr r3, [r3, #0]
8001f44: f06f 0220 mvn.w r2, #32
8001f48: 601a str r2, [r3, #0]
}
}
8001f4a: bf00 nop
8001f4c: 3718 adds r7, #24
8001f4e: 46bd mov sp, r7
8001f50: bd80 pop {r7, pc}
08001f52 <HAL_ADC_ConvCpltCallback>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
{
8001f52: b480 push {r7}
8001f54: b083 sub sp, #12
8001f56: af00 add r7, sp, #0
8001f58: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ADC_ConvCpltCallback could be implemented in the user file
*/
}
8001f5a: bf00 nop
8001f5c: 370c adds r7, #12
8001f5e: 46bd mov sp, r7
8001f60: f85d 7b04 ldr.w r7, [sp], #4
8001f64: 4770 bx lr
08001f66 <HAL_ADC_LevelOutOfWindowCallback>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
{
8001f66: b480 push {r7}
8001f68: b083 sub sp, #12
8001f6a: af00 add r7, sp, #0
8001f6c: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ADC_LevelOoutOfWindowCallback could be implemented in the user file
*/
}
8001f6e: bf00 nop
8001f70: 370c adds r7, #12
8001f72: 46bd mov sp, r7
8001f74: f85d 7b04 ldr.w r7, [sp], #4
8001f78: 4770 bx lr
08001f7a <HAL_ADC_ErrorCallback>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
{
8001f7a: b480 push {r7}
8001f7c: b083 sub sp, #12
8001f7e: af00 add r7, sp, #0
8001f80: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ADC_ErrorCallback could be implemented in the user file
*/
}
8001f82: bf00 nop
8001f84: 370c adds r7, #12
8001f86: 46bd mov sp, r7
8001f88: f85d 7b04 ldr.w r7, [sp], #4
8001f8c: 4770 bx lr
...
08001f90 <HAL_ADC_ConfigChannel>:
* the configuration information for the specified ADC.
* @param sConfig ADC configuration structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
{
8001f90: b480 push {r7}
8001f92: b085 sub sp, #20
8001f94: af00 add r7, sp, #0
8001f96: 6078 str r0, [r7, #4]
8001f98: 6039 str r1, [r7, #0]
__IO uint32_t counter = 0U;
8001f9a: 2300 movs r3, #0
8001f9c: 60bb str r3, [r7, #8]
assert_param(IS_ADC_CHANNEL(sConfig->Channel));
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
/* Process locked */
__HAL_LOCK(hadc);
8001f9e: 687b ldr r3, [r7, #4]
8001fa0: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8001fa4: 2b01 cmp r3, #1
8001fa6: d101 bne.n 8001fac <HAL_ADC_ConfigChannel+0x1c>
8001fa8: 2302 movs r3, #2
8001faa: e113 b.n 80021d4 <HAL_ADC_ConfigChannel+0x244>
8001fac: 687b ldr r3, [r7, #4]
8001fae: 2201 movs r2, #1
8001fb0: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* if ADC_Channel_10 ... ADC_Channel_18 is selected */
if (sConfig->Channel > ADC_CHANNEL_9)
8001fb4: 683b ldr r3, [r7, #0]
8001fb6: 681b ldr r3, [r3, #0]
8001fb8: 2b09 cmp r3, #9
8001fba: d925 bls.n 8002008 <HAL_ADC_ConfigChannel+0x78>
{
/* Clear the old sample time */
hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfig->Channel);
8001fbc: 687b ldr r3, [r7, #4]
8001fbe: 681b ldr r3, [r3, #0]
8001fc0: 68d9 ldr r1, [r3, #12]
8001fc2: 683b ldr r3, [r7, #0]
8001fc4: 681b ldr r3, [r3, #0]
8001fc6: b29b uxth r3, r3
8001fc8: 461a mov r2, r3
8001fca: 4613 mov r3, r2
8001fcc: 005b lsls r3, r3, #1
8001fce: 4413 add r3, r2
8001fd0: 3b1e subs r3, #30
8001fd2: 2207 movs r2, #7
8001fd4: fa02 f303 lsl.w r3, r2, r3
8001fd8: 43da mvns r2, r3
8001fda: 687b ldr r3, [r7, #4]
8001fdc: 681b ldr r3, [r3, #0]
8001fde: 400a ands r2, r1
8001fe0: 60da str r2, [r3, #12]
/* Set the new sample time */
hadc->Instance->SMPR1 |= ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel);
8001fe2: 687b ldr r3, [r7, #4]
8001fe4: 681b ldr r3, [r3, #0]
8001fe6: 68d9 ldr r1, [r3, #12]
8001fe8: 683b ldr r3, [r7, #0]
8001fea: 689a ldr r2, [r3, #8]
8001fec: 683b ldr r3, [r7, #0]
8001fee: 681b ldr r3, [r3, #0]
8001ff0: b29b uxth r3, r3
8001ff2: 4618 mov r0, r3
8001ff4: 4603 mov r3, r0
8001ff6: 005b lsls r3, r3, #1
8001ff8: 4403 add r3, r0
8001ffa: 3b1e subs r3, #30
8001ffc: 409a lsls r2, r3
8001ffe: 687b ldr r3, [r7, #4]
8002000: 681b ldr r3, [r3, #0]
8002002: 430a orrs r2, r1
8002004: 60da str r2, [r3, #12]
8002006: e022 b.n 800204e <HAL_ADC_ConfigChannel+0xbe>
}
else /* ADC_Channel include in ADC_Channel_[0..9] */
{
/* Clear the old sample time */
hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfig->Channel);
8002008: 687b ldr r3, [r7, #4]
800200a: 681b ldr r3, [r3, #0]
800200c: 6919 ldr r1, [r3, #16]
800200e: 683b ldr r3, [r7, #0]
8002010: 681b ldr r3, [r3, #0]
8002012: b29b uxth r3, r3
8002014: 461a mov r2, r3
8002016: 4613 mov r3, r2
8002018: 005b lsls r3, r3, #1
800201a: 4413 add r3, r2
800201c: 2207 movs r2, #7
800201e: fa02 f303 lsl.w r3, r2, r3
8002022: 43da mvns r2, r3
8002024: 687b ldr r3, [r7, #4]
8002026: 681b ldr r3, [r3, #0]
8002028: 400a ands r2, r1
800202a: 611a str r2, [r3, #16]
/* Set the new sample time */
hadc->Instance->SMPR2 |= ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel);
800202c: 687b ldr r3, [r7, #4]
800202e: 681b ldr r3, [r3, #0]
8002030: 6919 ldr r1, [r3, #16]
8002032: 683b ldr r3, [r7, #0]
8002034: 689a ldr r2, [r3, #8]
8002036: 683b ldr r3, [r7, #0]
8002038: 681b ldr r3, [r3, #0]
800203a: b29b uxth r3, r3
800203c: 4618 mov r0, r3
800203e: 4603 mov r3, r0
8002040: 005b lsls r3, r3, #1
8002042: 4403 add r3, r0
8002044: 409a lsls r2, r3
8002046: 687b ldr r3, [r7, #4]
8002048: 681b ldr r3, [r3, #0]
800204a: 430a orrs r2, r1
800204c: 611a str r2, [r3, #16]
}
/* For Rank 1 to 6 */
if (sConfig->Rank < 7U)
800204e: 683b ldr r3, [r7, #0]
8002050: 685b ldr r3, [r3, #4]
8002052: 2b06 cmp r3, #6
8002054: d824 bhi.n 80020a0 <HAL_ADC_ConfigChannel+0x110>
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR3 &= ~ADC_SQR3_RK(ADC_SQR3_SQ1, sConfig->Rank);
8002056: 687b ldr r3, [r7, #4]
8002058: 681b ldr r3, [r3, #0]
800205a: 6b59 ldr r1, [r3, #52] @ 0x34
800205c: 683b ldr r3, [r7, #0]
800205e: 685a ldr r2, [r3, #4]
8002060: 4613 mov r3, r2
8002062: 009b lsls r3, r3, #2
8002064: 4413 add r3, r2
8002066: 3b05 subs r3, #5
8002068: 221f movs r2, #31
800206a: fa02 f303 lsl.w r3, r2, r3
800206e: 43da mvns r2, r3
8002070: 687b ldr r3, [r7, #4]
8002072: 681b ldr r3, [r3, #0]
8002074: 400a ands r2, r1
8002076: 635a str r2, [r3, #52] @ 0x34
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR3 |= ADC_SQR3_RK(sConfig->Channel, sConfig->Rank);
8002078: 687b ldr r3, [r7, #4]
800207a: 681b ldr r3, [r3, #0]
800207c: 6b59 ldr r1, [r3, #52] @ 0x34
800207e: 683b ldr r3, [r7, #0]
8002080: 681b ldr r3, [r3, #0]
8002082: b29b uxth r3, r3
8002084: 4618 mov r0, r3
8002086: 683b ldr r3, [r7, #0]
8002088: 685a ldr r2, [r3, #4]
800208a: 4613 mov r3, r2
800208c: 009b lsls r3, r3, #2
800208e: 4413 add r3, r2
8002090: 3b05 subs r3, #5
8002092: fa00 f203 lsl.w r2, r0, r3
8002096: 687b ldr r3, [r7, #4]
8002098: 681b ldr r3, [r3, #0]
800209a: 430a orrs r2, r1
800209c: 635a str r2, [r3, #52] @ 0x34
800209e: e04c b.n 800213a <HAL_ADC_ConfigChannel+0x1aa>
}
/* For Rank 7 to 12 */
else if (sConfig->Rank < 13U)
80020a0: 683b ldr r3, [r7, #0]
80020a2: 685b ldr r3, [r3, #4]
80020a4: 2b0c cmp r3, #12
80020a6: d824 bhi.n 80020f2 <HAL_ADC_ConfigChannel+0x162>
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR2 &= ~ADC_SQR2_RK(ADC_SQR2_SQ7, sConfig->Rank);
80020a8: 687b ldr r3, [r7, #4]
80020aa: 681b ldr r3, [r3, #0]
80020ac: 6b19 ldr r1, [r3, #48] @ 0x30
80020ae: 683b ldr r3, [r7, #0]
80020b0: 685a ldr r2, [r3, #4]
80020b2: 4613 mov r3, r2
80020b4: 009b lsls r3, r3, #2
80020b6: 4413 add r3, r2
80020b8: 3b23 subs r3, #35 @ 0x23
80020ba: 221f movs r2, #31
80020bc: fa02 f303 lsl.w r3, r2, r3
80020c0: 43da mvns r2, r3
80020c2: 687b ldr r3, [r7, #4]
80020c4: 681b ldr r3, [r3, #0]
80020c6: 400a ands r2, r1
80020c8: 631a str r2, [r3, #48] @ 0x30
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR2 |= ADC_SQR2_RK(sConfig->Channel, sConfig->Rank);
80020ca: 687b ldr r3, [r7, #4]
80020cc: 681b ldr r3, [r3, #0]
80020ce: 6b19 ldr r1, [r3, #48] @ 0x30
80020d0: 683b ldr r3, [r7, #0]
80020d2: 681b ldr r3, [r3, #0]
80020d4: b29b uxth r3, r3
80020d6: 4618 mov r0, r3
80020d8: 683b ldr r3, [r7, #0]
80020da: 685a ldr r2, [r3, #4]
80020dc: 4613 mov r3, r2
80020de: 009b lsls r3, r3, #2
80020e0: 4413 add r3, r2
80020e2: 3b23 subs r3, #35 @ 0x23
80020e4: fa00 f203 lsl.w r2, r0, r3
80020e8: 687b ldr r3, [r7, #4]
80020ea: 681b ldr r3, [r3, #0]
80020ec: 430a orrs r2, r1
80020ee: 631a str r2, [r3, #48] @ 0x30
80020f0: e023 b.n 800213a <HAL_ADC_ConfigChannel+0x1aa>
}
/* For Rank 13 to 16 */
else
{
/* Clear the old SQx bits for the selected rank */
hadc->Instance->SQR1 &= ~ADC_SQR1_RK(ADC_SQR1_SQ13, sConfig->Rank);
80020f2: 687b ldr r3, [r7, #4]
80020f4: 681b ldr r3, [r3, #0]
80020f6: 6ad9 ldr r1, [r3, #44] @ 0x2c
80020f8: 683b ldr r3, [r7, #0]
80020fa: 685a ldr r2, [r3, #4]
80020fc: 4613 mov r3, r2
80020fe: 009b lsls r3, r3, #2
8002100: 4413 add r3, r2
8002102: 3b41 subs r3, #65 @ 0x41
8002104: 221f movs r2, #31
8002106: fa02 f303 lsl.w r3, r2, r3
800210a: 43da mvns r2, r3
800210c: 687b ldr r3, [r7, #4]
800210e: 681b ldr r3, [r3, #0]
8002110: 400a ands r2, r1
8002112: 62da str r2, [r3, #44] @ 0x2c
/* Set the SQx bits for the selected rank */
hadc->Instance->SQR1 |= ADC_SQR1_RK(sConfig->Channel, sConfig->Rank);
8002114: 687b ldr r3, [r7, #4]
8002116: 681b ldr r3, [r3, #0]
8002118: 6ad9 ldr r1, [r3, #44] @ 0x2c
800211a: 683b ldr r3, [r7, #0]
800211c: 681b ldr r3, [r3, #0]
800211e: b29b uxth r3, r3
8002120: 4618 mov r0, r3
8002122: 683b ldr r3, [r7, #0]
8002124: 685a ldr r2, [r3, #4]
8002126: 4613 mov r3, r2
8002128: 009b lsls r3, r3, #2
800212a: 4413 add r3, r2
800212c: 3b41 subs r3, #65 @ 0x41
800212e: fa00 f203 lsl.w r2, r0, r3
8002132: 687b ldr r3, [r7, #4]
8002134: 681b ldr r3, [r3, #0]
8002136: 430a orrs r2, r1
8002138: 62da str r2, [r3, #44] @ 0x2c
}
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
800213a: 4b29 ldr r3, [pc, #164] @ (80021e0 <HAL_ADC_ConfigChannel+0x250>)
800213c: 60fb str r3, [r7, #12]
/* if ADC1 Channel_18 is selected for VBAT Channel ennable VBATE */
if ((hadc->Instance == ADC1) && (sConfig->Channel == ADC_CHANNEL_VBAT))
800213e: 687b ldr r3, [r7, #4]
8002140: 681b ldr r3, [r3, #0]
8002142: 4a28 ldr r2, [pc, #160] @ (80021e4 <HAL_ADC_ConfigChannel+0x254>)
8002144: 4293 cmp r3, r2
8002146: d10f bne.n 8002168 <HAL_ADC_ConfigChannel+0x1d8>
8002148: 683b ldr r3, [r7, #0]
800214a: 681b ldr r3, [r3, #0]
800214c: 2b12 cmp r3, #18
800214e: d10b bne.n 8002168 <HAL_ADC_ConfigChannel+0x1d8>
{
/* Disable the TEMPSENSOR channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/
if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT)
{
tmpADC_Common->CCR &= ~ADC_CCR_TSVREFE;
8002150: 68fb ldr r3, [r7, #12]
8002152: 685b ldr r3, [r3, #4]
8002154: f423 0200 bic.w r2, r3, #8388608 @ 0x800000
8002158: 68fb ldr r3, [r7, #12]
800215a: 605a str r2, [r3, #4]
}
/* Enable the VBAT channel*/
tmpADC_Common->CCR |= ADC_CCR_VBATE;
800215c: 68fb ldr r3, [r7, #12]
800215e: 685b ldr r3, [r3, #4]
8002160: f443 0280 orr.w r2, r3, #4194304 @ 0x400000
8002164: 68fb ldr r3, [r7, #12]
8002166: 605a str r2, [r3, #4]
}
/* if ADC1 Channel_16 or Channel_18 is selected for Temperature sensor or
Channel_17 is selected for VREFINT enable TSVREFE */
if ((hadc->Instance == ADC1) && ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) || (sConfig->Channel == ADC_CHANNEL_VREFINT)))
8002168: 687b ldr r3, [r7, #4]
800216a: 681b ldr r3, [r3, #0]
800216c: 4a1d ldr r2, [pc, #116] @ (80021e4 <HAL_ADC_ConfigChannel+0x254>)
800216e: 4293 cmp r3, r2
8002170: d12b bne.n 80021ca <HAL_ADC_ConfigChannel+0x23a>
8002172: 683b ldr r3, [r7, #0]
8002174: 681b ldr r3, [r3, #0]
8002176: 4a1c ldr r2, [pc, #112] @ (80021e8 <HAL_ADC_ConfigChannel+0x258>)
8002178: 4293 cmp r3, r2
800217a: d003 beq.n 8002184 <HAL_ADC_ConfigChannel+0x1f4>
800217c: 683b ldr r3, [r7, #0]
800217e: 681b ldr r3, [r3, #0]
8002180: 2b11 cmp r3, #17
8002182: d122 bne.n 80021ca <HAL_ADC_ConfigChannel+0x23a>
{
/* Disable the VBAT channel in case of using board with multiplixed ADC_CHANNEL_VBAT & ADC_CHANNEL_TEMPSENSOR*/
if ((uint16_t)ADC_CHANNEL_TEMPSENSOR == (uint16_t)ADC_CHANNEL_VBAT)
{
tmpADC_Common->CCR &= ~ADC_CCR_VBATE;
8002184: 68fb ldr r3, [r7, #12]
8002186: 685b ldr r3, [r3, #4]
8002188: f423 0280 bic.w r2, r3, #4194304 @ 0x400000
800218c: 68fb ldr r3, [r7, #12]
800218e: 605a str r2, [r3, #4]
}
/* Enable the Temperature sensor and VREFINT channel*/
tmpADC_Common->CCR |= ADC_CCR_TSVREFE;
8002190: 68fb ldr r3, [r7, #12]
8002192: 685b ldr r3, [r3, #4]
8002194: f443 0200 orr.w r2, r3, #8388608 @ 0x800000
8002198: 68fb ldr r3, [r7, #12]
800219a: 605a str r2, [r3, #4]
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
800219c: 683b ldr r3, [r7, #0]
800219e: 681b ldr r3, [r3, #0]
80021a0: 4a11 ldr r2, [pc, #68] @ (80021e8 <HAL_ADC_ConfigChannel+0x258>)
80021a2: 4293 cmp r3, r2
80021a4: d111 bne.n 80021ca <HAL_ADC_ConfigChannel+0x23a>
{
/* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */
counter = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
80021a6: 4b11 ldr r3, [pc, #68] @ (80021ec <HAL_ADC_ConfigChannel+0x25c>)
80021a8: 681b ldr r3, [r3, #0]
80021aa: 4a11 ldr r2, [pc, #68] @ (80021f0 <HAL_ADC_ConfigChannel+0x260>)
80021ac: fba2 2303 umull r2, r3, r2, r3
80021b0: 0c9a lsrs r2, r3, #18
80021b2: 4613 mov r3, r2
80021b4: 009b lsls r3, r3, #2
80021b6: 4413 add r3, r2
80021b8: 005b lsls r3, r3, #1
80021ba: 60bb str r3, [r7, #8]
while (counter != 0U)
80021bc: e002 b.n 80021c4 <HAL_ADC_ConfigChannel+0x234>
{
counter--;
80021be: 68bb ldr r3, [r7, #8]
80021c0: 3b01 subs r3, #1
80021c2: 60bb str r3, [r7, #8]
while (counter != 0U)
80021c4: 68bb ldr r3, [r7, #8]
80021c6: 2b00 cmp r3, #0
80021c8: d1f9 bne.n 80021be <HAL_ADC_ConfigChannel+0x22e>
}
}
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
80021ca: 687b ldr r3, [r7, #4]
80021cc: 2200 movs r2, #0
80021ce: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Return function status */
return HAL_OK;
80021d2: 2300 movs r3, #0
}
80021d4: 4618 mov r0, r3
80021d6: 3714 adds r7, #20
80021d8: 46bd mov sp, r7
80021da: f85d 7b04 ldr.w r7, [sp], #4
80021de: 4770 bx lr
80021e0: 40012300 .word 0x40012300
80021e4: 40012000 .word 0x40012000
80021e8: 10000012 .word 0x10000012
80021ec: 20000008 .word 0x20000008
80021f0: 431bde83 .word 0x431bde83
080021f4 <ADC_Init>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
static void ADC_Init(ADC_HandleTypeDef *hadc)
{
80021f4: b480 push {r7}
80021f6: b085 sub sp, #20
80021f8: af00 add r7, sp, #0
80021fa: 6078 str r0, [r7, #4]
/* Set ADC parameters */
/* Pointer to the common control register to which is belonging hadc */
/* (Depending on STM32F4 product, there may be up to 3 ADCs and 1 common */
/* control register) */
tmpADC_Common = ADC_COMMON_REGISTER(hadc);
80021fc: 4b79 ldr r3, [pc, #484] @ (80023e4 <ADC_Init+0x1f0>)
80021fe: 60fb str r3, [r7, #12]
/* Set the ADC clock prescaler */
tmpADC_Common->CCR &= ~(ADC_CCR_ADCPRE);
8002200: 68fb ldr r3, [r7, #12]
8002202: 685b ldr r3, [r3, #4]
8002204: f423 3240 bic.w r2, r3, #196608 @ 0x30000
8002208: 68fb ldr r3, [r7, #12]
800220a: 605a str r2, [r3, #4]
tmpADC_Common->CCR |= hadc->Init.ClockPrescaler;
800220c: 68fb ldr r3, [r7, #12]
800220e: 685a ldr r2, [r3, #4]
8002210: 687b ldr r3, [r7, #4]
8002212: 685b ldr r3, [r3, #4]
8002214: 431a orrs r2, r3
8002216: 68fb ldr r3, [r7, #12]
8002218: 605a str r2, [r3, #4]
/* Set ADC scan mode */
hadc->Instance->CR1 &= ~(ADC_CR1_SCAN);
800221a: 687b ldr r3, [r7, #4]
800221c: 681b ldr r3, [r3, #0]
800221e: 685a ldr r2, [r3, #4]
8002220: 687b ldr r3, [r7, #4]
8002222: 681b ldr r3, [r3, #0]
8002224: f422 7280 bic.w r2, r2, #256 @ 0x100
8002228: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= ADC_CR1_SCANCONV(hadc->Init.ScanConvMode);
800222a: 687b ldr r3, [r7, #4]
800222c: 681b ldr r3, [r3, #0]
800222e: 6859 ldr r1, [r3, #4]
8002230: 687b ldr r3, [r7, #4]
8002232: 691b ldr r3, [r3, #16]
8002234: 021a lsls r2, r3, #8
8002236: 687b ldr r3, [r7, #4]
8002238: 681b ldr r3, [r3, #0]
800223a: 430a orrs r2, r1
800223c: 605a str r2, [r3, #4]
/* Set ADC resolution */
hadc->Instance->CR1 &= ~(ADC_CR1_RES);
800223e: 687b ldr r3, [r7, #4]
8002240: 681b ldr r3, [r3, #0]
8002242: 685a ldr r2, [r3, #4]
8002244: 687b ldr r3, [r7, #4]
8002246: 681b ldr r3, [r3, #0]
8002248: f022 7240 bic.w r2, r2, #50331648 @ 0x3000000
800224c: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= hadc->Init.Resolution;
800224e: 687b ldr r3, [r7, #4]
8002250: 681b ldr r3, [r3, #0]
8002252: 6859 ldr r1, [r3, #4]
8002254: 687b ldr r3, [r7, #4]
8002256: 689a ldr r2, [r3, #8]
8002258: 687b ldr r3, [r7, #4]
800225a: 681b ldr r3, [r3, #0]
800225c: 430a orrs r2, r1
800225e: 605a str r2, [r3, #4]
/* Set ADC data alignment */
hadc->Instance->CR2 &= ~(ADC_CR2_ALIGN);
8002260: 687b ldr r3, [r7, #4]
8002262: 681b ldr r3, [r3, #0]
8002264: 689a ldr r2, [r3, #8]
8002266: 687b ldr r3, [r7, #4]
8002268: 681b ldr r3, [r3, #0]
800226a: f422 6200 bic.w r2, r2, #2048 @ 0x800
800226e: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.DataAlign;
8002270: 687b ldr r3, [r7, #4]
8002272: 681b ldr r3, [r3, #0]
8002274: 6899 ldr r1, [r3, #8]
8002276: 687b ldr r3, [r7, #4]
8002278: 68da ldr r2, [r3, #12]
800227a: 687b ldr r3, [r7, #4]
800227c: 681b ldr r3, [r3, #0]
800227e: 430a orrs r2, r1
8002280: 609a str r2, [r3, #8]
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
8002282: 687b ldr r3, [r7, #4]
8002284: 6a9b ldr r3, [r3, #40] @ 0x28
8002286: 4a58 ldr r2, [pc, #352] @ (80023e8 <ADC_Init+0x1f4>)
8002288: 4293 cmp r3, r2
800228a: d022 beq.n 80022d2 <ADC_Init+0xde>
{
/* Select external trigger to start conversion */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
800228c: 687b ldr r3, [r7, #4]
800228e: 681b ldr r3, [r3, #0]
8002290: 689a ldr r2, [r3, #8]
8002292: 687b ldr r3, [r7, #4]
8002294: 681b ldr r3, [r3, #0]
8002296: f022 6270 bic.w r2, r2, #251658240 @ 0xf000000
800229a: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConv;
800229c: 687b ldr r3, [r7, #4]
800229e: 681b ldr r3, [r3, #0]
80022a0: 6899 ldr r1, [r3, #8]
80022a2: 687b ldr r3, [r7, #4]
80022a4: 6a9a ldr r2, [r3, #40] @ 0x28
80022a6: 687b ldr r3, [r7, #4]
80022a8: 681b ldr r3, [r3, #0]
80022aa: 430a orrs r2, r1
80022ac: 609a str r2, [r3, #8]
/* Select external trigger polarity */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
80022ae: 687b ldr r3, [r7, #4]
80022b0: 681b ldr r3, [r3, #0]
80022b2: 689a ldr r2, [r3, #8]
80022b4: 687b ldr r3, [r7, #4]
80022b6: 681b ldr r3, [r3, #0]
80022b8: f022 5240 bic.w r2, r2, #805306368 @ 0x30000000
80022bc: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= hadc->Init.ExternalTrigConvEdge;
80022be: 687b ldr r3, [r7, #4]
80022c0: 681b ldr r3, [r3, #0]
80022c2: 6899 ldr r1, [r3, #8]
80022c4: 687b ldr r3, [r7, #4]
80022c6: 6ada ldr r2, [r3, #44] @ 0x2c
80022c8: 687b ldr r3, [r7, #4]
80022ca: 681b ldr r3, [r3, #0]
80022cc: 430a orrs r2, r1
80022ce: 609a str r2, [r3, #8]
80022d0: e00f b.n 80022f2 <ADC_Init+0xfe>
}
else
{
/* Reset the external trigger */
hadc->Instance->CR2 &= ~(ADC_CR2_EXTSEL);
80022d2: 687b ldr r3, [r7, #4]
80022d4: 681b ldr r3, [r3, #0]
80022d6: 689a ldr r2, [r3, #8]
80022d8: 687b ldr r3, [r7, #4]
80022da: 681b ldr r3, [r3, #0]
80022dc: f022 6270 bic.w r2, r2, #251658240 @ 0xf000000
80022e0: 609a str r2, [r3, #8]
hadc->Instance->CR2 &= ~(ADC_CR2_EXTEN);
80022e2: 687b ldr r3, [r7, #4]
80022e4: 681b ldr r3, [r3, #0]
80022e6: 689a ldr r2, [r3, #8]
80022e8: 687b ldr r3, [r7, #4]
80022ea: 681b ldr r3, [r3, #0]
80022ec: f022 5240 bic.w r2, r2, #805306368 @ 0x30000000
80022f0: 609a str r2, [r3, #8]
}
/* Enable or disable ADC continuous conversion mode */
hadc->Instance->CR2 &= ~(ADC_CR2_CONT);
80022f2: 687b ldr r3, [r7, #4]
80022f4: 681b ldr r3, [r3, #0]
80022f6: 689a ldr r2, [r3, #8]
80022f8: 687b ldr r3, [r7, #4]
80022fa: 681b ldr r3, [r3, #0]
80022fc: f022 0202 bic.w r2, r2, #2
8002300: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode);
8002302: 687b ldr r3, [r7, #4]
8002304: 681b ldr r3, [r3, #0]
8002306: 6899 ldr r1, [r3, #8]
8002308: 687b ldr r3, [r7, #4]
800230a: 7e1b ldrb r3, [r3, #24]
800230c: 005a lsls r2, r3, #1
800230e: 687b ldr r3, [r7, #4]
8002310: 681b ldr r3, [r3, #0]
8002312: 430a orrs r2, r1
8002314: 609a str r2, [r3, #8]
if (hadc->Init.DiscontinuousConvMode != DISABLE)
8002316: 687b ldr r3, [r7, #4]
8002318: f893 3020 ldrb.w r3, [r3, #32]
800231c: 2b00 cmp r3, #0
800231e: d01b beq.n 8002358 <ADC_Init+0x164>
{
assert_param(IS_ADC_REGULAR_DISC_NUMBER(hadc->Init.NbrOfDiscConversion));
/* Enable the selected ADC regular discontinuous mode */
hadc->Instance->CR1 |= (uint32_t)ADC_CR1_DISCEN;
8002320: 687b ldr r3, [r7, #4]
8002322: 681b ldr r3, [r3, #0]
8002324: 685a ldr r2, [r3, #4]
8002326: 687b ldr r3, [r7, #4]
8002328: 681b ldr r3, [r3, #0]
800232a: f442 6200 orr.w r2, r2, #2048 @ 0x800
800232e: 605a str r2, [r3, #4]
/* Set the number of channels to be converted in discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCNUM);
8002330: 687b ldr r3, [r7, #4]
8002332: 681b ldr r3, [r3, #0]
8002334: 685a ldr r2, [r3, #4]
8002336: 687b ldr r3, [r7, #4]
8002338: 681b ldr r3, [r3, #0]
800233a: f422 4260 bic.w r2, r2, #57344 @ 0xe000
800233e: 605a str r2, [r3, #4]
hadc->Instance->CR1 |= ADC_CR1_DISCONTINUOUS(hadc->Init.NbrOfDiscConversion);
8002340: 687b ldr r3, [r7, #4]
8002342: 681b ldr r3, [r3, #0]
8002344: 6859 ldr r1, [r3, #4]
8002346: 687b ldr r3, [r7, #4]
8002348: 6a5b ldr r3, [r3, #36] @ 0x24
800234a: 3b01 subs r3, #1
800234c: 035a lsls r2, r3, #13
800234e: 687b ldr r3, [r7, #4]
8002350: 681b ldr r3, [r3, #0]
8002352: 430a orrs r2, r1
8002354: 605a str r2, [r3, #4]
8002356: e007 b.n 8002368 <ADC_Init+0x174>
}
else
{
/* Disable the selected ADC regular discontinuous mode */
hadc->Instance->CR1 &= ~(ADC_CR1_DISCEN);
8002358: 687b ldr r3, [r7, #4]
800235a: 681b ldr r3, [r3, #0]
800235c: 685a ldr r2, [r3, #4]
800235e: 687b ldr r3, [r7, #4]
8002360: 681b ldr r3, [r3, #0]
8002362: f422 6200 bic.w r2, r2, #2048 @ 0x800
8002366: 605a str r2, [r3, #4]
}
/* Set ADC number of conversion */
hadc->Instance->SQR1 &= ~(ADC_SQR1_L);
8002368: 687b ldr r3, [r7, #4]
800236a: 681b ldr r3, [r3, #0]
800236c: 6ada ldr r2, [r3, #44] @ 0x2c
800236e: 687b ldr r3, [r7, #4]
8002370: 681b ldr r3, [r3, #0]
8002372: f422 0270 bic.w r2, r2, #15728640 @ 0xf00000
8002376: 62da str r2, [r3, #44] @ 0x2c
hadc->Instance->SQR1 |= ADC_SQR1(hadc->Init.NbrOfConversion);
8002378: 687b ldr r3, [r7, #4]
800237a: 681b ldr r3, [r3, #0]
800237c: 6ad9 ldr r1, [r3, #44] @ 0x2c
800237e: 687b ldr r3, [r7, #4]
8002380: 69db ldr r3, [r3, #28]
8002382: 3b01 subs r3, #1
8002384: 051a lsls r2, r3, #20
8002386: 687b ldr r3, [r7, #4]
8002388: 681b ldr r3, [r3, #0]
800238a: 430a orrs r2, r1
800238c: 62da str r2, [r3, #44] @ 0x2c
/* Enable or disable ADC DMA continuous request */
hadc->Instance->CR2 &= ~(ADC_CR2_DDS);
800238e: 687b ldr r3, [r7, #4]
8002390: 681b ldr r3, [r3, #0]
8002392: 689a ldr r2, [r3, #8]
8002394: 687b ldr r3, [r7, #4]
8002396: 681b ldr r3, [r3, #0]
8002398: f422 7200 bic.w r2, r2, #512 @ 0x200
800239c: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_DMAContReq((uint32_t)hadc->Init.DMAContinuousRequests);
800239e: 687b ldr r3, [r7, #4]
80023a0: 681b ldr r3, [r3, #0]
80023a2: 6899 ldr r1, [r3, #8]
80023a4: 687b ldr r3, [r7, #4]
80023a6: f893 3030 ldrb.w r3, [r3, #48] @ 0x30
80023aa: 025a lsls r2, r3, #9
80023ac: 687b ldr r3, [r7, #4]
80023ae: 681b ldr r3, [r3, #0]
80023b0: 430a orrs r2, r1
80023b2: 609a str r2, [r3, #8]
/* Enable or disable ADC end of conversion selection */
hadc->Instance->CR2 &= ~(ADC_CR2_EOCS);
80023b4: 687b ldr r3, [r7, #4]
80023b6: 681b ldr r3, [r3, #0]
80023b8: 689a ldr r2, [r3, #8]
80023ba: 687b ldr r3, [r7, #4]
80023bc: 681b ldr r3, [r3, #0]
80023be: f422 6280 bic.w r2, r2, #1024 @ 0x400
80023c2: 609a str r2, [r3, #8]
hadc->Instance->CR2 |= ADC_CR2_EOCSelection(hadc->Init.EOCSelection);
80023c4: 687b ldr r3, [r7, #4]
80023c6: 681b ldr r3, [r3, #0]
80023c8: 6899 ldr r1, [r3, #8]
80023ca: 687b ldr r3, [r7, #4]
80023cc: 695b ldr r3, [r3, #20]
80023ce: 029a lsls r2, r3, #10
80023d0: 687b ldr r3, [r7, #4]
80023d2: 681b ldr r3, [r3, #0]
80023d4: 430a orrs r2, r1
80023d6: 609a str r2, [r3, #8]
}
80023d8: bf00 nop
80023da: 3714 adds r7, #20
80023dc: 46bd mov sp, r7
80023de: f85d 7b04 ldr.w r7, [sp], #4
80023e2: 4770 bx lr
80023e4: 40012300 .word 0x40012300
80023e8: 0f000001 .word 0x0f000001
080023ec <HAL_ADCEx_InjectedConvCpltCallback>:
* @param hadc pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None
*/
__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
{
80023ec: b480 push {r7}
80023ee: b083 sub sp, #12
80023f0: af00 add r7, sp, #0
80023f2: 6078 str r0, [r7, #4]
/* Prevent unused argument(s) compilation warning */
UNUSED(hadc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file
*/
}
80023f4: bf00 nop
80023f6: 370c adds r7, #12
80023f8: 46bd mov sp, r7
80023fa: f85d 7b04 ldr.w r7, [sp], #4
80023fe: 4770 bx lr
08002400 <HAL_CAN_Init>:
* @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
{
8002400: b580 push {r7, lr}
8002402: b084 sub sp, #16
8002404: af00 add r7, sp, #0
8002406: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Check CAN handle */
if (hcan == NULL)
8002408: 687b ldr r3, [r7, #4]
800240a: 2b00 cmp r3, #0
800240c: d101 bne.n 8002412 <HAL_CAN_Init+0x12>
{
return HAL_ERROR;
800240e: 2301 movs r3, #1
8002410: e0ed b.n 80025ee <HAL_CAN_Init+0x1ee>
/* Init the low level hardware: CLOCK, NVIC */
hcan->MspInitCallback(hcan);
}
#else
if (hcan->State == HAL_CAN_STATE_RESET)
8002412: 687b ldr r3, [r7, #4]
8002414: f893 3020 ldrb.w r3, [r3, #32]
8002418: b2db uxtb r3, r3
800241a: 2b00 cmp r3, #0
800241c: d102 bne.n 8002424 <HAL_CAN_Init+0x24>
{
/* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
800241e: 6878 ldr r0, [r7, #4]
8002420: f7fe f96c bl 80006fc <HAL_CAN_MspInit>
}
#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
/* Request initialisation */
SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
8002424: 687b ldr r3, [r7, #4]
8002426: 681b ldr r3, [r3, #0]
8002428: 681a ldr r2, [r3, #0]
800242a: 687b ldr r3, [r7, #4]
800242c: 681b ldr r3, [r3, #0]
800242e: f042 0201 orr.w r2, r2, #1
8002432: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8002434: f7ff fc0a bl 8001c4c <HAL_GetTick>
8002438: 60f8 str r0, [r7, #12]
/* Wait initialisation acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
800243a: e012 b.n 8002462 <HAL_CAN_Init+0x62>
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
800243c: f7ff fc06 bl 8001c4c <HAL_GetTick>
8002440: 4602 mov r2, r0
8002442: 68fb ldr r3, [r7, #12]
8002444: 1ad3 subs r3, r2, r3
8002446: 2b0a cmp r3, #10
8002448: d90b bls.n 8002462 <HAL_CAN_Init+0x62>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
800244a: 687b ldr r3, [r7, #4]
800244c: 6a5b ldr r3, [r3, #36] @ 0x24
800244e: f443 3200 orr.w r2, r3, #131072 @ 0x20000
8002452: 687b ldr r3, [r7, #4]
8002454: 625a str r2, [r3, #36] @ 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
8002456: 687b ldr r3, [r7, #4]
8002458: 2205 movs r2, #5
800245a: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
800245e: 2301 movs r3, #1
8002460: e0c5 b.n 80025ee <HAL_CAN_Init+0x1ee>
while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
8002462: 687b ldr r3, [r7, #4]
8002464: 681b ldr r3, [r3, #0]
8002466: 685b ldr r3, [r3, #4]
8002468: f003 0301 and.w r3, r3, #1
800246c: 2b00 cmp r3, #0
800246e: d0e5 beq.n 800243c <HAL_CAN_Init+0x3c>
}
}
/* Exit from sleep mode */
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
8002470: 687b ldr r3, [r7, #4]
8002472: 681b ldr r3, [r3, #0]
8002474: 681a ldr r2, [r3, #0]
8002476: 687b ldr r3, [r7, #4]
8002478: 681b ldr r3, [r3, #0]
800247a: f022 0202 bic.w r2, r2, #2
800247e: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8002480: f7ff fbe4 bl 8001c4c <HAL_GetTick>
8002484: 60f8 str r0, [r7, #12]
/* Check Sleep mode leave acknowledge */
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
8002486: e012 b.n 80024ae <HAL_CAN_Init+0xae>
{
if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
8002488: f7ff fbe0 bl 8001c4c <HAL_GetTick>
800248c: 4602 mov r2, r0
800248e: 68fb ldr r3, [r7, #12]
8002490: 1ad3 subs r3, r2, r3
8002492: 2b0a cmp r3, #10
8002494: d90b bls.n 80024ae <HAL_CAN_Init+0xae>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
8002496: 687b ldr r3, [r7, #4]
8002498: 6a5b ldr r3, [r3, #36] @ 0x24
800249a: f443 3200 orr.w r2, r3, #131072 @ 0x20000
800249e: 687b ldr r3, [r7, #4]
80024a0: 625a str r2, [r3, #36] @ 0x24
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
80024a2: 687b ldr r3, [r7, #4]
80024a4: 2205 movs r2, #5
80024a6: f883 2020 strb.w r2, [r3, #32]
return HAL_ERROR;
80024aa: 2301 movs r3, #1
80024ac: e09f b.n 80025ee <HAL_CAN_Init+0x1ee>
while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
80024ae: 687b ldr r3, [r7, #4]
80024b0: 681b ldr r3, [r3, #0]
80024b2: 685b ldr r3, [r3, #4]
80024b4: f003 0302 and.w r3, r3, #2
80024b8: 2b00 cmp r3, #0
80024ba: d1e5 bne.n 8002488 <HAL_CAN_Init+0x88>
}
}
/* Set the time triggered communication mode */
if (hcan->Init.TimeTriggeredMode == ENABLE)
80024bc: 687b ldr r3, [r7, #4]
80024be: 7e1b ldrb r3, [r3, #24]
80024c0: 2b01 cmp r3, #1
80024c2: d108 bne.n 80024d6 <HAL_CAN_Init+0xd6>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
80024c4: 687b ldr r3, [r7, #4]
80024c6: 681b ldr r3, [r3, #0]
80024c8: 681a ldr r2, [r3, #0]
80024ca: 687b ldr r3, [r7, #4]
80024cc: 681b ldr r3, [r3, #0]
80024ce: f042 0280 orr.w r2, r2, #128 @ 0x80
80024d2: 601a str r2, [r3, #0]
80024d4: e007 b.n 80024e6 <HAL_CAN_Init+0xe6>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
80024d6: 687b ldr r3, [r7, #4]
80024d8: 681b ldr r3, [r3, #0]
80024da: 681a ldr r2, [r3, #0]
80024dc: 687b ldr r3, [r7, #4]
80024de: 681b ldr r3, [r3, #0]
80024e0: f022 0280 bic.w r2, r2, #128 @ 0x80
80024e4: 601a str r2, [r3, #0]
}
/* Set the automatic bus-off management */
if (hcan->Init.AutoBusOff == ENABLE)
80024e6: 687b ldr r3, [r7, #4]
80024e8: 7e5b ldrb r3, [r3, #25]
80024ea: 2b01 cmp r3, #1
80024ec: d108 bne.n 8002500 <HAL_CAN_Init+0x100>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
80024ee: 687b ldr r3, [r7, #4]
80024f0: 681b ldr r3, [r3, #0]
80024f2: 681a ldr r2, [r3, #0]
80024f4: 687b ldr r3, [r7, #4]
80024f6: 681b ldr r3, [r3, #0]
80024f8: f042 0240 orr.w r2, r2, #64 @ 0x40
80024fc: 601a str r2, [r3, #0]
80024fe: e007 b.n 8002510 <HAL_CAN_Init+0x110>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
8002500: 687b ldr r3, [r7, #4]
8002502: 681b ldr r3, [r3, #0]
8002504: 681a ldr r2, [r3, #0]
8002506: 687b ldr r3, [r7, #4]
8002508: 681b ldr r3, [r3, #0]
800250a: f022 0240 bic.w r2, r2, #64 @ 0x40
800250e: 601a str r2, [r3, #0]
}
/* Set the automatic wake-up mode */
if (hcan->Init.AutoWakeUp == ENABLE)
8002510: 687b ldr r3, [r7, #4]
8002512: 7e9b ldrb r3, [r3, #26]
8002514: 2b01 cmp r3, #1
8002516: d108 bne.n 800252a <HAL_CAN_Init+0x12a>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
8002518: 687b ldr r3, [r7, #4]
800251a: 681b ldr r3, [r3, #0]
800251c: 681a ldr r2, [r3, #0]
800251e: 687b ldr r3, [r7, #4]
8002520: 681b ldr r3, [r3, #0]
8002522: f042 0220 orr.w r2, r2, #32
8002526: 601a str r2, [r3, #0]
8002528: e007 b.n 800253a <HAL_CAN_Init+0x13a>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
800252a: 687b ldr r3, [r7, #4]
800252c: 681b ldr r3, [r3, #0]
800252e: 681a ldr r2, [r3, #0]
8002530: 687b ldr r3, [r7, #4]
8002532: 681b ldr r3, [r3, #0]
8002534: f022 0220 bic.w r2, r2, #32
8002538: 601a str r2, [r3, #0]
}
/* Set the automatic retransmission */
if (hcan->Init.AutoRetransmission == ENABLE)
800253a: 687b ldr r3, [r7, #4]
800253c: 7edb ldrb r3, [r3, #27]
800253e: 2b01 cmp r3, #1
8002540: d108 bne.n 8002554 <HAL_CAN_Init+0x154>
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
8002542: 687b ldr r3, [r7, #4]
8002544: 681b ldr r3, [r3, #0]
8002546: 681a ldr r2, [r3, #0]
8002548: 687b ldr r3, [r7, #4]
800254a: 681b ldr r3, [r3, #0]
800254c: f022 0210 bic.w r2, r2, #16
8002550: 601a str r2, [r3, #0]
8002552: e007 b.n 8002564 <HAL_CAN_Init+0x164>
}
else
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
8002554: 687b ldr r3, [r7, #4]
8002556: 681b ldr r3, [r3, #0]
8002558: 681a ldr r2, [r3, #0]
800255a: 687b ldr r3, [r7, #4]
800255c: 681b ldr r3, [r3, #0]
800255e: f042 0210 orr.w r2, r2, #16
8002562: 601a str r2, [r3, #0]
}
/* Set the receive FIFO locked mode */
if (hcan->Init.ReceiveFifoLocked == ENABLE)
8002564: 687b ldr r3, [r7, #4]
8002566: 7f1b ldrb r3, [r3, #28]
8002568: 2b01 cmp r3, #1
800256a: d108 bne.n 800257e <HAL_CAN_Init+0x17e>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
800256c: 687b ldr r3, [r7, #4]
800256e: 681b ldr r3, [r3, #0]
8002570: 681a ldr r2, [r3, #0]
8002572: 687b ldr r3, [r7, #4]
8002574: 681b ldr r3, [r3, #0]
8002576: f042 0208 orr.w r2, r2, #8
800257a: 601a str r2, [r3, #0]
800257c: e007 b.n 800258e <HAL_CAN_Init+0x18e>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
800257e: 687b ldr r3, [r7, #4]
8002580: 681b ldr r3, [r3, #0]
8002582: 681a ldr r2, [r3, #0]
8002584: 687b ldr r3, [r7, #4]
8002586: 681b ldr r3, [r3, #0]
8002588: f022 0208 bic.w r2, r2, #8
800258c: 601a str r2, [r3, #0]
}
/* Set the transmit FIFO priority */
if (hcan->Init.TransmitFifoPriority == ENABLE)
800258e: 687b ldr r3, [r7, #4]
8002590: 7f5b ldrb r3, [r3, #29]
8002592: 2b01 cmp r3, #1
8002594: d108 bne.n 80025a8 <HAL_CAN_Init+0x1a8>
{
SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
8002596: 687b ldr r3, [r7, #4]
8002598: 681b ldr r3, [r3, #0]
800259a: 681a ldr r2, [r3, #0]
800259c: 687b ldr r3, [r7, #4]
800259e: 681b ldr r3, [r3, #0]
80025a0: f042 0204 orr.w r2, r2, #4
80025a4: 601a str r2, [r3, #0]
80025a6: e007 b.n 80025b8 <HAL_CAN_Init+0x1b8>
}
else
{
CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
80025a8: 687b ldr r3, [r7, #4]
80025aa: 681b ldr r3, [r3, #0]
80025ac: 681a ldr r2, [r3, #0]
80025ae: 687b ldr r3, [r7, #4]
80025b0: 681b ldr r3, [r3, #0]
80025b2: f022 0204 bic.w r2, r2, #4
80025b6: 601a str r2, [r3, #0]
}
/* Set the bit timing register */
WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
80025b8: 687b ldr r3, [r7, #4]
80025ba: 689a ldr r2, [r3, #8]
80025bc: 687b ldr r3, [r7, #4]
80025be: 68db ldr r3, [r3, #12]
80025c0: 431a orrs r2, r3
80025c2: 687b ldr r3, [r7, #4]
80025c4: 691b ldr r3, [r3, #16]
80025c6: 431a orrs r2, r3
80025c8: 687b ldr r3, [r7, #4]
80025ca: 695b ldr r3, [r3, #20]
80025cc: ea42 0103 orr.w r1, r2, r3
80025d0: 687b ldr r3, [r7, #4]
80025d2: 685b ldr r3, [r3, #4]
80025d4: 1e5a subs r2, r3, #1
80025d6: 687b ldr r3, [r7, #4]
80025d8: 681b ldr r3, [r3, #0]
80025da: 430a orrs r2, r1
80025dc: 61da str r2, [r3, #28]
hcan->Init.TimeSeg1 |
hcan->Init.TimeSeg2 |
(hcan->Init.Prescaler - 1U)));
/* Initialize the error code */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
80025de: 687b ldr r3, [r7, #4]
80025e0: 2200 movs r2, #0
80025e2: 625a str r2, [r3, #36] @ 0x24
/* Initialize the CAN state */
hcan->State = HAL_CAN_STATE_READY;
80025e4: 687b ldr r3, [r7, #4]
80025e6: 2201 movs r2, #1
80025e8: f883 2020 strb.w r2, [r3, #32]
/* Return function status */
return HAL_OK;
80025ec: 2300 movs r3, #0
}
80025ee: 4618 mov r0, r3
80025f0: 3710 adds r7, #16
80025f2: 46bd mov sp, r7
80025f4: bd80 pop {r7, pc}
080025f6 <HAL_CAN_AddTxMessage>:
* This parameter can be a value of @arg CAN_Tx_Mailboxes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader,
const uint8_t aData[], uint32_t *pTxMailbox)
{
80025f6: b480 push {r7}
80025f8: b089 sub sp, #36 @ 0x24
80025fa: af00 add r7, sp, #0
80025fc: 60f8 str r0, [r7, #12]
80025fe: 60b9 str r1, [r7, #8]
8002600: 607a str r2, [r7, #4]
8002602: 603b str r3, [r7, #0]
uint32_t transmitmailbox;
HAL_CAN_StateTypeDef state = hcan->State;
8002604: 68fb ldr r3, [r7, #12]
8002606: f893 3020 ldrb.w r3, [r3, #32]
800260a: 77fb strb r3, [r7, #31]
uint32_t tsr = READ_REG(hcan->Instance->TSR);
800260c: 68fb ldr r3, [r7, #12]
800260e: 681b ldr r3, [r3, #0]
8002610: 689b ldr r3, [r3, #8]
8002612: 61bb str r3, [r7, #24]
{
assert_param(IS_CAN_EXTID(pHeader->ExtId));
}
assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
if ((state == HAL_CAN_STATE_READY) ||
8002614: 7ffb ldrb r3, [r7, #31]
8002616: 2b01 cmp r3, #1
8002618: d003 beq.n 8002622 <HAL_CAN_AddTxMessage+0x2c>
800261a: 7ffb ldrb r3, [r7, #31]
800261c: 2b02 cmp r3, #2
800261e: f040 80ad bne.w 800277c <HAL_CAN_AddTxMessage+0x186>
(state == HAL_CAN_STATE_LISTENING))
{
/* Check that all the Tx mailboxes are not full */
if (((tsr & CAN_TSR_TME0) != 0U) ||
8002622: 69bb ldr r3, [r7, #24]
8002624: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
8002628: 2b00 cmp r3, #0
800262a: d10a bne.n 8002642 <HAL_CAN_AddTxMessage+0x4c>
((tsr & CAN_TSR_TME1) != 0U) ||
800262c: 69bb ldr r3, [r7, #24]
800262e: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
if (((tsr & CAN_TSR_TME0) != 0U) ||
8002632: 2b00 cmp r3, #0
8002634: d105 bne.n 8002642 <HAL_CAN_AddTxMessage+0x4c>
((tsr & CAN_TSR_TME2) != 0U))
8002636: 69bb ldr r3, [r7, #24]
8002638: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
((tsr & CAN_TSR_TME1) != 0U) ||
800263c: 2b00 cmp r3, #0
800263e: f000 8095 beq.w 800276c <HAL_CAN_AddTxMessage+0x176>
{
/* Select an empty transmit mailbox */
transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
8002642: 69bb ldr r3, [r7, #24]
8002644: 0e1b lsrs r3, r3, #24
8002646: f003 0303 and.w r3, r3, #3
800264a: 617b str r3, [r7, #20]
/* Store the Tx mailbox */
*pTxMailbox = (uint32_t)1 << transmitmailbox;
800264c: 2201 movs r2, #1
800264e: 697b ldr r3, [r7, #20]
8002650: 409a lsls r2, r3
8002652: 683b ldr r3, [r7, #0]
8002654: 601a str r2, [r3, #0]
/* Set up the Id */
if (pHeader->IDE == CAN_ID_STD)
8002656: 68bb ldr r3, [r7, #8]
8002658: 689b ldr r3, [r3, #8]
800265a: 2b00 cmp r3, #0
800265c: d10d bne.n 800267a <HAL_CAN_AddTxMessage+0x84>
{
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
800265e: 68bb ldr r3, [r7, #8]
8002660: 681b ldr r3, [r3, #0]
8002662: 055a lsls r2, r3, #21
pHeader->RTR);
8002664: 68bb ldr r3, [r7, #8]
8002666: 68db ldr r3, [r3, #12]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
8002668: 68f9 ldr r1, [r7, #12]
800266a: 6809 ldr r1, [r1, #0]
800266c: 431a orrs r2, r3
800266e: 697b ldr r3, [r7, #20]
8002670: 3318 adds r3, #24
8002672: 011b lsls r3, r3, #4
8002674: 440b add r3, r1
8002676: 601a str r2, [r3, #0]
8002678: e00f b.n 800269a <HAL_CAN_AddTxMessage+0xa4>
}
else
{
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
800267a: 68bb ldr r3, [r7, #8]
800267c: 685b ldr r3, [r3, #4]
800267e: 00da lsls r2, r3, #3
pHeader->IDE |
8002680: 68bb ldr r3, [r7, #8]
8002682: 689b ldr r3, [r3, #8]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8002684: 431a orrs r2, r3
pHeader->RTR);
8002686: 68bb ldr r3, [r7, #8]
8002688: 68db ldr r3, [r3, #12]
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
800268a: 68f9 ldr r1, [r7, #12]
800268c: 6809 ldr r1, [r1, #0]
pHeader->IDE |
800268e: 431a orrs r2, r3
hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
8002690: 697b ldr r3, [r7, #20]
8002692: 3318 adds r3, #24
8002694: 011b lsls r3, r3, #4
8002696: 440b add r3, r1
8002698: 601a str r2, [r3, #0]
}
/* Set up the DLC */
hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
800269a: 68fb ldr r3, [r7, #12]
800269c: 6819 ldr r1, [r3, #0]
800269e: 68bb ldr r3, [r7, #8]
80026a0: 691a ldr r2, [r3, #16]
80026a2: 697b ldr r3, [r7, #20]
80026a4: 3318 adds r3, #24
80026a6: 011b lsls r3, r3, #4
80026a8: 440b add r3, r1
80026aa: 3304 adds r3, #4
80026ac: 601a str r2, [r3, #0]
/* Set up the Transmit Global Time mode */
if (pHeader->TransmitGlobalTime == ENABLE)
80026ae: 68bb ldr r3, [r7, #8]
80026b0: 7d1b ldrb r3, [r3, #20]
80026b2: 2b01 cmp r3, #1
80026b4: d111 bne.n 80026da <HAL_CAN_AddTxMessage+0xe4>
{
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
80026b6: 68fb ldr r3, [r7, #12]
80026b8: 681a ldr r2, [r3, #0]
80026ba: 697b ldr r3, [r7, #20]
80026bc: 3318 adds r3, #24
80026be: 011b lsls r3, r3, #4
80026c0: 4413 add r3, r2
80026c2: 3304 adds r3, #4
80026c4: 681b ldr r3, [r3, #0]
80026c6: 68fa ldr r2, [r7, #12]
80026c8: 6811 ldr r1, [r2, #0]
80026ca: f443 7280 orr.w r2, r3, #256 @ 0x100
80026ce: 697b ldr r3, [r7, #20]
80026d0: 3318 adds r3, #24
80026d2: 011b lsls r3, r3, #4
80026d4: 440b add r3, r1
80026d6: 3304 adds r3, #4
80026d8: 601a str r2, [r3, #0]
}
/* Set up the data field */
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
80026da: 687b ldr r3, [r7, #4]
80026dc: 3307 adds r3, #7
80026de: 781b ldrb r3, [r3, #0]
80026e0: 061a lsls r2, r3, #24
80026e2: 687b ldr r3, [r7, #4]
80026e4: 3306 adds r3, #6
80026e6: 781b ldrb r3, [r3, #0]
80026e8: 041b lsls r3, r3, #16
80026ea: 431a orrs r2, r3
80026ec: 687b ldr r3, [r7, #4]
80026ee: 3305 adds r3, #5
80026f0: 781b ldrb r3, [r3, #0]
80026f2: 021b lsls r3, r3, #8
80026f4: 4313 orrs r3, r2
80026f6: 687a ldr r2, [r7, #4]
80026f8: 3204 adds r2, #4
80026fa: 7812 ldrb r2, [r2, #0]
80026fc: 4610 mov r0, r2
80026fe: 68fa ldr r2, [r7, #12]
8002700: 6811 ldr r1, [r2, #0]
8002702: ea43 0200 orr.w r2, r3, r0
8002706: 697b ldr r3, [r7, #20]
8002708: 011b lsls r3, r3, #4
800270a: 440b add r3, r1
800270c: f503 73c6 add.w r3, r3, #396 @ 0x18c
8002710: 601a str r2, [r3, #0]
((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
8002712: 687b ldr r3, [r7, #4]
8002714: 3303 adds r3, #3
8002716: 781b ldrb r3, [r3, #0]
8002718: 061a lsls r2, r3, #24
800271a: 687b ldr r3, [r7, #4]
800271c: 3302 adds r3, #2
800271e: 781b ldrb r3, [r3, #0]
8002720: 041b lsls r3, r3, #16
8002722: 431a orrs r2, r3
8002724: 687b ldr r3, [r7, #4]
8002726: 3301 adds r3, #1
8002728: 781b ldrb r3, [r3, #0]
800272a: 021b lsls r3, r3, #8
800272c: 4313 orrs r3, r2
800272e: 687a ldr r2, [r7, #4]
8002730: 7812 ldrb r2, [r2, #0]
8002732: 4610 mov r0, r2
8002734: 68fa ldr r2, [r7, #12]
8002736: 6811 ldr r1, [r2, #0]
8002738: ea43 0200 orr.w r2, r3, r0
800273c: 697b ldr r3, [r7, #20]
800273e: 011b lsls r3, r3, #4
8002740: 440b add r3, r1
8002742: f503 73c4 add.w r3, r3, #392 @ 0x188
8002746: 601a str r2, [r3, #0]
((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
/* Request transmission */
SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
8002748: 68fb ldr r3, [r7, #12]
800274a: 681a ldr r2, [r3, #0]
800274c: 697b ldr r3, [r7, #20]
800274e: 3318 adds r3, #24
8002750: 011b lsls r3, r3, #4
8002752: 4413 add r3, r2
8002754: 681b ldr r3, [r3, #0]
8002756: 68fa ldr r2, [r7, #12]
8002758: 6811 ldr r1, [r2, #0]
800275a: f043 0201 orr.w r2, r3, #1
800275e: 697b ldr r3, [r7, #20]
8002760: 3318 adds r3, #24
8002762: 011b lsls r3, r3, #4
8002764: 440b add r3, r1
8002766: 601a str r2, [r3, #0]
/* Return function status */
return HAL_OK;
8002768: 2300 movs r3, #0
800276a: e00e b.n 800278a <HAL_CAN_AddTxMessage+0x194>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
800276c: 68fb ldr r3, [r7, #12]
800276e: 6a5b ldr r3, [r3, #36] @ 0x24
8002770: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
8002774: 68fb ldr r3, [r7, #12]
8002776: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
8002778: 2301 movs r3, #1
800277a: e006 b.n 800278a <HAL_CAN_AddTxMessage+0x194>
}
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
800277c: 68fb ldr r3, [r7, #12]
800277e: 6a5b ldr r3, [r3, #36] @ 0x24
8002780: f443 2280 orr.w r2, r3, #262144 @ 0x40000
8002784: 68fb ldr r3, [r7, #12]
8002786: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
8002788: 2301 movs r3, #1
}
}
800278a: 4618 mov r0, r3
800278c: 3724 adds r7, #36 @ 0x24
800278e: 46bd mov sp, r7
8002790: f85d 7b04 ldr.w r7, [sp], #4
8002794: 4770 bx lr
08002796 <HAL_CAN_GetRxMessage>:
* @param aData array where the payload of the Rx frame will be stored.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
{
8002796: b480 push {r7}
8002798: b087 sub sp, #28
800279a: af00 add r7, sp, #0
800279c: 60f8 str r0, [r7, #12]
800279e: 60b9 str r1, [r7, #8]
80027a0: 607a str r2, [r7, #4]
80027a2: 603b str r3, [r7, #0]
HAL_CAN_StateTypeDef state = hcan->State;
80027a4: 68fb ldr r3, [r7, #12]
80027a6: f893 3020 ldrb.w r3, [r3, #32]
80027aa: 75fb strb r3, [r7, #23]
assert_param(IS_CAN_RX_FIFO(RxFifo));
if ((state == HAL_CAN_STATE_READY) ||
80027ac: 7dfb ldrb r3, [r7, #23]
80027ae: 2b01 cmp r3, #1
80027b0: d003 beq.n 80027ba <HAL_CAN_GetRxMessage+0x24>
80027b2: 7dfb ldrb r3, [r7, #23]
80027b4: 2b02 cmp r3, #2
80027b6: f040 8103 bne.w 80029c0 <HAL_CAN_GetRxMessage+0x22a>
(state == HAL_CAN_STATE_LISTENING))
{
/* Check the Rx FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
80027ba: 68bb ldr r3, [r7, #8]
80027bc: 2b00 cmp r3, #0
80027be: d10e bne.n 80027de <HAL_CAN_GetRxMessage+0x48>
{
/* Check that the Rx FIFO 0 is not empty */
if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)
80027c0: 68fb ldr r3, [r7, #12]
80027c2: 681b ldr r3, [r3, #0]
80027c4: 68db ldr r3, [r3, #12]
80027c6: f003 0303 and.w r3, r3, #3
80027ca: 2b00 cmp r3, #0
80027cc: d116 bne.n 80027fc <HAL_CAN_GetRxMessage+0x66>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
80027ce: 68fb ldr r3, [r7, #12]
80027d0: 6a5b ldr r3, [r3, #36] @ 0x24
80027d2: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
80027d6: 68fb ldr r3, [r7, #12]
80027d8: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
80027da: 2301 movs r3, #1
80027dc: e0f7 b.n 80029ce <HAL_CAN_GetRxMessage+0x238>
}
}
else /* Rx element is assigned to Rx FIFO 1 */
{
/* Check that the Rx FIFO 1 is not empty */
if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)
80027de: 68fb ldr r3, [r7, #12]
80027e0: 681b ldr r3, [r3, #0]
80027e2: 691b ldr r3, [r3, #16]
80027e4: f003 0303 and.w r3, r3, #3
80027e8: 2b00 cmp r3, #0
80027ea: d107 bne.n 80027fc <HAL_CAN_GetRxMessage+0x66>
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
80027ec: 68fb ldr r3, [r7, #12]
80027ee: 6a5b ldr r3, [r3, #36] @ 0x24
80027f0: f443 1200 orr.w r2, r3, #2097152 @ 0x200000
80027f4: 68fb ldr r3, [r7, #12]
80027f6: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
80027f8: 2301 movs r3, #1
80027fa: e0e8 b.n 80029ce <HAL_CAN_GetRxMessage+0x238>
}
}
/* Get the header */
pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
80027fc: 68fb ldr r3, [r7, #12]
80027fe: 681a ldr r2, [r3, #0]
8002800: 68bb ldr r3, [r7, #8]
8002802: 331b adds r3, #27
8002804: 011b lsls r3, r3, #4
8002806: 4413 add r3, r2
8002808: 681b ldr r3, [r3, #0]
800280a: f003 0204 and.w r2, r3, #4
800280e: 687b ldr r3, [r7, #4]
8002810: 609a str r2, [r3, #8]
if (pHeader->IDE == CAN_ID_STD)
8002812: 687b ldr r3, [r7, #4]
8002814: 689b ldr r3, [r3, #8]
8002816: 2b00 cmp r3, #0
8002818: d10c bne.n 8002834 <HAL_CAN_GetRxMessage+0x9e>
{
pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
800281a: 68fb ldr r3, [r7, #12]
800281c: 681a ldr r2, [r3, #0]
800281e: 68bb ldr r3, [r7, #8]
8002820: 331b adds r3, #27
8002822: 011b lsls r3, r3, #4
8002824: 4413 add r3, r2
8002826: 681b ldr r3, [r3, #0]
8002828: 0d5b lsrs r3, r3, #21
800282a: f3c3 020a ubfx r2, r3, #0, #11
800282e: 687b ldr r3, [r7, #4]
8002830: 601a str r2, [r3, #0]
8002832: e00b b.n 800284c <HAL_CAN_GetRxMessage+0xb6>
}
else
{
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) &
hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
8002834: 68fb ldr r3, [r7, #12]
8002836: 681a ldr r2, [r3, #0]
8002838: 68bb ldr r3, [r7, #8]
800283a: 331b adds r3, #27
800283c: 011b lsls r3, r3, #4
800283e: 4413 add r3, r2
8002840: 681b ldr r3, [r3, #0]
8002842: 08db lsrs r3, r3, #3
8002844: f023 4260 bic.w r2, r3, #3758096384 @ 0xe0000000
pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) &
8002848: 687b ldr r3, [r7, #4]
800284a: 605a str r2, [r3, #4]
}
pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
800284c: 68fb ldr r3, [r7, #12]
800284e: 681a ldr r2, [r3, #0]
8002850: 68bb ldr r3, [r7, #8]
8002852: 331b adds r3, #27
8002854: 011b lsls r3, r3, #4
8002856: 4413 add r3, r2
8002858: 681b ldr r3, [r3, #0]
800285a: f003 0202 and.w r2, r3, #2
800285e: 687b ldr r3, [r7, #4]
8002860: 60da str r2, [r3, #12]
if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U)
8002862: 68fb ldr r3, [r7, #12]
8002864: 681a ldr r2, [r3, #0]
8002866: 68bb ldr r3, [r7, #8]
8002868: 331b adds r3, #27
800286a: 011b lsls r3, r3, #4
800286c: 4413 add r3, r2
800286e: 3304 adds r3, #4
8002870: 681b ldr r3, [r3, #0]
8002872: f003 0308 and.w r3, r3, #8
8002876: 2b00 cmp r3, #0
8002878: d003 beq.n 8002882 <HAL_CAN_GetRxMessage+0xec>
{
/* Truncate DLC to 8 if received field is over range */
pHeader->DLC = 8U;
800287a: 687b ldr r3, [r7, #4]
800287c: 2208 movs r2, #8
800287e: 611a str r2, [r3, #16]
8002880: e00b b.n 800289a <HAL_CAN_GetRxMessage+0x104>
}
else
{
pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
8002882: 68fb ldr r3, [r7, #12]
8002884: 681a ldr r2, [r3, #0]
8002886: 68bb ldr r3, [r7, #8]
8002888: 331b adds r3, #27
800288a: 011b lsls r3, r3, #4
800288c: 4413 add r3, r2
800288e: 3304 adds r3, #4
8002890: 681b ldr r3, [r3, #0]
8002892: f003 020f and.w r2, r3, #15
8002896: 687b ldr r3, [r7, #4]
8002898: 611a str r2, [r3, #16]
}
pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
800289a: 68fb ldr r3, [r7, #12]
800289c: 681a ldr r2, [r3, #0]
800289e: 68bb ldr r3, [r7, #8]
80028a0: 331b adds r3, #27
80028a2: 011b lsls r3, r3, #4
80028a4: 4413 add r3, r2
80028a6: 3304 adds r3, #4
80028a8: 681b ldr r3, [r3, #0]
80028aa: 0a1b lsrs r3, r3, #8
80028ac: b2da uxtb r2, r3
80028ae: 687b ldr r3, [r7, #4]
80028b0: 619a str r2, [r3, #24]
pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
80028b2: 68fb ldr r3, [r7, #12]
80028b4: 681a ldr r2, [r3, #0]
80028b6: 68bb ldr r3, [r7, #8]
80028b8: 331b adds r3, #27
80028ba: 011b lsls r3, r3, #4
80028bc: 4413 add r3, r2
80028be: 3304 adds r3, #4
80028c0: 681b ldr r3, [r3, #0]
80028c2: 0c1b lsrs r3, r3, #16
80028c4: b29a uxth r2, r3
80028c6: 687b ldr r3, [r7, #4]
80028c8: 615a str r2, [r3, #20]
/* Get the data */
aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);
80028ca: 68fb ldr r3, [r7, #12]
80028cc: 681a ldr r2, [r3, #0]
80028ce: 68bb ldr r3, [r7, #8]
80028d0: 011b lsls r3, r3, #4
80028d2: 4413 add r3, r2
80028d4: f503 73dc add.w r3, r3, #440 @ 0x1b8
80028d8: 681b ldr r3, [r3, #0]
80028da: b2da uxtb r2, r3
80028dc: 683b ldr r3, [r7, #0]
80028de: 701a strb r2, [r3, #0]
aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);
80028e0: 68fb ldr r3, [r7, #12]
80028e2: 681a ldr r2, [r3, #0]
80028e4: 68bb ldr r3, [r7, #8]
80028e6: 011b lsls r3, r3, #4
80028e8: 4413 add r3, r2
80028ea: f503 73dc add.w r3, r3, #440 @ 0x1b8
80028ee: 681b ldr r3, [r3, #0]
80028f0: 0a1a lsrs r2, r3, #8
80028f2: 683b ldr r3, [r7, #0]
80028f4: 3301 adds r3, #1
80028f6: b2d2 uxtb r2, r2
80028f8: 701a strb r2, [r3, #0]
aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);
80028fa: 68fb ldr r3, [r7, #12]
80028fc: 681a ldr r2, [r3, #0]
80028fe: 68bb ldr r3, [r7, #8]
8002900: 011b lsls r3, r3, #4
8002902: 4413 add r3, r2
8002904: f503 73dc add.w r3, r3, #440 @ 0x1b8
8002908: 681b ldr r3, [r3, #0]
800290a: 0c1a lsrs r2, r3, #16
800290c: 683b ldr r3, [r7, #0]
800290e: 3302 adds r3, #2
8002910: b2d2 uxtb r2, r2
8002912: 701a strb r2, [r3, #0]
aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);
8002914: 68fb ldr r3, [r7, #12]
8002916: 681a ldr r2, [r3, #0]
8002918: 68bb ldr r3, [r7, #8]
800291a: 011b lsls r3, r3, #4
800291c: 4413 add r3, r2
800291e: f503 73dc add.w r3, r3, #440 @ 0x1b8
8002922: 681b ldr r3, [r3, #0]
8002924: 0e1a lsrs r2, r3, #24
8002926: 683b ldr r3, [r7, #0]
8002928: 3303 adds r3, #3
800292a: b2d2 uxtb r2, r2
800292c: 701a strb r2, [r3, #0]
aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);
800292e: 68fb ldr r3, [r7, #12]
8002930: 681a ldr r2, [r3, #0]
8002932: 68bb ldr r3, [r7, #8]
8002934: 011b lsls r3, r3, #4
8002936: 4413 add r3, r2
8002938: f503 73de add.w r3, r3, #444 @ 0x1bc
800293c: 681a ldr r2, [r3, #0]
800293e: 683b ldr r3, [r7, #0]
8002940: 3304 adds r3, #4
8002942: b2d2 uxtb r2, r2
8002944: 701a strb r2, [r3, #0]
aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);
8002946: 68fb ldr r3, [r7, #12]
8002948: 681a ldr r2, [r3, #0]
800294a: 68bb ldr r3, [r7, #8]
800294c: 011b lsls r3, r3, #4
800294e: 4413 add r3, r2
8002950: f503 73de add.w r3, r3, #444 @ 0x1bc
8002954: 681b ldr r3, [r3, #0]
8002956: 0a1a lsrs r2, r3, #8
8002958: 683b ldr r3, [r7, #0]
800295a: 3305 adds r3, #5
800295c: b2d2 uxtb r2, r2
800295e: 701a strb r2, [r3, #0]
aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);
8002960: 68fb ldr r3, [r7, #12]
8002962: 681a ldr r2, [r3, #0]
8002964: 68bb ldr r3, [r7, #8]
8002966: 011b lsls r3, r3, #4
8002968: 4413 add r3, r2
800296a: f503 73de add.w r3, r3, #444 @ 0x1bc
800296e: 681b ldr r3, [r3, #0]
8002970: 0c1a lsrs r2, r3, #16
8002972: 683b ldr r3, [r7, #0]
8002974: 3306 adds r3, #6
8002976: b2d2 uxtb r2, r2
8002978: 701a strb r2, [r3, #0]
aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);
800297a: 68fb ldr r3, [r7, #12]
800297c: 681a ldr r2, [r3, #0]
800297e: 68bb ldr r3, [r7, #8]
8002980: 011b lsls r3, r3, #4
8002982: 4413 add r3, r2
8002984: f503 73de add.w r3, r3, #444 @ 0x1bc
8002988: 681b ldr r3, [r3, #0]
800298a: 0e1a lsrs r2, r3, #24
800298c: 683b ldr r3, [r7, #0]
800298e: 3307 adds r3, #7
8002990: b2d2 uxtb r2, r2
8002992: 701a strb r2, [r3, #0]
/* Release the FIFO */
if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
8002994: 68bb ldr r3, [r7, #8]
8002996: 2b00 cmp r3, #0
8002998: d108 bne.n 80029ac <HAL_CAN_GetRxMessage+0x216>
{
/* Release RX FIFO 0 */
SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
800299a: 68fb ldr r3, [r7, #12]
800299c: 681b ldr r3, [r3, #0]
800299e: 68da ldr r2, [r3, #12]
80029a0: 68fb ldr r3, [r7, #12]
80029a2: 681b ldr r3, [r3, #0]
80029a4: f042 0220 orr.w r2, r2, #32
80029a8: 60da str r2, [r3, #12]
80029aa: e007 b.n 80029bc <HAL_CAN_GetRxMessage+0x226>
}
else /* Rx element is assigned to Rx FIFO 1 */
{
/* Release RX FIFO 1 */
SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
80029ac: 68fb ldr r3, [r7, #12]
80029ae: 681b ldr r3, [r3, #0]
80029b0: 691a ldr r2, [r3, #16]
80029b2: 68fb ldr r3, [r7, #12]
80029b4: 681b ldr r3, [r3, #0]
80029b6: f042 0220 orr.w r2, r2, #32
80029ba: 611a str r2, [r3, #16]
}
/* Return function status */
return HAL_OK;
80029bc: 2300 movs r3, #0
80029be: e006 b.n 80029ce <HAL_CAN_GetRxMessage+0x238>
}
else
{
/* Update error code */
hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
80029c0: 68fb ldr r3, [r7, #12]
80029c2: 6a5b ldr r3, [r3, #36] @ 0x24
80029c4: f443 2280 orr.w r2, r3, #262144 @ 0x40000
80029c8: 68fb ldr r3, [r7, #12]
80029ca: 625a str r2, [r3, #36] @ 0x24
return HAL_ERROR;
80029cc: 2301 movs r3, #1
}
}
80029ce: 4618 mov r0, r3
80029d0: 371c adds r7, #28
80029d2: 46bd mov sp, r7
80029d4: f85d 7b04 ldr.w r7, [sp], #4
80029d8: 4770 bx lr
080029da <HAL_CAN_GetRxFifoFillLevel>:
* @param RxFifo Rx FIFO.
* This parameter can be a value of @arg CAN_receive_FIFO_number.
* @retval Number of messages available in Rx FIFO.
*/
uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo)
{
80029da: b480 push {r7}
80029dc: b085 sub sp, #20
80029de: af00 add r7, sp, #0
80029e0: 6078 str r0, [r7, #4]
80029e2: 6039 str r1, [r7, #0]
uint32_t filllevel = 0U;
80029e4: 2300 movs r3, #0
80029e6: 60fb str r3, [r7, #12]
HAL_CAN_StateTypeDef state = hcan->State;
80029e8: 687b ldr r3, [r7, #4]
80029ea: f893 3020 ldrb.w r3, [r3, #32]
80029ee: 72fb strb r3, [r7, #11]
/* Check function parameters */
assert_param(IS_CAN_RX_FIFO(RxFifo));
if ((state == HAL_CAN_STATE_READY) ||
80029f0: 7afb ldrb r3, [r7, #11]
80029f2: 2b01 cmp r3, #1
80029f4: d002 beq.n 80029fc <HAL_CAN_GetRxFifoFillLevel+0x22>
80029f6: 7afb ldrb r3, [r7, #11]
80029f8: 2b02 cmp r3, #2
80029fa: d10f bne.n 8002a1c <HAL_CAN_GetRxFifoFillLevel+0x42>
(state == HAL_CAN_STATE_LISTENING))
{
if (RxFifo == CAN_RX_FIFO0)
80029fc: 683b ldr r3, [r7, #0]
80029fe: 2b00 cmp r3, #0
8002a00: d106 bne.n 8002a10 <HAL_CAN_GetRxFifoFillLevel+0x36>
{
filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0;
8002a02: 687b ldr r3, [r7, #4]
8002a04: 681b ldr r3, [r3, #0]
8002a06: 68db ldr r3, [r3, #12]
8002a08: f003 0303 and.w r3, r3, #3
8002a0c: 60fb str r3, [r7, #12]
8002a0e: e005 b.n 8002a1c <HAL_CAN_GetRxFifoFillLevel+0x42>
}
else /* RxFifo == CAN_RX_FIFO1 */
{
filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1;
8002a10: 687b ldr r3, [r7, #4]
8002a12: 681b ldr r3, [r3, #0]
8002a14: 691b ldr r3, [r3, #16]
8002a16: f003 0303 and.w r3, r3, #3
8002a1a: 60fb str r3, [r7, #12]
}
}
/* Return Rx FIFO fill level */
return filllevel;
8002a1c: 68fb ldr r3, [r7, #12]
}
8002a1e: 4618 mov r0, r3
8002a20: 3714 adds r7, #20
8002a22: 46bd mov sp, r7
8002a24: f85d 7b04 ldr.w r7, [sp], #4
8002a28: 4770 bx lr
...
08002a2c <__NVIC_SetPriorityGrouping>:
{
8002a2c: b480 push {r7}
8002a2e: b085 sub sp, #20
8002a30: af00 add r7, sp, #0
8002a32: 6078 str r0, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8002a34: 687b ldr r3, [r7, #4]
8002a36: f003 0307 and.w r3, r3, #7
8002a3a: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8002a3c: 4b0c ldr r3, [pc, #48] @ (8002a70 <__NVIC_SetPriorityGrouping+0x44>)
8002a3e: 68db ldr r3, [r3, #12]
8002a40: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8002a42: 68ba ldr r2, [r7, #8]
8002a44: f64f 03ff movw r3, #63743 @ 0xf8ff
8002a48: 4013 ands r3, r2
8002a4a: 60bb str r3, [r7, #8]
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8002a4c: 68fb ldr r3, [r7, #12]
8002a4e: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8002a50: 68bb ldr r3, [r7, #8]
8002a52: 4313 orrs r3, r2
reg_value = (reg_value |
8002a54: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8002a58: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8002a5c: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8002a5e: 4a04 ldr r2, [pc, #16] @ (8002a70 <__NVIC_SetPriorityGrouping+0x44>)
8002a60: 68bb ldr r3, [r7, #8]
8002a62: 60d3 str r3, [r2, #12]
}
8002a64: bf00 nop
8002a66: 3714 adds r7, #20
8002a68: 46bd mov sp, r7
8002a6a: f85d 7b04 ldr.w r7, [sp], #4
8002a6e: 4770 bx lr
8002a70: e000ed00 .word 0xe000ed00
08002a74 <__NVIC_GetPriorityGrouping>:
{
8002a74: b480 push {r7}
8002a76: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8002a78: 4b04 ldr r3, [pc, #16] @ (8002a8c <__NVIC_GetPriorityGrouping+0x18>)
8002a7a: 68db ldr r3, [r3, #12]
8002a7c: 0a1b lsrs r3, r3, #8
8002a7e: f003 0307 and.w r3, r3, #7
}
8002a82: 4618 mov r0, r3
8002a84: 46bd mov sp, r7
8002a86: f85d 7b04 ldr.w r7, [sp], #4
8002a8a: 4770 bx lr
8002a8c: e000ed00 .word 0xe000ed00
08002a90 <__NVIC_EnableIRQ>:
{
8002a90: b480 push {r7}
8002a92: b083 sub sp, #12
8002a94: af00 add r7, sp, #0
8002a96: 4603 mov r3, r0
8002a98: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8002a9a: f997 3007 ldrsb.w r3, [r7, #7]
8002a9e: 2b00 cmp r3, #0
8002aa0: db0b blt.n 8002aba <__NVIC_EnableIRQ+0x2a>
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8002aa2: 79fb ldrb r3, [r7, #7]
8002aa4: f003 021f and.w r2, r3, #31
8002aa8: 4907 ldr r1, [pc, #28] @ (8002ac8 <__NVIC_EnableIRQ+0x38>)
8002aaa: f997 3007 ldrsb.w r3, [r7, #7]
8002aae: 095b lsrs r3, r3, #5
8002ab0: 2001 movs r0, #1
8002ab2: fa00 f202 lsl.w r2, r0, r2
8002ab6: f841 2023 str.w r2, [r1, r3, lsl #2]
}
8002aba: bf00 nop
8002abc: 370c adds r7, #12
8002abe: 46bd mov sp, r7
8002ac0: f85d 7b04 ldr.w r7, [sp], #4
8002ac4: 4770 bx lr
8002ac6: bf00 nop
8002ac8: e000e100 .word 0xe000e100
08002acc <__NVIC_SetPriority>:
{
8002acc: b480 push {r7}
8002ace: b083 sub sp, #12
8002ad0: af00 add r7, sp, #0
8002ad2: 4603 mov r3, r0
8002ad4: 6039 str r1, [r7, #0]
8002ad6: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8002ad8: f997 3007 ldrsb.w r3, [r7, #7]
8002adc: 2b00 cmp r3, #0
8002ade: db0a blt.n 8002af6 <__NVIC_SetPriority+0x2a>
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8002ae0: 683b ldr r3, [r7, #0]
8002ae2: b2da uxtb r2, r3
8002ae4: 490c ldr r1, [pc, #48] @ (8002b18 <__NVIC_SetPriority+0x4c>)
8002ae6: f997 3007 ldrsb.w r3, [r7, #7]
8002aea: 0112 lsls r2, r2, #4
8002aec: b2d2 uxtb r2, r2
8002aee: 440b add r3, r1
8002af0: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
8002af4: e00a b.n 8002b0c <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8002af6: 683b ldr r3, [r7, #0]
8002af8: b2da uxtb r2, r3
8002afa: 4908 ldr r1, [pc, #32] @ (8002b1c <__NVIC_SetPriority+0x50>)
8002afc: 79fb ldrb r3, [r7, #7]
8002afe: f003 030f and.w r3, r3, #15
8002b02: 3b04 subs r3, #4
8002b04: 0112 lsls r2, r2, #4
8002b06: b2d2 uxtb r2, r2
8002b08: 440b add r3, r1
8002b0a: 761a strb r2, [r3, #24]
}
8002b0c: bf00 nop
8002b0e: 370c adds r7, #12
8002b10: 46bd mov sp, r7
8002b12: f85d 7b04 ldr.w r7, [sp], #4
8002b16: 4770 bx lr
8002b18: e000e100 .word 0xe000e100
8002b1c: e000ed00 .word 0xe000ed00
08002b20 <NVIC_EncodePriority>:
{
8002b20: b480 push {r7}
8002b22: b089 sub sp, #36 @ 0x24
8002b24: af00 add r7, sp, #0
8002b26: 60f8 str r0, [r7, #12]
8002b28: 60b9 str r1, [r7, #8]
8002b2a: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8002b2c: 68fb ldr r3, [r7, #12]
8002b2e: f003 0307 and.w r3, r3, #7
8002b32: 61fb str r3, [r7, #28]
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8002b34: 69fb ldr r3, [r7, #28]
8002b36: f1c3 0307 rsb r3, r3, #7
8002b3a: 2b04 cmp r3, #4
8002b3c: bf28 it cs
8002b3e: 2304 movcs r3, #4
8002b40: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8002b42: 69fb ldr r3, [r7, #28]
8002b44: 3304 adds r3, #4
8002b46: 2b06 cmp r3, #6
8002b48: d902 bls.n 8002b50 <NVIC_EncodePriority+0x30>
8002b4a: 69fb ldr r3, [r7, #28]
8002b4c: 3b03 subs r3, #3
8002b4e: e000 b.n 8002b52 <NVIC_EncodePriority+0x32>
8002b50: 2300 movs r3, #0
8002b52: 617b str r3, [r7, #20]
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8002b54: f04f 32ff mov.w r2, #4294967295
8002b58: 69bb ldr r3, [r7, #24]
8002b5a: fa02 f303 lsl.w r3, r2, r3
8002b5e: 43da mvns r2, r3
8002b60: 68bb ldr r3, [r7, #8]
8002b62: 401a ands r2, r3
8002b64: 697b ldr r3, [r7, #20]
8002b66: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8002b68: f04f 31ff mov.w r1, #4294967295
8002b6c: 697b ldr r3, [r7, #20]
8002b6e: fa01 f303 lsl.w r3, r1, r3
8002b72: 43d9 mvns r1, r3
8002b74: 687b ldr r3, [r7, #4]
8002b76: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8002b78: 4313 orrs r3, r2
}
8002b7a: 4618 mov r0, r3
8002b7c: 3724 adds r7, #36 @ 0x24
8002b7e: 46bd mov sp, r7
8002b80: f85d 7b04 ldr.w r7, [sp], #4
8002b84: 4770 bx lr
08002b86 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8002b86: b580 push {r7, lr}
8002b88: b082 sub sp, #8
8002b8a: af00 add r7, sp, #0
8002b8c: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8002b8e: 6878 ldr r0, [r7, #4]
8002b90: f7ff ff4c bl 8002a2c <__NVIC_SetPriorityGrouping>
}
8002b94: bf00 nop
8002b96: 3708 adds r7, #8
8002b98: 46bd mov sp, r7
8002b9a: bd80 pop {r7, pc}
08002b9c <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8002b9c: b580 push {r7, lr}
8002b9e: b086 sub sp, #24
8002ba0: af00 add r7, sp, #0
8002ba2: 4603 mov r3, r0
8002ba4: 60b9 str r1, [r7, #8]
8002ba6: 607a str r2, [r7, #4]
8002ba8: 73fb strb r3, [r7, #15]
uint32_t prioritygroup = 0x00U;
8002baa: 2300 movs r3, #0
8002bac: 617b str r3, [r7, #20]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8002bae: f7ff ff61 bl 8002a74 <__NVIC_GetPriorityGrouping>
8002bb2: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8002bb4: 687a ldr r2, [r7, #4]
8002bb6: 68b9 ldr r1, [r7, #8]
8002bb8: 6978 ldr r0, [r7, #20]
8002bba: f7ff ffb1 bl 8002b20 <NVIC_EncodePriority>
8002bbe: 4602 mov r2, r0
8002bc0: f997 300f ldrsb.w r3, [r7, #15]
8002bc4: 4611 mov r1, r2
8002bc6: 4618 mov r0, r3
8002bc8: f7ff ff80 bl 8002acc <__NVIC_SetPriority>
}
8002bcc: bf00 nop
8002bce: 3718 adds r7, #24
8002bd0: 46bd mov sp, r7
8002bd2: bd80 pop {r7, pc}
08002bd4 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8002bd4: b580 push {r7, lr}
8002bd6: b082 sub sp, #8
8002bd8: af00 add r7, sp, #0
8002bda: 4603 mov r3, r0
8002bdc: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8002bde: f997 3007 ldrsb.w r3, [r7, #7]
8002be2: 4618 mov r0, r3
8002be4: f7ff ff54 bl 8002a90 <__NVIC_EnableIRQ>
}
8002be8: bf00 nop
8002bea: 3708 adds r7, #8
8002bec: 46bd mov sp, r7
8002bee: bd80 pop {r7, pc}
08002bf0 <HAL_DMA_Abort_IT>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
{
8002bf0: b480 push {r7}
8002bf2: b083 sub sp, #12
8002bf4: af00 add r7, sp, #0
8002bf6: 6078 str r0, [r7, #4]
if(hdma->State != HAL_DMA_STATE_BUSY)
8002bf8: 687b ldr r3, [r7, #4]
8002bfa: f893 3035 ldrb.w r3, [r3, #53] @ 0x35
8002bfe: b2db uxtb r3, r3
8002c00: 2b02 cmp r3, #2
8002c02: d004 beq.n 8002c0e <HAL_DMA_Abort_IT+0x1e>
{
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8002c04: 687b ldr r3, [r7, #4]
8002c06: 2280 movs r2, #128 @ 0x80
8002c08: 655a str r2, [r3, #84] @ 0x54
return HAL_ERROR;
8002c0a: 2301 movs r3, #1
8002c0c: e00c b.n 8002c28 <HAL_DMA_Abort_IT+0x38>
}
else
{
/* Set Abort State */
hdma->State = HAL_DMA_STATE_ABORT;
8002c0e: 687b ldr r3, [r7, #4]
8002c10: 2205 movs r2, #5
8002c12: f883 2035 strb.w r2, [r3, #53] @ 0x35
/* Disable the stream */
__HAL_DMA_DISABLE(hdma);
8002c16: 687b ldr r3, [r7, #4]
8002c18: 681b ldr r3, [r3, #0]
8002c1a: 681a ldr r2, [r3, #0]
8002c1c: 687b ldr r3, [r7, #4]
8002c1e: 681b ldr r3, [r3, #0]
8002c20: f022 0201 bic.w r2, r2, #1
8002c24: 601a str r2, [r3, #0]
}
return HAL_OK;
8002c26: 2300 movs r3, #0
}
8002c28: 4618 mov r0, r3
8002c2a: 370c adds r7, #12
8002c2c: 46bd mov sp, r7
8002c2e: f85d 7b04 ldr.w r7, [sp], #4
8002c32: 4770 bx lr
08002c34 <HAL_FLASH_Program>:
* @param Data specifies the data to be programmed
*
* @retval HAL_StatusTypeDef HAL Status
*/
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
{
8002c34: b580 push {r7, lr}
8002c36: b086 sub sp, #24
8002c38: af00 add r7, sp, #0
8002c3a: 60f8 str r0, [r7, #12]
8002c3c: 60b9 str r1, [r7, #8]
8002c3e: e9c7 2300 strd r2, r3, [r7]
HAL_StatusTypeDef status = HAL_ERROR;
8002c42: 2301 movs r3, #1
8002c44: 75fb strb r3, [r7, #23]
/* Process Locked */
__HAL_LOCK(&pFlash);
8002c46: 4b23 ldr r3, [pc, #140] @ (8002cd4 <HAL_FLASH_Program+0xa0>)
8002c48: 7e1b ldrb r3, [r3, #24]
8002c4a: 2b01 cmp r3, #1
8002c4c: d101 bne.n 8002c52 <HAL_FLASH_Program+0x1e>
8002c4e: 2302 movs r3, #2
8002c50: e03b b.n 8002cca <HAL_FLASH_Program+0x96>
8002c52: 4b20 ldr r3, [pc, #128] @ (8002cd4 <HAL_FLASH_Program+0xa0>)
8002c54: 2201 movs r2, #1
8002c56: 761a strb r2, [r3, #24]
/* Check the parameters */
assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
8002c58: f24c 3050 movw r0, #50000 @ 0xc350
8002c5c: f000 f83e bl 8002cdc <FLASH_WaitForLastOperation>
8002c60: 4603 mov r3, r0
8002c62: 75fb strb r3, [r7, #23]
if(status == HAL_OK)
8002c64: 7dfb ldrb r3, [r7, #23]
8002c66: 2b00 cmp r3, #0
8002c68: d12b bne.n 8002cc2 <HAL_FLASH_Program+0x8e>
{
if(TypeProgram == FLASH_TYPEPROGRAM_BYTE)
8002c6a: 68fb ldr r3, [r7, #12]
8002c6c: 2b00 cmp r3, #0
8002c6e: d105 bne.n 8002c7c <HAL_FLASH_Program+0x48>
{
/*Program byte (8-bit) at a specified address.*/
FLASH_Program_Byte(Address, (uint8_t) Data);
8002c70: 783b ldrb r3, [r7, #0]
8002c72: 4619 mov r1, r3
8002c74: 68b8 ldr r0, [r7, #8]
8002c76: f000 f8e9 bl 8002e4c <FLASH_Program_Byte>
8002c7a: e016 b.n 8002caa <HAL_FLASH_Program+0x76>
}
else if(TypeProgram == FLASH_TYPEPROGRAM_HALFWORD)
8002c7c: 68fb ldr r3, [r7, #12]
8002c7e: 2b01 cmp r3, #1
8002c80: d105 bne.n 8002c8e <HAL_FLASH_Program+0x5a>
{
/*Program halfword (16-bit) at a specified address.*/
FLASH_Program_HalfWord(Address, (uint16_t) Data);
8002c82: 883b ldrh r3, [r7, #0]
8002c84: 4619 mov r1, r3
8002c86: 68b8 ldr r0, [r7, #8]
8002c88: f000 f8bc bl 8002e04 <FLASH_Program_HalfWord>
8002c8c: e00d b.n 8002caa <HAL_FLASH_Program+0x76>
}
else if(TypeProgram == FLASH_TYPEPROGRAM_WORD)
8002c8e: 68fb ldr r3, [r7, #12]
8002c90: 2b02 cmp r3, #2
8002c92: d105 bne.n 8002ca0 <HAL_FLASH_Program+0x6c>
{
/*Program word (32-bit) at a specified address.*/
FLASH_Program_Word(Address, (uint32_t) Data);
8002c94: 683b ldr r3, [r7, #0]
8002c96: 4619 mov r1, r3
8002c98: 68b8 ldr r0, [r7, #8]
8002c9a: f000 f891 bl 8002dc0 <FLASH_Program_Word>
8002c9e: e004 b.n 8002caa <HAL_FLASH_Program+0x76>
}
else
{
/*Program double word (64-bit) at a specified address.*/
FLASH_Program_DoubleWord(Address, Data);
8002ca0: e9d7 2300 ldrd r2, r3, [r7]
8002ca4: 68b8 ldr r0, [r7, #8]
8002ca6: f000 f859 bl 8002d5c <FLASH_Program_DoubleWord>
}
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
8002caa: f24c 3050 movw r0, #50000 @ 0xc350
8002cae: f000 f815 bl 8002cdc <FLASH_WaitForLastOperation>
8002cb2: 4603 mov r3, r0
8002cb4: 75fb strb r3, [r7, #23]
/* If the program operation is completed, disable the PG Bit */
FLASH->CR &= (~FLASH_CR_PG);
8002cb6: 4b08 ldr r3, [pc, #32] @ (8002cd8 <HAL_FLASH_Program+0xa4>)
8002cb8: 691b ldr r3, [r3, #16]
8002cba: 4a07 ldr r2, [pc, #28] @ (8002cd8 <HAL_FLASH_Program+0xa4>)
8002cbc: f023 0301 bic.w r3, r3, #1
8002cc0: 6113 str r3, [r2, #16]
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
8002cc2: 4b04 ldr r3, [pc, #16] @ (8002cd4 <HAL_FLASH_Program+0xa0>)
8002cc4: 2200 movs r2, #0
8002cc6: 761a strb r2, [r3, #24]
return status;
8002cc8: 7dfb ldrb r3, [r7, #23]
}
8002cca: 4618 mov r0, r3
8002ccc: 3718 adds r7, #24
8002cce: 46bd mov sp, r7
8002cd0: bd80 pop {r7, pc}
8002cd2: bf00 nop
8002cd4: 200002ac .word 0x200002ac
8002cd8: 40023c00 .word 0x40023c00
08002cdc <FLASH_WaitForLastOperation>:
* @brief Wait for a FLASH operation to complete.
* @param Timeout maximum flash operationtimeout
* @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
{
8002cdc: b580 push {r7, lr}
8002cde: b084 sub sp, #16
8002ce0: af00 add r7, sp, #0
8002ce2: 6078 str r0, [r7, #4]
uint32_t tickstart = 0U;
8002ce4: 2300 movs r3, #0
8002ce6: 60fb str r3, [r7, #12]
/* Clear Error Code */
pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
8002ce8: 4b1a ldr r3, [pc, #104] @ (8002d54 <FLASH_WaitForLastOperation+0x78>)
8002cea: 2200 movs r2, #0
8002cec: 61da str r2, [r3, #28]
/* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
Even if the FLASH operation fails, the BUSY flag will be reset and an error
flag will be set */
/* Get tick */
tickstart = HAL_GetTick();
8002cee: f7fe ffad bl 8001c4c <HAL_GetTick>
8002cf2: 60f8 str r0, [r7, #12]
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET)
8002cf4: e010 b.n 8002d18 <FLASH_WaitForLastOperation+0x3c>
{
if(Timeout != HAL_MAX_DELAY)
8002cf6: 687b ldr r3, [r7, #4]
8002cf8: f1b3 3fff cmp.w r3, #4294967295
8002cfc: d00c beq.n 8002d18 <FLASH_WaitForLastOperation+0x3c>
{
if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
8002cfe: 687b ldr r3, [r7, #4]
8002d00: 2b00 cmp r3, #0
8002d02: d007 beq.n 8002d14 <FLASH_WaitForLastOperation+0x38>
8002d04: f7fe ffa2 bl 8001c4c <HAL_GetTick>
8002d08: 4602 mov r2, r0
8002d0a: 68fb ldr r3, [r7, #12]
8002d0c: 1ad3 subs r3, r2, r3
8002d0e: 687a ldr r2, [r7, #4]
8002d10: 429a cmp r2, r3
8002d12: d201 bcs.n 8002d18 <FLASH_WaitForLastOperation+0x3c>
{
return HAL_TIMEOUT;
8002d14: 2303 movs r3, #3
8002d16: e019 b.n 8002d4c <FLASH_WaitForLastOperation+0x70>
while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET)
8002d18: 4b0f ldr r3, [pc, #60] @ (8002d58 <FLASH_WaitForLastOperation+0x7c>)
8002d1a: 68db ldr r3, [r3, #12]
8002d1c: f403 3380 and.w r3, r3, #65536 @ 0x10000
8002d20: 2b00 cmp r3, #0
8002d22: d1e8 bne.n 8002cf6 <FLASH_WaitForLastOperation+0x1a>
}
}
}
/* Check FLASH End of Operation flag */
if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
8002d24: 4b0c ldr r3, [pc, #48] @ (8002d58 <FLASH_WaitForLastOperation+0x7c>)
8002d26: 68db ldr r3, [r3, #12]
8002d28: f003 0301 and.w r3, r3, #1
8002d2c: 2b00 cmp r3, #0
8002d2e: d002 beq.n 8002d36 <FLASH_WaitForLastOperation+0x5a>
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
8002d30: 4b09 ldr r3, [pc, #36] @ (8002d58 <FLASH_WaitForLastOperation+0x7c>)
8002d32: 2201 movs r2, #1
8002d34: 60da str r2, [r3, #12]
}
#if defined(FLASH_SR_RDERR)
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
8002d36: 4b08 ldr r3, [pc, #32] @ (8002d58 <FLASH_WaitForLastOperation+0x7c>)
8002d38: 68db ldr r3, [r3, #12]
8002d3a: f403 73f9 and.w r3, r3, #498 @ 0x1f2
8002d3e: 2b00 cmp r3, #0
8002d40: d003 beq.n 8002d4a <FLASH_WaitForLastOperation+0x6e>
if(__HAL_FLASH_GET_FLAG((FLASH_FLAG_OPERR | FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | \
FLASH_FLAG_PGPERR | FLASH_FLAG_PGSERR)) != RESET)
#endif /* FLASH_SR_RDERR */
{
/*Save the error code*/
FLASH_SetErrorCode();
8002d42: f000 f8a5 bl 8002e90 <FLASH_SetErrorCode>
return HAL_ERROR;
8002d46: 2301 movs r3, #1
8002d48: e000 b.n 8002d4c <FLASH_WaitForLastOperation+0x70>
}
/* If there is no error flag set */
return HAL_OK;
8002d4a: 2300 movs r3, #0
}
8002d4c: 4618 mov r0, r3
8002d4e: 3710 adds r7, #16
8002d50: 46bd mov sp, r7
8002d52: bd80 pop {r7, pc}
8002d54: 200002ac .word 0x200002ac
8002d58: 40023c00 .word 0x40023c00
08002d5c <FLASH_Program_DoubleWord>:
* @param Address specifies the address to be programmed.
* @param Data specifies the data to be programmed.
* @retval None
*/
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
{
8002d5c: b480 push {r7}
8002d5e: b085 sub sp, #20
8002d60: af00 add r7, sp, #0
8002d62: 60f8 str r0, [r7, #12]
8002d64: e9c7 2300 strd r2, r3, [r7]
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
8002d68: 4b14 ldr r3, [pc, #80] @ (8002dbc <FLASH_Program_DoubleWord+0x60>)
8002d6a: 691b ldr r3, [r3, #16]
8002d6c: 4a13 ldr r2, [pc, #76] @ (8002dbc <FLASH_Program_DoubleWord+0x60>)
8002d6e: f423 7340 bic.w r3, r3, #768 @ 0x300
8002d72: 6113 str r3, [r2, #16]
FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
8002d74: 4b11 ldr r3, [pc, #68] @ (8002dbc <FLASH_Program_DoubleWord+0x60>)
8002d76: 691b ldr r3, [r3, #16]
8002d78: 4a10 ldr r2, [pc, #64] @ (8002dbc <FLASH_Program_DoubleWord+0x60>)
8002d7a: f443 7340 orr.w r3, r3, #768 @ 0x300
8002d7e: 6113 str r3, [r2, #16]
FLASH->CR |= FLASH_CR_PG;
8002d80: 4b0e ldr r3, [pc, #56] @ (8002dbc <FLASH_Program_DoubleWord+0x60>)
8002d82: 691b ldr r3, [r3, #16]
8002d84: 4a0d ldr r2, [pc, #52] @ (8002dbc <FLASH_Program_DoubleWord+0x60>)
8002d86: f043 0301 orr.w r3, r3, #1
8002d8a: 6113 str r3, [r2, #16]
/* Program first word */
*(__IO uint32_t*)Address = (uint32_t)Data;
8002d8c: 68fb ldr r3, [r7, #12]
8002d8e: 683a ldr r2, [r7, #0]
8002d90: 601a str r2, [r3, #0]
__ASM volatile ("isb 0xF":::"memory");
8002d92: f3bf 8f6f isb sy
}
8002d96: bf00 nop
/* Barrier to ensure programming is performed in 2 steps, in right order
(independently of compiler optimization behavior) */
__ISB();
/* Program second word */
*(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
8002d98: e9d7 0100 ldrd r0, r1, [r7]
8002d9c: f04f 0200 mov.w r2, #0
8002da0: f04f 0300 mov.w r3, #0
8002da4: 000a movs r2, r1
8002da6: 2300 movs r3, #0
8002da8: 68f9 ldr r1, [r7, #12]
8002daa: 3104 adds r1, #4
8002dac: 4613 mov r3, r2
8002dae: 600b str r3, [r1, #0]
}
8002db0: bf00 nop
8002db2: 3714 adds r7, #20
8002db4: 46bd mov sp, r7
8002db6: f85d 7b04 ldr.w r7, [sp], #4
8002dba: 4770 bx lr
8002dbc: 40023c00 .word 0x40023c00
08002dc0 <FLASH_Program_Word>:
* @param Address specifies the address to be programmed.
* @param Data specifies the data to be programmed.
* @retval None
*/
static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
{
8002dc0: b480 push {r7}
8002dc2: b083 sub sp, #12
8002dc4: af00 add r7, sp, #0
8002dc6: 6078 str r0, [r7, #4]
8002dc8: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
8002dca: 4b0d ldr r3, [pc, #52] @ (8002e00 <FLASH_Program_Word+0x40>)
8002dcc: 691b ldr r3, [r3, #16]
8002dce: 4a0c ldr r2, [pc, #48] @ (8002e00 <FLASH_Program_Word+0x40>)
8002dd0: f423 7340 bic.w r3, r3, #768 @ 0x300
8002dd4: 6113 str r3, [r2, #16]
FLASH->CR |= FLASH_PSIZE_WORD;
8002dd6: 4b0a ldr r3, [pc, #40] @ (8002e00 <FLASH_Program_Word+0x40>)
8002dd8: 691b ldr r3, [r3, #16]
8002dda: 4a09 ldr r2, [pc, #36] @ (8002e00 <FLASH_Program_Word+0x40>)
8002ddc: f443 7300 orr.w r3, r3, #512 @ 0x200
8002de0: 6113 str r3, [r2, #16]
FLASH->CR |= FLASH_CR_PG;
8002de2: 4b07 ldr r3, [pc, #28] @ (8002e00 <FLASH_Program_Word+0x40>)
8002de4: 691b ldr r3, [r3, #16]
8002de6: 4a06 ldr r2, [pc, #24] @ (8002e00 <FLASH_Program_Word+0x40>)
8002de8: f043 0301 orr.w r3, r3, #1
8002dec: 6113 str r3, [r2, #16]
*(__IO uint32_t*)Address = Data;
8002dee: 687b ldr r3, [r7, #4]
8002df0: 683a ldr r2, [r7, #0]
8002df2: 601a str r2, [r3, #0]
}
8002df4: bf00 nop
8002df6: 370c adds r7, #12
8002df8: 46bd mov sp, r7
8002dfa: f85d 7b04 ldr.w r7, [sp], #4
8002dfe: 4770 bx lr
8002e00: 40023c00 .word 0x40023c00
08002e04 <FLASH_Program_HalfWord>:
* @param Address specifies the address to be programmed.
* @param Data specifies the data to be programmed.
* @retval None
*/
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
{
8002e04: b480 push {r7}
8002e06: b083 sub sp, #12
8002e08: af00 add r7, sp, #0
8002e0a: 6078 str r0, [r7, #4]
8002e0c: 460b mov r3, r1
8002e0e: 807b strh r3, [r7, #2]
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
8002e10: 4b0d ldr r3, [pc, #52] @ (8002e48 <FLASH_Program_HalfWord+0x44>)
8002e12: 691b ldr r3, [r3, #16]
8002e14: 4a0c ldr r2, [pc, #48] @ (8002e48 <FLASH_Program_HalfWord+0x44>)
8002e16: f423 7340 bic.w r3, r3, #768 @ 0x300
8002e1a: 6113 str r3, [r2, #16]
FLASH->CR |= FLASH_PSIZE_HALF_WORD;
8002e1c: 4b0a ldr r3, [pc, #40] @ (8002e48 <FLASH_Program_HalfWord+0x44>)
8002e1e: 691b ldr r3, [r3, #16]
8002e20: 4a09 ldr r2, [pc, #36] @ (8002e48 <FLASH_Program_HalfWord+0x44>)
8002e22: f443 7380 orr.w r3, r3, #256 @ 0x100
8002e26: 6113 str r3, [r2, #16]
FLASH->CR |= FLASH_CR_PG;
8002e28: 4b07 ldr r3, [pc, #28] @ (8002e48 <FLASH_Program_HalfWord+0x44>)
8002e2a: 691b ldr r3, [r3, #16]
8002e2c: 4a06 ldr r2, [pc, #24] @ (8002e48 <FLASH_Program_HalfWord+0x44>)
8002e2e: f043 0301 orr.w r3, r3, #1
8002e32: 6113 str r3, [r2, #16]
*(__IO uint16_t*)Address = Data;
8002e34: 687b ldr r3, [r7, #4]
8002e36: 887a ldrh r2, [r7, #2]
8002e38: 801a strh r2, [r3, #0]
}
8002e3a: bf00 nop
8002e3c: 370c adds r7, #12
8002e3e: 46bd mov sp, r7
8002e40: f85d 7b04 ldr.w r7, [sp], #4
8002e44: 4770 bx lr
8002e46: bf00 nop
8002e48: 40023c00 .word 0x40023c00
08002e4c <FLASH_Program_Byte>:
* @param Address specifies the address to be programmed.
* @param Data specifies the data to be programmed.
* @retval None
*/
static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
{
8002e4c: b480 push {r7}
8002e4e: b083 sub sp, #12
8002e50: af00 add r7, sp, #0
8002e52: 6078 str r0, [r7, #4]
8002e54: 460b mov r3, r1
8002e56: 70fb strb r3, [r7, #3]
/* Check the parameters */
assert_param(IS_FLASH_ADDRESS(Address));
/* If the previous operation is completed, proceed to program the new data */
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
8002e58: 4b0c ldr r3, [pc, #48] @ (8002e8c <FLASH_Program_Byte+0x40>)
8002e5a: 691b ldr r3, [r3, #16]
8002e5c: 4a0b ldr r2, [pc, #44] @ (8002e8c <FLASH_Program_Byte+0x40>)
8002e5e: f423 7340 bic.w r3, r3, #768 @ 0x300
8002e62: 6113 str r3, [r2, #16]
FLASH->CR |= FLASH_PSIZE_BYTE;
8002e64: 4b09 ldr r3, [pc, #36] @ (8002e8c <FLASH_Program_Byte+0x40>)
8002e66: 4a09 ldr r2, [pc, #36] @ (8002e8c <FLASH_Program_Byte+0x40>)
8002e68: 691b ldr r3, [r3, #16]
8002e6a: 6113 str r3, [r2, #16]
FLASH->CR |= FLASH_CR_PG;
8002e6c: 4b07 ldr r3, [pc, #28] @ (8002e8c <FLASH_Program_Byte+0x40>)
8002e6e: 691b ldr r3, [r3, #16]
8002e70: 4a06 ldr r2, [pc, #24] @ (8002e8c <FLASH_Program_Byte+0x40>)
8002e72: f043 0301 orr.w r3, r3, #1
8002e76: 6113 str r3, [r2, #16]
*(__IO uint8_t*)Address = Data;
8002e78: 687b ldr r3, [r7, #4]
8002e7a: 78fa ldrb r2, [r7, #3]
8002e7c: 701a strb r2, [r3, #0]
}
8002e7e: bf00 nop
8002e80: 370c adds r7, #12
8002e82: 46bd mov sp, r7
8002e84: f85d 7b04 ldr.w r7, [sp], #4
8002e88: 4770 bx lr
8002e8a: bf00 nop
8002e8c: 40023c00 .word 0x40023c00
08002e90 <FLASH_SetErrorCode>:
/**
* @brief Set the specific FLASH error flag.
* @retval None
*/
static void FLASH_SetErrorCode(void)
{
8002e90: b480 push {r7}
8002e92: af00 add r7, sp, #0
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
8002e94: 4b2f ldr r3, [pc, #188] @ (8002f54 <FLASH_SetErrorCode+0xc4>)
8002e96: 68db ldr r3, [r3, #12]
8002e98: f003 0310 and.w r3, r3, #16
8002e9c: 2b00 cmp r3, #0
8002e9e: d008 beq.n 8002eb2 <FLASH_SetErrorCode+0x22>
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
8002ea0: 4b2d ldr r3, [pc, #180] @ (8002f58 <FLASH_SetErrorCode+0xc8>)
8002ea2: 69db ldr r3, [r3, #28]
8002ea4: f043 0310 orr.w r3, r3, #16
8002ea8: 4a2b ldr r2, [pc, #172] @ (8002f58 <FLASH_SetErrorCode+0xc8>)
8002eaa: 61d3 str r3, [r2, #28]
/* Clear FLASH write protection error pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR);
8002eac: 4b29 ldr r3, [pc, #164] @ (8002f54 <FLASH_SetErrorCode+0xc4>)
8002eae: 2210 movs r2, #16
8002eb0: 60da str r2, [r3, #12]
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
8002eb2: 4b28 ldr r3, [pc, #160] @ (8002f54 <FLASH_SetErrorCode+0xc4>)
8002eb4: 68db ldr r3, [r3, #12]
8002eb6: f003 0320 and.w r3, r3, #32
8002eba: 2b00 cmp r3, #0
8002ebc: d008 beq.n 8002ed0 <FLASH_SetErrorCode+0x40>
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
8002ebe: 4b26 ldr r3, [pc, #152] @ (8002f58 <FLASH_SetErrorCode+0xc8>)
8002ec0: 69db ldr r3, [r3, #28]
8002ec2: f043 0308 orr.w r3, r3, #8
8002ec6: 4a24 ldr r2, [pc, #144] @ (8002f58 <FLASH_SetErrorCode+0xc8>)
8002ec8: 61d3 str r3, [r2, #28]
/* Clear FLASH Programming alignment error pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGAERR);
8002eca: 4b22 ldr r3, [pc, #136] @ (8002f54 <FLASH_SetErrorCode+0xc4>)
8002ecc: 2220 movs r2, #32
8002ece: 60da str r2, [r3, #12]
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGPERR) != RESET)
8002ed0: 4b20 ldr r3, [pc, #128] @ (8002f54 <FLASH_SetErrorCode+0xc4>)
8002ed2: 68db ldr r3, [r3, #12]
8002ed4: f003 0340 and.w r3, r3, #64 @ 0x40
8002ed8: 2b00 cmp r3, #0
8002eda: d008 beq.n 8002eee <FLASH_SetErrorCode+0x5e>
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGP;
8002edc: 4b1e ldr r3, [pc, #120] @ (8002f58 <FLASH_SetErrorCode+0xc8>)
8002ede: 69db ldr r3, [r3, #28]
8002ee0: f043 0304 orr.w r3, r3, #4
8002ee4: 4a1c ldr r2, [pc, #112] @ (8002f58 <FLASH_SetErrorCode+0xc8>)
8002ee6: 61d3 str r3, [r2, #28]
/* Clear FLASH Programming parallelism error pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGPERR);
8002ee8: 4b1a ldr r3, [pc, #104] @ (8002f54 <FLASH_SetErrorCode+0xc4>)
8002eea: 2240 movs r2, #64 @ 0x40
8002eec: 60da str r2, [r3, #12]
}
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR) != RESET)
8002eee: 4b19 ldr r3, [pc, #100] @ (8002f54 <FLASH_SetErrorCode+0xc4>)
8002ef0: 68db ldr r3, [r3, #12]
8002ef2: f003 0380 and.w r3, r3, #128 @ 0x80
8002ef6: 2b00 cmp r3, #0
8002ef8: d008 beq.n 8002f0c <FLASH_SetErrorCode+0x7c>
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS;
8002efa: 4b17 ldr r3, [pc, #92] @ (8002f58 <FLASH_SetErrorCode+0xc8>)
8002efc: 69db ldr r3, [r3, #28]
8002efe: f043 0302 orr.w r3, r3, #2
8002f02: 4a15 ldr r2, [pc, #84] @ (8002f58 <FLASH_SetErrorCode+0xc8>)
8002f04: 61d3 str r3, [r2, #28]
/* Clear FLASH Programming sequence error pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_PGSERR);
8002f06: 4b13 ldr r3, [pc, #76] @ (8002f54 <FLASH_SetErrorCode+0xc4>)
8002f08: 2280 movs r2, #128 @ 0x80
8002f0a: 60da str r2, [r3, #12]
}
#if defined(FLASH_SR_RDERR)
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
8002f0c: 4b11 ldr r3, [pc, #68] @ (8002f54 <FLASH_SetErrorCode+0xc4>)
8002f0e: 68db ldr r3, [r3, #12]
8002f10: f403 7380 and.w r3, r3, #256 @ 0x100
8002f14: 2b00 cmp r3, #0
8002f16: d009 beq.n 8002f2c <FLASH_SetErrorCode+0x9c>
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
8002f18: 4b0f ldr r3, [pc, #60] @ (8002f58 <FLASH_SetErrorCode+0xc8>)
8002f1a: 69db ldr r3, [r3, #28]
8002f1c: f043 0301 orr.w r3, r3, #1
8002f20: 4a0d ldr r2, [pc, #52] @ (8002f58 <FLASH_SetErrorCode+0xc8>)
8002f22: 61d3 str r3, [r2, #28]
/* Clear FLASH Proprietary readout protection error pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_RDERR);
8002f24: 4b0b ldr r3, [pc, #44] @ (8002f54 <FLASH_SetErrorCode+0xc4>)
8002f26: f44f 7280 mov.w r2, #256 @ 0x100
8002f2a: 60da str r2, [r3, #12]
}
#endif /* FLASH_SR_RDERR */
if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR) != RESET)
8002f2c: 4b09 ldr r3, [pc, #36] @ (8002f54 <FLASH_SetErrorCode+0xc4>)
8002f2e: 68db ldr r3, [r3, #12]
8002f30: f003 0302 and.w r3, r3, #2
8002f34: 2b00 cmp r3, #0
8002f36: d008 beq.n 8002f4a <FLASH_SetErrorCode+0xba>
{
pFlash.ErrorCode |= HAL_FLASH_ERROR_OPERATION;
8002f38: 4b07 ldr r3, [pc, #28] @ (8002f58 <FLASH_SetErrorCode+0xc8>)
8002f3a: 69db ldr r3, [r3, #28]
8002f3c: f043 0320 orr.w r3, r3, #32
8002f40: 4a05 ldr r2, [pc, #20] @ (8002f58 <FLASH_SetErrorCode+0xc8>)
8002f42: 61d3 str r3, [r2, #28]
/* Clear FLASH Operation error pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_OPERR);
8002f44: 4b03 ldr r3, [pc, #12] @ (8002f54 <FLASH_SetErrorCode+0xc4>)
8002f46: 2202 movs r2, #2
8002f48: 60da str r2, [r3, #12]
}
}
8002f4a: bf00 nop
8002f4c: 46bd mov sp, r7
8002f4e: f85d 7b04 ldr.w r7, [sp], #4
8002f52: 4770 bx lr
8002f54: 40023c00 .word 0x40023c00
8002f58: 200002ac .word 0x200002ac
08002f5c <HAL_FLASHEx_Erase>:
* (0xFFFFFFFFU means that all the sectors have been correctly erased)
*
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError)
{
8002f5c: b580 push {r7, lr}
8002f5e: b084 sub sp, #16
8002f60: af00 add r7, sp, #0
8002f62: 6078 str r0, [r7, #4]
8002f64: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_ERROR;
8002f66: 2301 movs r3, #1
8002f68: 73fb strb r3, [r7, #15]
uint32_t index = 0U;
8002f6a: 2300 movs r3, #0
8002f6c: 60bb str r3, [r7, #8]
/* Process Locked */
__HAL_LOCK(&pFlash);
8002f6e: 4b31 ldr r3, [pc, #196] @ (8003034 <HAL_FLASHEx_Erase+0xd8>)
8002f70: 7e1b ldrb r3, [r3, #24]
8002f72: 2b01 cmp r3, #1
8002f74: d101 bne.n 8002f7a <HAL_FLASHEx_Erase+0x1e>
8002f76: 2302 movs r3, #2
8002f78: e058 b.n 800302c <HAL_FLASHEx_Erase+0xd0>
8002f7a: 4b2e ldr r3, [pc, #184] @ (8003034 <HAL_FLASHEx_Erase+0xd8>)
8002f7c: 2201 movs r2, #1
8002f7e: 761a strb r2, [r3, #24]
/* Check the parameters */
assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
8002f80: f24c 3050 movw r0, #50000 @ 0xc350
8002f84: f7ff feaa bl 8002cdc <FLASH_WaitForLastOperation>
8002f88: 4603 mov r3, r0
8002f8a: 73fb strb r3, [r7, #15]
if (status == HAL_OK)
8002f8c: 7bfb ldrb r3, [r7, #15]
8002f8e: 2b00 cmp r3, #0
8002f90: d148 bne.n 8003024 <HAL_FLASHEx_Erase+0xc8>
{
/*Initialization of SectorError variable*/
*SectorError = 0xFFFFFFFFU;
8002f92: 683b ldr r3, [r7, #0]
8002f94: f04f 32ff mov.w r2, #4294967295
8002f98: 601a str r2, [r3, #0]
if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
8002f9a: 687b ldr r3, [r7, #4]
8002f9c: 681b ldr r3, [r3, #0]
8002f9e: 2b01 cmp r3, #1
8002fa0: d115 bne.n 8002fce <HAL_FLASHEx_Erase+0x72>
{
/*Mass erase to be done*/
FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
8002fa2: 687b ldr r3, [r7, #4]
8002fa4: 691b ldr r3, [r3, #16]
8002fa6: b2da uxtb r2, r3
8002fa8: 687b ldr r3, [r7, #4]
8002faa: 685b ldr r3, [r3, #4]
8002fac: 4619 mov r1, r3
8002fae: 4610 mov r0, r2
8002fb0: f000 f844 bl 800303c <FLASH_MassErase>
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
8002fb4: f24c 3050 movw r0, #50000 @ 0xc350
8002fb8: f7ff fe90 bl 8002cdc <FLASH_WaitForLastOperation>
8002fbc: 4603 mov r3, r0
8002fbe: 73fb strb r3, [r7, #15]
/* if the erase operation is completed, disable the MER Bit */
FLASH->CR &= (~FLASH_MER_BIT);
8002fc0: 4b1d ldr r3, [pc, #116] @ (8003038 <HAL_FLASHEx_Erase+0xdc>)
8002fc2: 691b ldr r3, [r3, #16]
8002fc4: 4a1c ldr r2, [pc, #112] @ (8003038 <HAL_FLASHEx_Erase+0xdc>)
8002fc6: f023 0304 bic.w r3, r3, #4
8002fca: 6113 str r3, [r2, #16]
8002fcc: e028 b.n 8003020 <HAL_FLASHEx_Erase+0xc4>
{
/* Check the parameters */
assert_param(IS_FLASH_NBSECTORS(pEraseInit->NbSectors + pEraseInit->Sector));
/* Erase by sector by sector to be done*/
for (index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
8002fce: 687b ldr r3, [r7, #4]
8002fd0: 689b ldr r3, [r3, #8]
8002fd2: 60bb str r3, [r7, #8]
8002fd4: e01c b.n 8003010 <HAL_FLASHEx_Erase+0xb4>
{
FLASH_Erase_Sector(index, (uint8_t) pEraseInit->VoltageRange);
8002fd6: 687b ldr r3, [r7, #4]
8002fd8: 691b ldr r3, [r3, #16]
8002fda: b2db uxtb r3, r3
8002fdc: 4619 mov r1, r3
8002fde: 68b8 ldr r0, [r7, #8]
8002fe0: f000 f850 bl 8003084 <FLASH_Erase_Sector>
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
8002fe4: f24c 3050 movw r0, #50000 @ 0xc350
8002fe8: f7ff fe78 bl 8002cdc <FLASH_WaitForLastOperation>
8002fec: 4603 mov r3, r0
8002fee: 73fb strb r3, [r7, #15]
/* If the erase operation is completed, disable the SER and SNB Bits */
CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));
8002ff0: 4b11 ldr r3, [pc, #68] @ (8003038 <HAL_FLASHEx_Erase+0xdc>)
8002ff2: 691b ldr r3, [r3, #16]
8002ff4: 4a10 ldr r2, [pc, #64] @ (8003038 <HAL_FLASHEx_Erase+0xdc>)
8002ff6: f023 03fa bic.w r3, r3, #250 @ 0xfa
8002ffa: 6113 str r3, [r2, #16]
if (status != HAL_OK)
8002ffc: 7bfb ldrb r3, [r7, #15]
8002ffe: 2b00 cmp r3, #0
8003000: d003 beq.n 800300a <HAL_FLASHEx_Erase+0xae>
{
/* In case of error, stop erase procedure and return the faulty sector*/
*SectorError = index;
8003002: 683b ldr r3, [r7, #0]
8003004: 68ba ldr r2, [r7, #8]
8003006: 601a str r2, [r3, #0]
break;
8003008: e00a b.n 8003020 <HAL_FLASHEx_Erase+0xc4>
for (index = pEraseInit->Sector; index < (pEraseInit->NbSectors + pEraseInit->Sector); index++)
800300a: 68bb ldr r3, [r7, #8]
800300c: 3301 adds r3, #1
800300e: 60bb str r3, [r7, #8]
8003010: 687b ldr r3, [r7, #4]
8003012: 68da ldr r2, [r3, #12]
8003014: 687b ldr r3, [r7, #4]
8003016: 689b ldr r3, [r3, #8]
8003018: 4413 add r3, r2
800301a: 68ba ldr r2, [r7, #8]
800301c: 429a cmp r2, r3
800301e: d3da bcc.n 8002fd6 <HAL_FLASHEx_Erase+0x7a>
}
}
}
/* Flush the caches to be sure of the data consistency */
FLASH_FlushCaches();
8003020: f000 f878 bl 8003114 <FLASH_FlushCaches>
}
/* Process Unlocked */
__HAL_UNLOCK(&pFlash);
8003024: 4b03 ldr r3, [pc, #12] @ (8003034 <HAL_FLASHEx_Erase+0xd8>)
8003026: 2200 movs r2, #0
8003028: 761a strb r2, [r3, #24]
return status;
800302a: 7bfb ldrb r3, [r7, #15]
}
800302c: 4618 mov r0, r3
800302e: 3710 adds r7, #16
8003030: 46bd mov sp, r7
8003032: bd80 pop {r7, pc}
8003034: 200002ac .word 0x200002ac
8003038: 40023c00 .word 0x40023c00
0800303c <FLASH_MassErase>:
* @arg FLASH_BANK_1: Bank1 to be erased
*
* @retval None
*/
static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
{
800303c: b480 push {r7}
800303e: b083 sub sp, #12
8003040: af00 add r7, sp, #0
8003042: 4603 mov r3, r0
8003044: 6039 str r1, [r7, #0]
8003046: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_VOLTAGERANGE(VoltageRange));
assert_param(IS_FLASH_BANK(Banks));
/* If the previous operation is completed, proceed to erase all sectors */
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
8003048: 4b0d ldr r3, [pc, #52] @ (8003080 <FLASH_MassErase+0x44>)
800304a: 691b ldr r3, [r3, #16]
800304c: 4a0c ldr r2, [pc, #48] @ (8003080 <FLASH_MassErase+0x44>)
800304e: f423 7340 bic.w r3, r3, #768 @ 0x300
8003052: 6113 str r3, [r2, #16]
FLASH->CR |= FLASH_CR_MER;
8003054: 4b0a ldr r3, [pc, #40] @ (8003080 <FLASH_MassErase+0x44>)
8003056: 691b ldr r3, [r3, #16]
8003058: 4a09 ldr r2, [pc, #36] @ (8003080 <FLASH_MassErase+0x44>)
800305a: f043 0304 orr.w r3, r3, #4
800305e: 6113 str r3, [r2, #16]
FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange << 8U);
8003060: 4b07 ldr r3, [pc, #28] @ (8003080 <FLASH_MassErase+0x44>)
8003062: 691a ldr r2, [r3, #16]
8003064: 79fb ldrb r3, [r7, #7]
8003066: 021b lsls r3, r3, #8
8003068: 4313 orrs r3, r2
800306a: 4a05 ldr r2, [pc, #20] @ (8003080 <FLASH_MassErase+0x44>)
800306c: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8003070: 6113 str r3, [r2, #16]
}
8003072: bf00 nop
8003074: 370c adds r7, #12
8003076: 46bd mov sp, r7
8003078: f85d 7b04 ldr.w r7, [sp], #4
800307c: 4770 bx lr
800307e: bf00 nop
8003080: 40023c00 .word 0x40023c00
08003084 <FLASH_Erase_Sector>:
* the operation will be done by double word (64-bit)
*
* @retval None
*/
void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
{
8003084: b480 push {r7}
8003086: b085 sub sp, #20
8003088: af00 add r7, sp, #0
800308a: 6078 str r0, [r7, #4]
800308c: 460b mov r3, r1
800308e: 70fb strb r3, [r7, #3]
uint32_t tmp_psize = 0U;
8003090: 2300 movs r3, #0
8003092: 60fb str r3, [r7, #12]
/* Check the parameters */
assert_param(IS_FLASH_SECTOR(Sector));
assert_param(IS_VOLTAGERANGE(VoltageRange));
if (VoltageRange == FLASH_VOLTAGE_RANGE_1)
8003094: 78fb ldrb r3, [r7, #3]
8003096: 2b00 cmp r3, #0
8003098: d102 bne.n 80030a0 <FLASH_Erase_Sector+0x1c>
{
tmp_psize = FLASH_PSIZE_BYTE;
800309a: 2300 movs r3, #0
800309c: 60fb str r3, [r7, #12]
800309e: e010 b.n 80030c2 <FLASH_Erase_Sector+0x3e>
}
else if (VoltageRange == FLASH_VOLTAGE_RANGE_2)
80030a0: 78fb ldrb r3, [r7, #3]
80030a2: 2b01 cmp r3, #1
80030a4: d103 bne.n 80030ae <FLASH_Erase_Sector+0x2a>
{
tmp_psize = FLASH_PSIZE_HALF_WORD;
80030a6: f44f 7380 mov.w r3, #256 @ 0x100
80030aa: 60fb str r3, [r7, #12]
80030ac: e009 b.n 80030c2 <FLASH_Erase_Sector+0x3e>
}
else if (VoltageRange == FLASH_VOLTAGE_RANGE_3)
80030ae: 78fb ldrb r3, [r7, #3]
80030b0: 2b02 cmp r3, #2
80030b2: d103 bne.n 80030bc <FLASH_Erase_Sector+0x38>
{
tmp_psize = FLASH_PSIZE_WORD;
80030b4: f44f 7300 mov.w r3, #512 @ 0x200
80030b8: 60fb str r3, [r7, #12]
80030ba: e002 b.n 80030c2 <FLASH_Erase_Sector+0x3e>
}
else
{
tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
80030bc: f44f 7340 mov.w r3, #768 @ 0x300
80030c0: 60fb str r3, [r7, #12]
}
/* If the previous operation is completed, proceed to erase the sector */
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
80030c2: 4b13 ldr r3, [pc, #76] @ (8003110 <FLASH_Erase_Sector+0x8c>)
80030c4: 691b ldr r3, [r3, #16]
80030c6: 4a12 ldr r2, [pc, #72] @ (8003110 <FLASH_Erase_Sector+0x8c>)
80030c8: f423 7340 bic.w r3, r3, #768 @ 0x300
80030cc: 6113 str r3, [r2, #16]
FLASH->CR |= tmp_psize;
80030ce: 4b10 ldr r3, [pc, #64] @ (8003110 <FLASH_Erase_Sector+0x8c>)
80030d0: 691a ldr r2, [r3, #16]
80030d2: 490f ldr r1, [pc, #60] @ (8003110 <FLASH_Erase_Sector+0x8c>)
80030d4: 68fb ldr r3, [r7, #12]
80030d6: 4313 orrs r3, r2
80030d8: 610b str r3, [r1, #16]
CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
80030da: 4b0d ldr r3, [pc, #52] @ (8003110 <FLASH_Erase_Sector+0x8c>)
80030dc: 691b ldr r3, [r3, #16]
80030de: 4a0c ldr r2, [pc, #48] @ (8003110 <FLASH_Erase_Sector+0x8c>)
80030e0: f023 03f8 bic.w r3, r3, #248 @ 0xf8
80030e4: 6113 str r3, [r2, #16]
FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
80030e6: 4b0a ldr r3, [pc, #40] @ (8003110 <FLASH_Erase_Sector+0x8c>)
80030e8: 691a ldr r2, [r3, #16]
80030ea: 687b ldr r3, [r7, #4]
80030ec: 00db lsls r3, r3, #3
80030ee: 4313 orrs r3, r2
80030f0: 4a07 ldr r2, [pc, #28] @ (8003110 <FLASH_Erase_Sector+0x8c>)
80030f2: f043 0302 orr.w r3, r3, #2
80030f6: 6113 str r3, [r2, #16]
FLASH->CR |= FLASH_CR_STRT;
80030f8: 4b05 ldr r3, [pc, #20] @ (8003110 <FLASH_Erase_Sector+0x8c>)
80030fa: 691b ldr r3, [r3, #16]
80030fc: 4a04 ldr r2, [pc, #16] @ (8003110 <FLASH_Erase_Sector+0x8c>)
80030fe: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8003102: 6113 str r3, [r2, #16]
}
8003104: bf00 nop
8003106: 3714 adds r7, #20
8003108: 46bd mov sp, r7
800310a: f85d 7b04 ldr.w r7, [sp], #4
800310e: 4770 bx lr
8003110: 40023c00 .word 0x40023c00
08003114 <FLASH_FlushCaches>:
/**
* @brief Flush the instruction and data caches
* @retval None
*/
void FLASH_FlushCaches(void)
{
8003114: b480 push {r7}
8003116: af00 add r7, sp, #0
/* Flush instruction cache */
if (READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)
8003118: 4b20 ldr r3, [pc, #128] @ (800319c <FLASH_FlushCaches+0x88>)
800311a: 681b ldr r3, [r3, #0]
800311c: f403 7300 and.w r3, r3, #512 @ 0x200
8003120: 2b00 cmp r3, #0
8003122: d017 beq.n 8003154 <FLASH_FlushCaches+0x40>
{
/* Disable instruction cache */
__HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
8003124: 4b1d ldr r3, [pc, #116] @ (800319c <FLASH_FlushCaches+0x88>)
8003126: 681b ldr r3, [r3, #0]
8003128: 4a1c ldr r2, [pc, #112] @ (800319c <FLASH_FlushCaches+0x88>)
800312a: f423 7300 bic.w r3, r3, #512 @ 0x200
800312e: 6013 str r3, [r2, #0]
/* Reset instruction cache */
__HAL_FLASH_INSTRUCTION_CACHE_RESET();
8003130: 4b1a ldr r3, [pc, #104] @ (800319c <FLASH_FlushCaches+0x88>)
8003132: 681b ldr r3, [r3, #0]
8003134: 4a19 ldr r2, [pc, #100] @ (800319c <FLASH_FlushCaches+0x88>)
8003136: f443 6300 orr.w r3, r3, #2048 @ 0x800
800313a: 6013 str r3, [r2, #0]
800313c: 4b17 ldr r3, [pc, #92] @ (800319c <FLASH_FlushCaches+0x88>)
800313e: 681b ldr r3, [r3, #0]
8003140: 4a16 ldr r2, [pc, #88] @ (800319c <FLASH_FlushCaches+0x88>)
8003142: f423 6300 bic.w r3, r3, #2048 @ 0x800
8003146: 6013 str r3, [r2, #0]
/* Enable instruction cache */
__HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
8003148: 4b14 ldr r3, [pc, #80] @ (800319c <FLASH_FlushCaches+0x88>)
800314a: 681b ldr r3, [r3, #0]
800314c: 4a13 ldr r2, [pc, #76] @ (800319c <FLASH_FlushCaches+0x88>)
800314e: f443 7300 orr.w r3, r3, #512 @ 0x200
8003152: 6013 str r3, [r2, #0]
}
/* Flush data cache */
if (READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
8003154: 4b11 ldr r3, [pc, #68] @ (800319c <FLASH_FlushCaches+0x88>)
8003156: 681b ldr r3, [r3, #0]
8003158: f403 6380 and.w r3, r3, #1024 @ 0x400
800315c: 2b00 cmp r3, #0
800315e: d017 beq.n 8003190 <FLASH_FlushCaches+0x7c>
{
/* Disable data cache */
__HAL_FLASH_DATA_CACHE_DISABLE();
8003160: 4b0e ldr r3, [pc, #56] @ (800319c <FLASH_FlushCaches+0x88>)
8003162: 681b ldr r3, [r3, #0]
8003164: 4a0d ldr r2, [pc, #52] @ (800319c <FLASH_FlushCaches+0x88>)
8003166: f423 6380 bic.w r3, r3, #1024 @ 0x400
800316a: 6013 str r3, [r2, #0]
/* Reset data cache */
__HAL_FLASH_DATA_CACHE_RESET();
800316c: 4b0b ldr r3, [pc, #44] @ (800319c <FLASH_FlushCaches+0x88>)
800316e: 681b ldr r3, [r3, #0]
8003170: 4a0a ldr r2, [pc, #40] @ (800319c <FLASH_FlushCaches+0x88>)
8003172: f443 5380 orr.w r3, r3, #4096 @ 0x1000
8003176: 6013 str r3, [r2, #0]
8003178: 4b08 ldr r3, [pc, #32] @ (800319c <FLASH_FlushCaches+0x88>)
800317a: 681b ldr r3, [r3, #0]
800317c: 4a07 ldr r2, [pc, #28] @ (800319c <FLASH_FlushCaches+0x88>)
800317e: f423 5380 bic.w r3, r3, #4096 @ 0x1000
8003182: 6013 str r3, [r2, #0]
/* Enable data cache */
__HAL_FLASH_DATA_CACHE_ENABLE();
8003184: 4b05 ldr r3, [pc, #20] @ (800319c <FLASH_FlushCaches+0x88>)
8003186: 681b ldr r3, [r3, #0]
8003188: 4a04 ldr r2, [pc, #16] @ (800319c <FLASH_FlushCaches+0x88>)
800318a: f443 6380 orr.w r3, r3, #1024 @ 0x400
800318e: 6013 str r3, [r2, #0]
}
}
8003190: bf00 nop
8003192: 46bd mov sp, r7
8003194: f85d 7b04 ldr.w r7, [sp], #4
8003198: 4770 bx lr
800319a: bf00 nop
800319c: 40023c00 .word 0x40023c00
080031a0 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80031a0: b480 push {r7}
80031a2: b089 sub sp, #36 @ 0x24
80031a4: af00 add r7, sp, #0
80031a6: 6078 str r0, [r7, #4]
80031a8: 6039 str r1, [r7, #0]
uint32_t position;
uint32_t ioposition = 0x00U;
80031aa: 2300 movs r3, #0
80031ac: 617b str r3, [r7, #20]
uint32_t iocurrent = 0x00U;
80031ae: 2300 movs r3, #0
80031b0: 613b str r3, [r7, #16]
uint32_t temp = 0x00U;
80031b2: 2300 movs r3, #0
80031b4: 61bb str r3, [r7, #24]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
for(position = 0U; position < GPIO_NUMBER; position++)
80031b6: 2300 movs r3, #0
80031b8: 61fb str r3, [r7, #28]
80031ba: e165 b.n 8003488 <HAL_GPIO_Init+0x2e8>
{
/* Get the IO position */
ioposition = 0x01U << position;
80031bc: 2201 movs r2, #1
80031be: 69fb ldr r3, [r7, #28]
80031c0: fa02 f303 lsl.w r3, r2, r3
80031c4: 617b str r3, [r7, #20]
/* Get the current IO position */
iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
80031c6: 683b ldr r3, [r7, #0]
80031c8: 681b ldr r3, [r3, #0]
80031ca: 697a ldr r2, [r7, #20]
80031cc: 4013 ands r3, r2
80031ce: 613b str r3, [r7, #16]
if(iocurrent == ioposition)
80031d0: 693a ldr r2, [r7, #16]
80031d2: 697b ldr r3, [r7, #20]
80031d4: 429a cmp r2, r3
80031d6: f040 8154 bne.w 8003482 <HAL_GPIO_Init+0x2e2>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
80031da: 683b ldr r3, [r7, #0]
80031dc: 685b ldr r3, [r3, #4]
80031de: f003 0303 and.w r3, r3, #3
80031e2: 2b01 cmp r3, #1
80031e4: d005 beq.n 80031f2 <HAL_GPIO_Init+0x52>
(GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80031e6: 683b ldr r3, [r7, #0]
80031e8: 685b ldr r3, [r3, #4]
80031ea: f003 0303 and.w r3, r3, #3
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || \
80031ee: 2b02 cmp r3, #2
80031f0: d130 bne.n 8003254 <HAL_GPIO_Init+0xb4>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
80031f2: 687b ldr r3, [r7, #4]
80031f4: 689b ldr r3, [r3, #8]
80031f6: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2U));
80031f8: 69fb ldr r3, [r7, #28]
80031fa: 005b lsls r3, r3, #1
80031fc: 2203 movs r2, #3
80031fe: fa02 f303 lsl.w r3, r2, r3
8003202: 43db mvns r3, r3
8003204: 69ba ldr r2, [r7, #24]
8003206: 4013 ands r3, r2
8003208: 61bb str r3, [r7, #24]
temp |= (GPIO_Init->Speed << (position * 2U));
800320a: 683b ldr r3, [r7, #0]
800320c: 68da ldr r2, [r3, #12]
800320e: 69fb ldr r3, [r7, #28]
8003210: 005b lsls r3, r3, #1
8003212: fa02 f303 lsl.w r3, r2, r3
8003216: 69ba ldr r2, [r7, #24]
8003218: 4313 orrs r3, r2
800321a: 61bb str r3, [r7, #24]
GPIOx->OSPEEDR = temp;
800321c: 687b ldr r3, [r7, #4]
800321e: 69ba ldr r2, [r7, #24]
8003220: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8003222: 687b ldr r3, [r7, #4]
8003224: 685b ldr r3, [r3, #4]
8003226: 61bb str r3, [r7, #24]
temp &= ~(GPIO_OTYPER_OT_0 << position) ;
8003228: 2201 movs r2, #1
800322a: 69fb ldr r3, [r7, #28]
800322c: fa02 f303 lsl.w r3, r2, r3
8003230: 43db mvns r3, r3
8003232: 69ba ldr r2, [r7, #24]
8003234: 4013 ands r3, r2
8003236: 61bb str r3, [r7, #24]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
8003238: 683b ldr r3, [r7, #0]
800323a: 685b ldr r3, [r3, #4]
800323c: 091b lsrs r3, r3, #4
800323e: f003 0201 and.w r2, r3, #1
8003242: 69fb ldr r3, [r7, #28]
8003244: fa02 f303 lsl.w r3, r2, r3
8003248: 69ba ldr r2, [r7, #24]
800324a: 4313 orrs r3, r2
800324c: 61bb str r3, [r7, #24]
GPIOx->OTYPER = temp;
800324e: 687b ldr r3, [r7, #4]
8003250: 69ba ldr r2, [r7, #24]
8003252: 605a str r2, [r3, #4]
}
if((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8003254: 683b ldr r3, [r7, #0]
8003256: 685b ldr r3, [r3, #4]
8003258: f003 0303 and.w r3, r3, #3
800325c: 2b03 cmp r3, #3
800325e: d017 beq.n 8003290 <HAL_GPIO_Init+0xf0>
{
/* Check the parameters */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8003260: 687b ldr r3, [r7, #4]
8003262: 68db ldr r3, [r3, #12]
8003264: 61bb str r3, [r7, #24]
temp &= ~(GPIO_PUPDR_PUPDR0 << (position * 2U));
8003266: 69fb ldr r3, [r7, #28]
8003268: 005b lsls r3, r3, #1
800326a: 2203 movs r2, #3
800326c: fa02 f303 lsl.w r3, r2, r3
8003270: 43db mvns r3, r3
8003272: 69ba ldr r2, [r7, #24]
8003274: 4013 ands r3, r2
8003276: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Pull) << (position * 2U));
8003278: 683b ldr r3, [r7, #0]
800327a: 689a ldr r2, [r3, #8]
800327c: 69fb ldr r3, [r7, #28]
800327e: 005b lsls r3, r3, #1
8003280: fa02 f303 lsl.w r3, r2, r3
8003284: 69ba ldr r2, [r7, #24]
8003286: 4313 orrs r3, r2
8003288: 61bb str r3, [r7, #24]
GPIOx->PUPDR = temp;
800328a: 687b ldr r3, [r7, #4]
800328c: 69ba ldr r2, [r7, #24]
800328e: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
8003290: 683b ldr r3, [r7, #0]
8003292: 685b ldr r3, [r3, #4]
8003294: f003 0303 and.w r3, r3, #3
8003298: 2b02 cmp r3, #2
800329a: d123 bne.n 80032e4 <HAL_GPIO_Init+0x144>
{
/* Check the Alternate function parameter */
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
800329c: 69fb ldr r3, [r7, #28]
800329e: 08da lsrs r2, r3, #3
80032a0: 687b ldr r3, [r7, #4]
80032a2: 3208 adds r2, #8
80032a4: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80032a8: 61bb str r3, [r7, #24]
temp &= ~(0xFU << ((uint32_t)(position & 0x07U) * 4U)) ;
80032aa: 69fb ldr r3, [r7, #28]
80032ac: f003 0307 and.w r3, r3, #7
80032b0: 009b lsls r3, r3, #2
80032b2: 220f movs r2, #15
80032b4: fa02 f303 lsl.w r3, r2, r3
80032b8: 43db mvns r3, r3
80032ba: 69ba ldr r2, [r7, #24]
80032bc: 4013 ands r3, r2
80032be: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & 0x07U) * 4U));
80032c0: 683b ldr r3, [r7, #0]
80032c2: 691a ldr r2, [r3, #16]
80032c4: 69fb ldr r3, [r7, #28]
80032c6: f003 0307 and.w r3, r3, #7
80032ca: 009b lsls r3, r3, #2
80032cc: fa02 f303 lsl.w r3, r2, r3
80032d0: 69ba ldr r2, [r7, #24]
80032d2: 4313 orrs r3, r2
80032d4: 61bb str r3, [r7, #24]
GPIOx->AFR[position >> 3U] = temp;
80032d6: 69fb ldr r3, [r7, #28]
80032d8: 08da lsrs r2, r3, #3
80032da: 687b ldr r3, [r7, #4]
80032dc: 3208 adds r2, #8
80032de: 69b9 ldr r1, [r7, #24]
80032e0: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
80032e4: 687b ldr r3, [r7, #4]
80032e6: 681b ldr r3, [r3, #0]
80032e8: 61bb str r3, [r7, #24]
temp &= ~(GPIO_MODER_MODER0 << (position * 2U));
80032ea: 69fb ldr r3, [r7, #28]
80032ec: 005b lsls r3, r3, #1
80032ee: 2203 movs r2, #3
80032f0: fa02 f303 lsl.w r3, r2, r3
80032f4: 43db mvns r3, r3
80032f6: 69ba ldr r2, [r7, #24]
80032f8: 4013 ands r3, r2
80032fa: 61bb str r3, [r7, #24]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
80032fc: 683b ldr r3, [r7, #0]
80032fe: 685b ldr r3, [r3, #4]
8003300: f003 0203 and.w r2, r3, #3
8003304: 69fb ldr r3, [r7, #28]
8003306: 005b lsls r3, r3, #1
8003308: fa02 f303 lsl.w r3, r2, r3
800330c: 69ba ldr r2, [r7, #24]
800330e: 4313 orrs r3, r2
8003310: 61bb str r3, [r7, #24]
GPIOx->MODER = temp;
8003312: 687b ldr r3, [r7, #4]
8003314: 69ba ldr r2, [r7, #24]
8003316: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if((GPIO_Init->Mode & EXTI_MODE) != 0x00U)
8003318: 683b ldr r3, [r7, #0]
800331a: 685b ldr r3, [r3, #4]
800331c: f403 3340 and.w r3, r3, #196608 @ 0x30000
8003320: 2b00 cmp r3, #0
8003322: f000 80ae beq.w 8003482 <HAL_GPIO_Init+0x2e2>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8003326: 2300 movs r3, #0
8003328: 60fb str r3, [r7, #12]
800332a: 4b5d ldr r3, [pc, #372] @ (80034a0 <HAL_GPIO_Init+0x300>)
800332c: 6c5b ldr r3, [r3, #68] @ 0x44
800332e: 4a5c ldr r2, [pc, #368] @ (80034a0 <HAL_GPIO_Init+0x300>)
8003330: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8003334: 6453 str r3, [r2, #68] @ 0x44
8003336: 4b5a ldr r3, [pc, #360] @ (80034a0 <HAL_GPIO_Init+0x300>)
8003338: 6c5b ldr r3, [r3, #68] @ 0x44
800333a: f403 4380 and.w r3, r3, #16384 @ 0x4000
800333e: 60fb str r3, [r7, #12]
8003340: 68fb ldr r3, [r7, #12]
temp = SYSCFG->EXTICR[position >> 2U];
8003342: 4a58 ldr r2, [pc, #352] @ (80034a4 <HAL_GPIO_Init+0x304>)
8003344: 69fb ldr r3, [r7, #28]
8003346: 089b lsrs r3, r3, #2
8003348: 3302 adds r3, #2
800334a: f852 3023 ldr.w r3, [r2, r3, lsl #2]
800334e: 61bb str r3, [r7, #24]
temp &= ~(0x0FU << (4U * (position & 0x03U)));
8003350: 69fb ldr r3, [r7, #28]
8003352: f003 0303 and.w r3, r3, #3
8003356: 009b lsls r3, r3, #2
8003358: 220f movs r2, #15
800335a: fa02 f303 lsl.w r3, r2, r3
800335e: 43db mvns r3, r3
8003360: 69ba ldr r2, [r7, #24]
8003362: 4013 ands r3, r2
8003364: 61bb str r3, [r7, #24]
temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4U * (position & 0x03U)));
8003366: 687b ldr r3, [r7, #4]
8003368: 4a4f ldr r2, [pc, #316] @ (80034a8 <HAL_GPIO_Init+0x308>)
800336a: 4293 cmp r3, r2
800336c: d025 beq.n 80033ba <HAL_GPIO_Init+0x21a>
800336e: 687b ldr r3, [r7, #4]
8003370: 4a4e ldr r2, [pc, #312] @ (80034ac <HAL_GPIO_Init+0x30c>)
8003372: 4293 cmp r3, r2
8003374: d01f beq.n 80033b6 <HAL_GPIO_Init+0x216>
8003376: 687b ldr r3, [r7, #4]
8003378: 4a4d ldr r2, [pc, #308] @ (80034b0 <HAL_GPIO_Init+0x310>)
800337a: 4293 cmp r3, r2
800337c: d019 beq.n 80033b2 <HAL_GPIO_Init+0x212>
800337e: 687b ldr r3, [r7, #4]
8003380: 4a4c ldr r2, [pc, #304] @ (80034b4 <HAL_GPIO_Init+0x314>)
8003382: 4293 cmp r3, r2
8003384: d013 beq.n 80033ae <HAL_GPIO_Init+0x20e>
8003386: 687b ldr r3, [r7, #4]
8003388: 4a4b ldr r2, [pc, #300] @ (80034b8 <HAL_GPIO_Init+0x318>)
800338a: 4293 cmp r3, r2
800338c: d00d beq.n 80033aa <HAL_GPIO_Init+0x20a>
800338e: 687b ldr r3, [r7, #4]
8003390: 4a4a ldr r2, [pc, #296] @ (80034bc <HAL_GPIO_Init+0x31c>)
8003392: 4293 cmp r3, r2
8003394: d007 beq.n 80033a6 <HAL_GPIO_Init+0x206>
8003396: 687b ldr r3, [r7, #4]
8003398: 4a49 ldr r2, [pc, #292] @ (80034c0 <HAL_GPIO_Init+0x320>)
800339a: 4293 cmp r3, r2
800339c: d101 bne.n 80033a2 <HAL_GPIO_Init+0x202>
800339e: 2306 movs r3, #6
80033a0: e00c b.n 80033bc <HAL_GPIO_Init+0x21c>
80033a2: 2307 movs r3, #7
80033a4: e00a b.n 80033bc <HAL_GPIO_Init+0x21c>
80033a6: 2305 movs r3, #5
80033a8: e008 b.n 80033bc <HAL_GPIO_Init+0x21c>
80033aa: 2304 movs r3, #4
80033ac: e006 b.n 80033bc <HAL_GPIO_Init+0x21c>
80033ae: 2303 movs r3, #3
80033b0: e004 b.n 80033bc <HAL_GPIO_Init+0x21c>
80033b2: 2302 movs r3, #2
80033b4: e002 b.n 80033bc <HAL_GPIO_Init+0x21c>
80033b6: 2301 movs r3, #1
80033b8: e000 b.n 80033bc <HAL_GPIO_Init+0x21c>
80033ba: 2300 movs r3, #0
80033bc: 69fa ldr r2, [r7, #28]
80033be: f002 0203 and.w r2, r2, #3
80033c2: 0092 lsls r2, r2, #2
80033c4: 4093 lsls r3, r2
80033c6: 69ba ldr r2, [r7, #24]
80033c8: 4313 orrs r3, r2
80033ca: 61bb str r3, [r7, #24]
SYSCFG->EXTICR[position >> 2U] = temp;
80033cc: 4935 ldr r1, [pc, #212] @ (80034a4 <HAL_GPIO_Init+0x304>)
80033ce: 69fb ldr r3, [r7, #28]
80033d0: 089b lsrs r3, r3, #2
80033d2: 3302 adds r3, #2
80033d4: 69ba ldr r2, [r7, #24]
80033d6: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR;
80033da: 4b3a ldr r3, [pc, #232] @ (80034c4 <HAL_GPIO_Init+0x324>)
80033dc: 689b ldr r3, [r3, #8]
80033de: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
80033e0: 693b ldr r3, [r7, #16]
80033e2: 43db mvns r3, r3
80033e4: 69ba ldr r2, [r7, #24]
80033e6: 4013 ands r3, r2
80033e8: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
80033ea: 683b ldr r3, [r7, #0]
80033ec: 685b ldr r3, [r3, #4]
80033ee: f403 1380 and.w r3, r3, #1048576 @ 0x100000
80033f2: 2b00 cmp r3, #0
80033f4: d003 beq.n 80033fe <HAL_GPIO_Init+0x25e>
{
temp |= iocurrent;
80033f6: 69ba ldr r2, [r7, #24]
80033f8: 693b ldr r3, [r7, #16]
80033fa: 4313 orrs r3, r2
80033fc: 61bb str r3, [r7, #24]
}
EXTI->RTSR = temp;
80033fe: 4a31 ldr r2, [pc, #196] @ (80034c4 <HAL_GPIO_Init+0x324>)
8003400: 69bb ldr r3, [r7, #24]
8003402: 6093 str r3, [r2, #8]
temp = EXTI->FTSR;
8003404: 4b2f ldr r3, [pc, #188] @ (80034c4 <HAL_GPIO_Init+0x324>)
8003406: 68db ldr r3, [r3, #12]
8003408: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
800340a: 693b ldr r3, [r7, #16]
800340c: 43db mvns r3, r3
800340e: 69ba ldr r2, [r7, #24]
8003410: 4013 ands r3, r2
8003412: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8003414: 683b ldr r3, [r7, #0]
8003416: 685b ldr r3, [r3, #4]
8003418: f403 1300 and.w r3, r3, #2097152 @ 0x200000
800341c: 2b00 cmp r3, #0
800341e: d003 beq.n 8003428 <HAL_GPIO_Init+0x288>
{
temp |= iocurrent;
8003420: 69ba ldr r2, [r7, #24]
8003422: 693b ldr r3, [r7, #16]
8003424: 4313 orrs r3, r2
8003426: 61bb str r3, [r7, #24]
}
EXTI->FTSR = temp;
8003428: 4a26 ldr r2, [pc, #152] @ (80034c4 <HAL_GPIO_Init+0x324>)
800342a: 69bb ldr r3, [r7, #24]
800342c: 60d3 str r3, [r2, #12]
temp = EXTI->EMR;
800342e: 4b25 ldr r3, [pc, #148] @ (80034c4 <HAL_GPIO_Init+0x324>)
8003430: 685b ldr r3, [r3, #4]
8003432: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
8003434: 693b ldr r3, [r7, #16]
8003436: 43db mvns r3, r3
8003438: 69ba ldr r2, [r7, #24]
800343a: 4013 ands r3, r2
800343c: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
800343e: 683b ldr r3, [r7, #0]
8003440: 685b ldr r3, [r3, #4]
8003442: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003446: 2b00 cmp r3, #0
8003448: d003 beq.n 8003452 <HAL_GPIO_Init+0x2b2>
{
temp |= iocurrent;
800344a: 69ba ldr r2, [r7, #24]
800344c: 693b ldr r3, [r7, #16]
800344e: 4313 orrs r3, r2
8003450: 61bb str r3, [r7, #24]
}
EXTI->EMR = temp;
8003452: 4a1c ldr r2, [pc, #112] @ (80034c4 <HAL_GPIO_Init+0x324>)
8003454: 69bb ldr r3, [r7, #24]
8003456: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR;
8003458: 4b1a ldr r3, [pc, #104] @ (80034c4 <HAL_GPIO_Init+0x324>)
800345a: 681b ldr r3, [r3, #0]
800345c: 61bb str r3, [r7, #24]
temp &= ~((uint32_t)iocurrent);
800345e: 693b ldr r3, [r7, #16]
8003460: 43db mvns r3, r3
8003462: 69ba ldr r2, [r7, #24]
8003464: 4013 ands r3, r2
8003466: 61bb str r3, [r7, #24]
if((GPIO_Init->Mode & EXTI_IT) != 0x00U)
8003468: 683b ldr r3, [r7, #0]
800346a: 685b ldr r3, [r3, #4]
800346c: f403 3380 and.w r3, r3, #65536 @ 0x10000
8003470: 2b00 cmp r3, #0
8003472: d003 beq.n 800347c <HAL_GPIO_Init+0x2dc>
{
temp |= iocurrent;
8003474: 69ba ldr r2, [r7, #24]
8003476: 693b ldr r3, [r7, #16]
8003478: 4313 orrs r3, r2
800347a: 61bb str r3, [r7, #24]
}
EXTI->IMR = temp;
800347c: 4a11 ldr r2, [pc, #68] @ (80034c4 <HAL_GPIO_Init+0x324>)
800347e: 69bb ldr r3, [r7, #24]
8003480: 6013 str r3, [r2, #0]
for(position = 0U; position < GPIO_NUMBER; position++)
8003482: 69fb ldr r3, [r7, #28]
8003484: 3301 adds r3, #1
8003486: 61fb str r3, [r7, #28]
8003488: 69fb ldr r3, [r7, #28]
800348a: 2b0f cmp r3, #15
800348c: f67f ae96 bls.w 80031bc <HAL_GPIO_Init+0x1c>
}
}
}
}
8003490: bf00 nop
8003492: bf00 nop
8003494: 3724 adds r7, #36 @ 0x24
8003496: 46bd mov sp, r7
8003498: f85d 7b04 ldr.w r7, [sp], #4
800349c: 4770 bx lr
800349e: bf00 nop
80034a0: 40023800 .word 0x40023800
80034a4: 40013800 .word 0x40013800
80034a8: 40020000 .word 0x40020000
80034ac: 40020400 .word 0x40020400
80034b0: 40020800 .word 0x40020800
80034b4: 40020c00 .word 0x40020c00
80034b8: 40021000 .word 0x40021000
80034bc: 40021400 .word 0x40021400
80034c0: 40021800 .word 0x40021800
80034c4: 40013c00 .word 0x40013c00
080034c8 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
80034c8: b480 push {r7}
80034ca: b083 sub sp, #12
80034cc: af00 add r7, sp, #0
80034ce: 6078 str r0, [r7, #4]
80034d0: 460b mov r3, r1
80034d2: 807b strh r3, [r7, #2]
80034d4: 4613 mov r3, r2
80034d6: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if(PinState != GPIO_PIN_RESET)
80034d8: 787b ldrb r3, [r7, #1]
80034da: 2b00 cmp r3, #0
80034dc: d003 beq.n 80034e6 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = GPIO_Pin;
80034de: 887a ldrh r2, [r7, #2]
80034e0: 687b ldr r3, [r7, #4]
80034e2: 619a str r2, [r3, #24]
}
else
{
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
}
}
80034e4: e003 b.n 80034ee <HAL_GPIO_WritePin+0x26>
GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U;
80034e6: 887b ldrh r3, [r7, #2]
80034e8: 041a lsls r2, r3, #16
80034ea: 687b ldr r3, [r7, #4]
80034ec: 619a str r2, [r3, #24]
}
80034ee: bf00 nop
80034f0: 370c adds r7, #12
80034f2: 46bd mov sp, r7
80034f4: f85d 7b04 ldr.w r7, [sp], #4
80034f8: 4770 bx lr
...
080034fc <HAL_PWREx_EnableOverDrive>:
* During the Over-drive switch activation, no peripheral clocks should be enabled.
* The peripheral clocks must be enabled once the Over-drive mode is activated.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void)
{
80034fc: b580 push {r7, lr}
80034fe: b082 sub sp, #8
8003500: af00 add r7, sp, #0
uint32_t tickstart = 0U;
8003502: 2300 movs r3, #0
8003504: 607b str r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
8003506: 2300 movs r3, #0
8003508: 603b str r3, [r7, #0]
800350a: 4b20 ldr r3, [pc, #128] @ (800358c <HAL_PWREx_EnableOverDrive+0x90>)
800350c: 6c1b ldr r3, [r3, #64] @ 0x40
800350e: 4a1f ldr r2, [pc, #124] @ (800358c <HAL_PWREx_EnableOverDrive+0x90>)
8003510: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8003514: 6413 str r3, [r2, #64] @ 0x40
8003516: 4b1d ldr r3, [pc, #116] @ (800358c <HAL_PWREx_EnableOverDrive+0x90>)
8003518: 6c1b ldr r3, [r3, #64] @ 0x40
800351a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800351e: 603b str r3, [r7, #0]
8003520: 683b ldr r3, [r7, #0]
/* Enable the Over-drive to extend the clock frequency to 180 Mhz */
__HAL_PWR_OVERDRIVE_ENABLE();
8003522: 4b1b ldr r3, [pc, #108] @ (8003590 <HAL_PWREx_EnableOverDrive+0x94>)
8003524: 2201 movs r2, #1
8003526: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8003528: f7fe fb90 bl 8001c4c <HAL_GetTick>
800352c: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
800352e: e009 b.n 8003544 <HAL_PWREx_EnableOverDrive+0x48>
{
if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE)
8003530: f7fe fb8c bl 8001c4c <HAL_GetTick>
8003534: 4602 mov r2, r0
8003536: 687b ldr r3, [r7, #4]
8003538: 1ad3 subs r3, r2, r3
800353a: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
800353e: d901 bls.n 8003544 <HAL_PWREx_EnableOverDrive+0x48>
{
return HAL_TIMEOUT;
8003540: 2303 movs r3, #3
8003542: e01f b.n 8003584 <HAL_PWREx_EnableOverDrive+0x88>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY))
8003544: 4b13 ldr r3, [pc, #76] @ (8003594 <HAL_PWREx_EnableOverDrive+0x98>)
8003546: 685b ldr r3, [r3, #4]
8003548: f403 3380 and.w r3, r3, #65536 @ 0x10000
800354c: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8003550: d1ee bne.n 8003530 <HAL_PWREx_EnableOverDrive+0x34>
}
}
/* Enable the Over-drive switch */
__HAL_PWR_OVERDRIVESWITCHING_ENABLE();
8003552: 4b11 ldr r3, [pc, #68] @ (8003598 <HAL_PWREx_EnableOverDrive+0x9c>)
8003554: 2201 movs r2, #1
8003556: 601a str r2, [r3, #0]
/* Get tick */
tickstart = HAL_GetTick();
8003558: f7fe fb78 bl 8001c4c <HAL_GetTick>
800355c: 6078 str r0, [r7, #4]
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
800355e: e009 b.n 8003574 <HAL_PWREx_EnableOverDrive+0x78>
{
if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE)
8003560: f7fe fb74 bl 8001c4c <HAL_GetTick>
8003564: 4602 mov r2, r0
8003566: 687b ldr r3, [r7, #4]
8003568: 1ad3 subs r3, r2, r3
800356a: f5b3 7f7a cmp.w r3, #1000 @ 0x3e8
800356e: d901 bls.n 8003574 <HAL_PWREx_EnableOverDrive+0x78>
{
return HAL_TIMEOUT;
8003570: 2303 movs r3, #3
8003572: e007 b.n 8003584 <HAL_PWREx_EnableOverDrive+0x88>
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY))
8003574: 4b07 ldr r3, [pc, #28] @ (8003594 <HAL_PWREx_EnableOverDrive+0x98>)
8003576: 685b ldr r3, [r3, #4]
8003578: f403 3300 and.w r3, r3, #131072 @ 0x20000
800357c: f5b3 3f00 cmp.w r3, #131072 @ 0x20000
8003580: d1ee bne.n 8003560 <HAL_PWREx_EnableOverDrive+0x64>
}
}
return HAL_OK;
8003582: 2300 movs r3, #0
}
8003584: 4618 mov r0, r3
8003586: 3708 adds r7, #8
8003588: 46bd mov sp, r7
800358a: bd80 pop {r7, pc}
800358c: 40023800 .word 0x40023800
8003590: 420e0040 .word 0x420e0040
8003594: 40007000 .word 0x40007000
8003598: 420e0044 .word 0x420e0044
0800359c <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
800359c: b580 push {r7, lr}
800359e: b084 sub sp, #16
80035a0: af00 add r7, sp, #0
80035a2: 6078 str r0, [r7, #4]
80035a4: 6039 str r1, [r7, #0]
uint32_t tickstart;
/* Check Null pointer */
if(RCC_ClkInitStruct == NULL)
80035a6: 687b ldr r3, [r7, #4]
80035a8: 2b00 cmp r3, #0
80035aa: d101 bne.n 80035b0 <HAL_RCC_ClockConfig+0x14>
{
return HAL_ERROR;
80035ac: 2301 movs r3, #1
80035ae: e0cc b.n 800374a <HAL_RCC_ClockConfig+0x1ae>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if(FLatency > __HAL_FLASH_GET_LATENCY())
80035b0: 4b68 ldr r3, [pc, #416] @ (8003754 <HAL_RCC_ClockConfig+0x1b8>)
80035b2: 681b ldr r3, [r3, #0]
80035b4: f003 030f and.w r3, r3, #15
80035b8: 683a ldr r2, [r7, #0]
80035ba: 429a cmp r2, r3
80035bc: d90c bls.n 80035d8 <HAL_RCC_ClockConfig+0x3c>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80035be: 4b65 ldr r3, [pc, #404] @ (8003754 <HAL_RCC_ClockConfig+0x1b8>)
80035c0: 683a ldr r2, [r7, #0]
80035c2: b2d2 uxtb r2, r2
80035c4: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80035c6: 4b63 ldr r3, [pc, #396] @ (8003754 <HAL_RCC_ClockConfig+0x1b8>)
80035c8: 681b ldr r3, [r3, #0]
80035ca: f003 030f and.w r3, r3, #15
80035ce: 683a ldr r2, [r7, #0]
80035d0: 429a cmp r2, r3
80035d2: d001 beq.n 80035d8 <HAL_RCC_ClockConfig+0x3c>
{
return HAL_ERROR;
80035d4: 2301 movs r3, #1
80035d6: e0b8 b.n 800374a <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
80035d8: 687b ldr r3, [r7, #4]
80035da: 681b ldr r3, [r3, #0]
80035dc: f003 0302 and.w r3, r3, #2
80035e0: 2b00 cmp r3, #0
80035e2: d020 beq.n 8003626 <HAL_RCC_ClockConfig+0x8a>
{
/* Set the highest APBx dividers in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80035e4: 687b ldr r3, [r7, #4]
80035e6: 681b ldr r3, [r3, #0]
80035e8: f003 0304 and.w r3, r3, #4
80035ec: 2b00 cmp r3, #0
80035ee: d005 beq.n 80035fc <HAL_RCC_ClockConfig+0x60>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
80035f0: 4b59 ldr r3, [pc, #356] @ (8003758 <HAL_RCC_ClockConfig+0x1bc>)
80035f2: 689b ldr r3, [r3, #8]
80035f4: 4a58 ldr r2, [pc, #352] @ (8003758 <HAL_RCC_ClockConfig+0x1bc>)
80035f6: f443 53e0 orr.w r3, r3, #7168 @ 0x1c00
80035fa: 6093 str r3, [r2, #8]
}
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
80035fc: 687b ldr r3, [r7, #4]
80035fe: 681b ldr r3, [r3, #0]
8003600: f003 0308 and.w r3, r3, #8
8003604: 2b00 cmp r3, #0
8003606: d005 beq.n 8003614 <HAL_RCC_ClockConfig+0x78>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
8003608: 4b53 ldr r3, [pc, #332] @ (8003758 <HAL_RCC_ClockConfig+0x1bc>)
800360a: 689b ldr r3, [r3, #8]
800360c: 4a52 ldr r2, [pc, #328] @ (8003758 <HAL_RCC_ClockConfig+0x1bc>)
800360e: f443 4360 orr.w r3, r3, #57344 @ 0xe000
8003612: 6093 str r3, [r2, #8]
}
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8003614: 4b50 ldr r3, [pc, #320] @ (8003758 <HAL_RCC_ClockConfig+0x1bc>)
8003616: 689b ldr r3, [r3, #8]
8003618: f023 02f0 bic.w r2, r3, #240 @ 0xf0
800361c: 687b ldr r3, [r7, #4]
800361e: 689b ldr r3, [r3, #8]
8003620: 494d ldr r1, [pc, #308] @ (8003758 <HAL_RCC_ClockConfig+0x1bc>)
8003622: 4313 orrs r3, r2
8003624: 608b str r3, [r1, #8]
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8003626: 687b ldr r3, [r7, #4]
8003628: 681b ldr r3, [r3, #0]
800362a: f003 0301 and.w r3, r3, #1
800362e: 2b00 cmp r3, #0
8003630: d044 beq.n 80036bc <HAL_RCC_ClockConfig+0x120>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8003632: 687b ldr r3, [r7, #4]
8003634: 685b ldr r3, [r3, #4]
8003636: 2b01 cmp r3, #1
8003638: d107 bne.n 800364a <HAL_RCC_ClockConfig+0xae>
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
800363a: 4b47 ldr r3, [pc, #284] @ (8003758 <HAL_RCC_ClockConfig+0x1bc>)
800363c: 681b ldr r3, [r3, #0]
800363e: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003642: 2b00 cmp r3, #0
8003644: d119 bne.n 800367a <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8003646: 2301 movs r3, #1
8003648: e07f b.n 800374a <HAL_RCC_ClockConfig+0x1ae>
}
}
/* PLL is selected as System Clock Source */
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
800364a: 687b ldr r3, [r7, #4]
800364c: 685b ldr r3, [r3, #4]
800364e: 2b02 cmp r3, #2
8003650: d003 beq.n 800365a <HAL_RCC_ClockConfig+0xbe>
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
8003652: 687b ldr r3, [r7, #4]
8003654: 685b ldr r3, [r3, #4]
else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
8003656: 2b03 cmp r3, #3
8003658: d107 bne.n 800366a <HAL_RCC_ClockConfig+0xce>
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
800365a: 4b3f ldr r3, [pc, #252] @ (8003758 <HAL_RCC_ClockConfig+0x1bc>)
800365c: 681b ldr r3, [r3, #0]
800365e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8003662: 2b00 cmp r3, #0
8003664: d109 bne.n 800367a <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8003666: 2301 movs r3, #1
8003668: e06f b.n 800374a <HAL_RCC_ClockConfig+0x1ae>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
800366a: 4b3b ldr r3, [pc, #236] @ (8003758 <HAL_RCC_ClockConfig+0x1bc>)
800366c: 681b ldr r3, [r3, #0]
800366e: f003 0302 and.w r3, r3, #2
8003672: 2b00 cmp r3, #0
8003674: d101 bne.n 800367a <HAL_RCC_ClockConfig+0xde>
{
return HAL_ERROR;
8003676: 2301 movs r3, #1
8003678: e067 b.n 800374a <HAL_RCC_ClockConfig+0x1ae>
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
800367a: 4b37 ldr r3, [pc, #220] @ (8003758 <HAL_RCC_ClockConfig+0x1bc>)
800367c: 689b ldr r3, [r3, #8]
800367e: f023 0203 bic.w r2, r3, #3
8003682: 687b ldr r3, [r7, #4]
8003684: 685b ldr r3, [r3, #4]
8003686: 4934 ldr r1, [pc, #208] @ (8003758 <HAL_RCC_ClockConfig+0x1bc>)
8003688: 4313 orrs r3, r2
800368a: 608b str r3, [r1, #8]
/* Get Start Tick */
tickstart = HAL_GetTick();
800368c: f7fe fade bl 8001c4c <HAL_GetTick>
8003690: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8003692: e00a b.n 80036aa <HAL_RCC_ClockConfig+0x10e>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8003694: f7fe fada bl 8001c4c <HAL_GetTick>
8003698: 4602 mov r2, r0
800369a: 68fb ldr r3, [r7, #12]
800369c: 1ad3 subs r3, r2, r3
800369e: f241 3288 movw r2, #5000 @ 0x1388
80036a2: 4293 cmp r3, r2
80036a4: d901 bls.n 80036aa <HAL_RCC_ClockConfig+0x10e>
{
return HAL_TIMEOUT;
80036a6: 2303 movs r3, #3
80036a8: e04f b.n 800374a <HAL_RCC_ClockConfig+0x1ae>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80036aa: 4b2b ldr r3, [pc, #172] @ (8003758 <HAL_RCC_ClockConfig+0x1bc>)
80036ac: 689b ldr r3, [r3, #8]
80036ae: f003 020c and.w r2, r3, #12
80036b2: 687b ldr r3, [r7, #4]
80036b4: 685b ldr r3, [r3, #4]
80036b6: 009b lsls r3, r3, #2
80036b8: 429a cmp r2, r3
80036ba: d1eb bne.n 8003694 <HAL_RCC_ClockConfig+0xf8>
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < __HAL_FLASH_GET_LATENCY())
80036bc: 4b25 ldr r3, [pc, #148] @ (8003754 <HAL_RCC_ClockConfig+0x1b8>)
80036be: 681b ldr r3, [r3, #0]
80036c0: f003 030f and.w r3, r3, #15
80036c4: 683a ldr r2, [r7, #0]
80036c6: 429a cmp r2, r3
80036c8: d20c bcs.n 80036e4 <HAL_RCC_ClockConfig+0x148>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
80036ca: 4b22 ldr r3, [pc, #136] @ (8003754 <HAL_RCC_ClockConfig+0x1b8>)
80036cc: 683a ldr r2, [r7, #0]
80036ce: b2d2 uxtb r2, r2
80036d0: 701a strb r2, [r3, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if(__HAL_FLASH_GET_LATENCY() != FLatency)
80036d2: 4b20 ldr r3, [pc, #128] @ (8003754 <HAL_RCC_ClockConfig+0x1b8>)
80036d4: 681b ldr r3, [r3, #0]
80036d6: f003 030f and.w r3, r3, #15
80036da: 683a ldr r2, [r7, #0]
80036dc: 429a cmp r2, r3
80036de: d001 beq.n 80036e4 <HAL_RCC_ClockConfig+0x148>
{
return HAL_ERROR;
80036e0: 2301 movs r3, #1
80036e2: e032 b.n 800374a <HAL_RCC_ClockConfig+0x1ae>
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80036e4: 687b ldr r3, [r7, #4]
80036e6: 681b ldr r3, [r3, #0]
80036e8: f003 0304 and.w r3, r3, #4
80036ec: 2b00 cmp r3, #0
80036ee: d008 beq.n 8003702 <HAL_RCC_ClockConfig+0x166>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
80036f0: 4b19 ldr r3, [pc, #100] @ (8003758 <HAL_RCC_ClockConfig+0x1bc>)
80036f2: 689b ldr r3, [r3, #8]
80036f4: f423 52e0 bic.w r2, r3, #7168 @ 0x1c00
80036f8: 687b ldr r3, [r7, #4]
80036fa: 68db ldr r3, [r3, #12]
80036fc: 4916 ldr r1, [pc, #88] @ (8003758 <HAL_RCC_ClockConfig+0x1bc>)
80036fe: 4313 orrs r3, r2
8003700: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8003702: 687b ldr r3, [r7, #4]
8003704: 681b ldr r3, [r3, #0]
8003706: f003 0308 and.w r3, r3, #8
800370a: 2b00 cmp r3, #0
800370c: d009 beq.n 8003722 <HAL_RCC_ClockConfig+0x186>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
800370e: 4b12 ldr r3, [pc, #72] @ (8003758 <HAL_RCC_ClockConfig+0x1bc>)
8003710: 689b ldr r3, [r3, #8]
8003712: f423 4260 bic.w r2, r3, #57344 @ 0xe000
8003716: 687b ldr r3, [r7, #4]
8003718: 691b ldr r3, [r3, #16]
800371a: 00db lsls r3, r3, #3
800371c: 490e ldr r1, [pc, #56] @ (8003758 <HAL_RCC_ClockConfig+0x1bc>)
800371e: 4313 orrs r3, r2
8003720: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
8003722: f000 f887 bl 8003834 <HAL_RCC_GetSysClockFreq>
8003726: 4602 mov r2, r0
8003728: 4b0b ldr r3, [pc, #44] @ (8003758 <HAL_RCC_ClockConfig+0x1bc>)
800372a: 689b ldr r3, [r3, #8]
800372c: 091b lsrs r3, r3, #4
800372e: f003 030f and.w r3, r3, #15
8003732: 490a ldr r1, [pc, #40] @ (800375c <HAL_RCC_ClockConfig+0x1c0>)
8003734: 5ccb ldrb r3, [r1, r3]
8003736: fa22 f303 lsr.w r3, r2, r3
800373a: 4a09 ldr r2, [pc, #36] @ (8003760 <HAL_RCC_ClockConfig+0x1c4>)
800373c: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings */
HAL_InitTick (uwTickPrio);
800373e: 4b09 ldr r3, [pc, #36] @ (8003764 <HAL_RCC_ClockConfig+0x1c8>)
8003740: 681b ldr r3, [r3, #0]
8003742: 4618 mov r0, r3
8003744: f7fd feea bl 800151c <HAL_InitTick>
return HAL_OK;
8003748: 2300 movs r3, #0
}
800374a: 4618 mov r0, r3
800374c: 3710 adds r7, #16
800374e: 46bd mov sp, r7
8003750: bd80 pop {r7, pc}
8003752: bf00 nop
8003754: 40023c00 .word 0x40023c00
8003758: 40023800 .word 0x40023800
800375c: 08005a44 .word 0x08005a44
8003760: 20000008 .word 0x20000008
8003764: 2000000c .word 0x2000000c
08003768 <HAL_RCC_GetHCLKFreq>:
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8003768: b480 push {r7}
800376a: af00 add r7, sp, #0
return SystemCoreClock;
800376c: 4b03 ldr r3, [pc, #12] @ (800377c <HAL_RCC_GetHCLKFreq+0x14>)
800376e: 681b ldr r3, [r3, #0]
}
8003770: 4618 mov r0, r3
8003772: 46bd mov sp, r7
8003774: f85d 7b04 ldr.w r7, [sp], #4
8003778: 4770 bx lr
800377a: bf00 nop
800377c: 20000008 .word 0x20000008
08003780 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8003780: b580 push {r7, lr}
8003782: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
8003784: f7ff fff0 bl 8003768 <HAL_RCC_GetHCLKFreq>
8003788: 4602 mov r2, r0
800378a: 4b05 ldr r3, [pc, #20] @ (80037a0 <HAL_RCC_GetPCLK1Freq+0x20>)
800378c: 689b ldr r3, [r3, #8]
800378e: 0a9b lsrs r3, r3, #10
8003790: f003 0307 and.w r3, r3, #7
8003794: 4903 ldr r1, [pc, #12] @ (80037a4 <HAL_RCC_GetPCLK1Freq+0x24>)
8003796: 5ccb ldrb r3, [r1, r3]
8003798: fa22 f303 lsr.w r3, r2, r3
}
800379c: 4618 mov r0, r3
800379e: bd80 pop {r7, pc}
80037a0: 40023800 .word 0x40023800
80037a4: 08005a54 .word 0x08005a54
080037a8 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
80037a8: b580 push {r7, lr}
80037aa: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
80037ac: f7ff ffdc bl 8003768 <HAL_RCC_GetHCLKFreq>
80037b0: 4602 mov r2, r0
80037b2: 4b05 ldr r3, [pc, #20] @ (80037c8 <HAL_RCC_GetPCLK2Freq+0x20>)
80037b4: 689b ldr r3, [r3, #8]
80037b6: 0b5b lsrs r3, r3, #13
80037b8: f003 0307 and.w r3, r3, #7
80037bc: 4903 ldr r1, [pc, #12] @ (80037cc <HAL_RCC_GetPCLK2Freq+0x24>)
80037be: 5ccb ldrb r3, [r1, r3]
80037c0: fa22 f303 lsr.w r3, r2, r3
}
80037c4: 4618 mov r0, r3
80037c6: bd80 pop {r7, pc}
80037c8: 40023800 .word 0x40023800
80037cc: 08005a54 .word 0x08005a54
080037d0 <HAL_RCC_GetClockConfig>:
* will be configured.
* @param pFLatency Pointer on the Flash Latency.
* @retval None
*/
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
80037d0: b480 push {r7}
80037d2: b083 sub sp, #12
80037d4: af00 add r7, sp, #0
80037d6: 6078 str r0, [r7, #4]
80037d8: 6039 str r1, [r7, #0]
/* Set all possible values for the Clock type parameter --------------------*/
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
80037da: 687b ldr r3, [r7, #4]
80037dc: 220f movs r2, #15
80037de: 601a str r2, [r3, #0]
/* Get the SYSCLK configuration --------------------------------------------*/
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
80037e0: 4b12 ldr r3, [pc, #72] @ (800382c <HAL_RCC_GetClockConfig+0x5c>)
80037e2: 689b ldr r3, [r3, #8]
80037e4: f003 0203 and.w r2, r3, #3
80037e8: 687b ldr r3, [r7, #4]
80037ea: 605a str r2, [r3, #4]
/* Get the HCLK configuration ----------------------------------------------*/
RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
80037ec: 4b0f ldr r3, [pc, #60] @ (800382c <HAL_RCC_GetClockConfig+0x5c>)
80037ee: 689b ldr r3, [r3, #8]
80037f0: f003 02f0 and.w r2, r3, #240 @ 0xf0
80037f4: 687b ldr r3, [r7, #4]
80037f6: 609a str r2, [r3, #8]
/* Get the APB1 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
80037f8: 4b0c ldr r3, [pc, #48] @ (800382c <HAL_RCC_GetClockConfig+0x5c>)
80037fa: 689b ldr r3, [r3, #8]
80037fc: f403 52e0 and.w r2, r3, #7168 @ 0x1c00
8003800: 687b ldr r3, [r7, #4]
8003802: 60da str r2, [r3, #12]
/* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
8003804: 4b09 ldr r3, [pc, #36] @ (800382c <HAL_RCC_GetClockConfig+0x5c>)
8003806: 689b ldr r3, [r3, #8]
8003808: 08db lsrs r3, r3, #3
800380a: f403 52e0 and.w r2, r3, #7168 @ 0x1c00
800380e: 687b ldr r3, [r7, #4]
8003810: 611a str r2, [r3, #16]
/* Get the Flash Wait State (Latency) configuration ------------------------*/
*pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
8003812: 4b07 ldr r3, [pc, #28] @ (8003830 <HAL_RCC_GetClockConfig+0x60>)
8003814: 681b ldr r3, [r3, #0]
8003816: f003 020f and.w r2, r3, #15
800381a: 683b ldr r3, [r7, #0]
800381c: 601a str r2, [r3, #0]
}
800381e: bf00 nop
8003820: 370c adds r7, #12
8003822: 46bd mov sp, r7
8003824: f85d 7b04 ldr.w r7, [sp], #4
8003828: 4770 bx lr
800382a: bf00 nop
800382c: 40023800 .word 0x40023800
8003830: 40023c00 .word 0x40023c00
08003834 <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8003834: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8003838: b0ae sub sp, #184 @ 0xb8
800383a: af00 add r7, sp, #0
uint32_t pllm = 0U;
800383c: 2300 movs r3, #0
800383e: f8c7 30ac str.w r3, [r7, #172] @ 0xac
uint32_t pllvco = 0U;
8003842: 2300 movs r3, #0
8003844: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
uint32_t pllp = 0U;
8003848: 2300 movs r3, #0
800384a: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
uint32_t pllr = 0U;
800384e: 2300 movs r3, #0
8003850: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
uint32_t sysclockfreq = 0U;
8003854: 2300 movs r3, #0
8003856: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
/* Get SYSCLK source -------------------------------------------------------*/
switch (RCC->CFGR & RCC_CFGR_SWS)
800385a: 4bcb ldr r3, [pc, #812] @ (8003b88 <HAL_RCC_GetSysClockFreq+0x354>)
800385c: 689b ldr r3, [r3, #8]
800385e: f003 030c and.w r3, r3, #12
8003862: 2b0c cmp r3, #12
8003864: f200 8206 bhi.w 8003c74 <HAL_RCC_GetSysClockFreq+0x440>
8003868: a201 add r2, pc, #4 @ (adr r2, 8003870 <HAL_RCC_GetSysClockFreq+0x3c>)
800386a: f852 f023 ldr.w pc, [r2, r3, lsl #2]
800386e: bf00 nop
8003870: 080038a5 .word 0x080038a5
8003874: 08003c75 .word 0x08003c75
8003878: 08003c75 .word 0x08003c75
800387c: 08003c75 .word 0x08003c75
8003880: 080038ad .word 0x080038ad
8003884: 08003c75 .word 0x08003c75
8003888: 08003c75 .word 0x08003c75
800388c: 08003c75 .word 0x08003c75
8003890: 080038b5 .word 0x080038b5
8003894: 08003c75 .word 0x08003c75
8003898: 08003c75 .word 0x08003c75
800389c: 08003c75 .word 0x08003c75
80038a0: 08003aa5 .word 0x08003aa5
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
{
sysclockfreq = HSI_VALUE;
80038a4: 4bb9 ldr r3, [pc, #740] @ (8003b8c <HAL_RCC_GetSysClockFreq+0x358>)
80038a6: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
break;
80038aa: e1e7 b.n 8003c7c <HAL_RCC_GetSysClockFreq+0x448>
}
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
{
sysclockfreq = HSE_VALUE;
80038ac: 4bb8 ldr r3, [pc, #736] @ (8003b90 <HAL_RCC_GetSysClockFreq+0x35c>)
80038ae: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
break;
80038b2: e1e3 b.n 8003c7c <HAL_RCC_GetSysClockFreq+0x448>
}
case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLP */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
80038b4: 4bb4 ldr r3, [pc, #720] @ (8003b88 <HAL_RCC_GetSysClockFreq+0x354>)
80038b6: 685b ldr r3, [r3, #4]
80038b8: f003 033f and.w r3, r3, #63 @ 0x3f
80038bc: f8c7 30ac str.w r3, [r7, #172] @ 0xac
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
80038c0: 4bb1 ldr r3, [pc, #708] @ (8003b88 <HAL_RCC_GetSysClockFreq+0x354>)
80038c2: 685b ldr r3, [r3, #4]
80038c4: f403 0380 and.w r3, r3, #4194304 @ 0x400000
80038c8: 2b00 cmp r3, #0
80038ca: d071 beq.n 80039b0 <HAL_RCC_GetSysClockFreq+0x17c>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
80038cc: 4bae ldr r3, [pc, #696] @ (8003b88 <HAL_RCC_GetSysClockFreq+0x354>)
80038ce: 685b ldr r3, [r3, #4]
80038d0: 099b lsrs r3, r3, #6
80038d2: 2200 movs r2, #0
80038d4: f8c7 3098 str.w r3, [r7, #152] @ 0x98
80038d8: f8c7 209c str.w r2, [r7, #156] @ 0x9c
80038dc: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
80038e0: f3c3 0308 ubfx r3, r3, #0, #9
80038e4: f8c7 3090 str.w r3, [r7, #144] @ 0x90
80038e8: 2300 movs r3, #0
80038ea: f8c7 3094 str.w r3, [r7, #148] @ 0x94
80038ee: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90
80038f2: 4622 mov r2, r4
80038f4: 462b mov r3, r5
80038f6: f04f 0000 mov.w r0, #0
80038fa: f04f 0100 mov.w r1, #0
80038fe: 0159 lsls r1, r3, #5
8003900: ea41 61d2 orr.w r1, r1, r2, lsr #27
8003904: 0150 lsls r0, r2, #5
8003906: 4602 mov r2, r0
8003908: 460b mov r3, r1
800390a: 4621 mov r1, r4
800390c: 1a51 subs r1, r2, r1
800390e: 6439 str r1, [r7, #64] @ 0x40
8003910: 4629 mov r1, r5
8003912: eb63 0301 sbc.w r3, r3, r1
8003916: 647b str r3, [r7, #68] @ 0x44
8003918: f04f 0200 mov.w r2, #0
800391c: f04f 0300 mov.w r3, #0
8003920: e9d7 8910 ldrd r8, r9, [r7, #64] @ 0x40
8003924: 4649 mov r1, r9
8003926: 018b lsls r3, r1, #6
8003928: 4641 mov r1, r8
800392a: ea43 6391 orr.w r3, r3, r1, lsr #26
800392e: 4641 mov r1, r8
8003930: 018a lsls r2, r1, #6
8003932: 4641 mov r1, r8
8003934: 1a51 subs r1, r2, r1
8003936: 63b9 str r1, [r7, #56] @ 0x38
8003938: 4649 mov r1, r9
800393a: eb63 0301 sbc.w r3, r3, r1
800393e: 63fb str r3, [r7, #60] @ 0x3c
8003940: f04f 0200 mov.w r2, #0
8003944: f04f 0300 mov.w r3, #0
8003948: e9d7 890e ldrd r8, r9, [r7, #56] @ 0x38
800394c: 4649 mov r1, r9
800394e: 00cb lsls r3, r1, #3
8003950: 4641 mov r1, r8
8003952: ea43 7351 orr.w r3, r3, r1, lsr #29
8003956: 4641 mov r1, r8
8003958: 00ca lsls r2, r1, #3
800395a: 4610 mov r0, r2
800395c: 4619 mov r1, r3
800395e: 4603 mov r3, r0
8003960: 4622 mov r2, r4
8003962: 189b adds r3, r3, r2
8003964: 633b str r3, [r7, #48] @ 0x30
8003966: 462b mov r3, r5
8003968: 460a mov r2, r1
800396a: eb42 0303 adc.w r3, r2, r3
800396e: 637b str r3, [r7, #52] @ 0x34
8003970: f04f 0200 mov.w r2, #0
8003974: f04f 0300 mov.w r3, #0
8003978: e9d7 450c ldrd r4, r5, [r7, #48] @ 0x30
800397c: 4629 mov r1, r5
800397e: 024b lsls r3, r1, #9
8003980: 4621 mov r1, r4
8003982: ea43 53d1 orr.w r3, r3, r1, lsr #23
8003986: 4621 mov r1, r4
8003988: 024a lsls r2, r1, #9
800398a: 4610 mov r0, r2
800398c: 4619 mov r1, r3
800398e: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8003992: 2200 movs r2, #0
8003994: f8c7 3088 str.w r3, [r7, #136] @ 0x88
8003998: f8c7 208c str.w r2, [r7, #140] @ 0x8c
800399c: e9d7 2322 ldrd r2, r3, [r7, #136] @ 0x88
80039a0: f7fc fc30 bl 8000204 <__aeabi_uldivmod>
80039a4: 4602 mov r2, r0
80039a6: 460b mov r3, r1
80039a8: 4613 mov r3, r2
80039aa: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
80039ae: e067 b.n 8003a80 <HAL_RCC_GetSysClockFreq+0x24c>
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
80039b0: 4b75 ldr r3, [pc, #468] @ (8003b88 <HAL_RCC_GetSysClockFreq+0x354>)
80039b2: 685b ldr r3, [r3, #4]
80039b4: 099b lsrs r3, r3, #6
80039b6: 2200 movs r2, #0
80039b8: f8c7 3080 str.w r3, [r7, #128] @ 0x80
80039bc: f8c7 2084 str.w r2, [r7, #132] @ 0x84
80039c0: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
80039c4: f3c3 0308 ubfx r3, r3, #0, #9
80039c8: 67bb str r3, [r7, #120] @ 0x78
80039ca: 2300 movs r3, #0
80039cc: 67fb str r3, [r7, #124] @ 0x7c
80039ce: e9d7 451e ldrd r4, r5, [r7, #120] @ 0x78
80039d2: 4622 mov r2, r4
80039d4: 462b mov r3, r5
80039d6: f04f 0000 mov.w r0, #0
80039da: f04f 0100 mov.w r1, #0
80039de: 0159 lsls r1, r3, #5
80039e0: ea41 61d2 orr.w r1, r1, r2, lsr #27
80039e4: 0150 lsls r0, r2, #5
80039e6: 4602 mov r2, r0
80039e8: 460b mov r3, r1
80039ea: 4621 mov r1, r4
80039ec: 1a51 subs r1, r2, r1
80039ee: 62b9 str r1, [r7, #40] @ 0x28
80039f0: 4629 mov r1, r5
80039f2: eb63 0301 sbc.w r3, r3, r1
80039f6: 62fb str r3, [r7, #44] @ 0x2c
80039f8: f04f 0200 mov.w r2, #0
80039fc: f04f 0300 mov.w r3, #0
8003a00: e9d7 890a ldrd r8, r9, [r7, #40] @ 0x28
8003a04: 4649 mov r1, r9
8003a06: 018b lsls r3, r1, #6
8003a08: 4641 mov r1, r8
8003a0a: ea43 6391 orr.w r3, r3, r1, lsr #26
8003a0e: 4641 mov r1, r8
8003a10: 018a lsls r2, r1, #6
8003a12: 4641 mov r1, r8
8003a14: ebb2 0a01 subs.w sl, r2, r1
8003a18: 4649 mov r1, r9
8003a1a: eb63 0b01 sbc.w fp, r3, r1
8003a1e: f04f 0200 mov.w r2, #0
8003a22: f04f 0300 mov.w r3, #0
8003a26: ea4f 03cb mov.w r3, fp, lsl #3
8003a2a: ea43 735a orr.w r3, r3, sl, lsr #29
8003a2e: ea4f 02ca mov.w r2, sl, lsl #3
8003a32: 4692 mov sl, r2
8003a34: 469b mov fp, r3
8003a36: 4623 mov r3, r4
8003a38: eb1a 0303 adds.w r3, sl, r3
8003a3c: 623b str r3, [r7, #32]
8003a3e: 462b mov r3, r5
8003a40: eb4b 0303 adc.w r3, fp, r3
8003a44: 627b str r3, [r7, #36] @ 0x24
8003a46: f04f 0200 mov.w r2, #0
8003a4a: f04f 0300 mov.w r3, #0
8003a4e: e9d7 4508 ldrd r4, r5, [r7, #32]
8003a52: 4629 mov r1, r5
8003a54: 028b lsls r3, r1, #10
8003a56: 4621 mov r1, r4
8003a58: ea43 5391 orr.w r3, r3, r1, lsr #22
8003a5c: 4621 mov r1, r4
8003a5e: 028a lsls r2, r1, #10
8003a60: 4610 mov r0, r2
8003a62: 4619 mov r1, r3
8003a64: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8003a68: 2200 movs r2, #0
8003a6a: 673b str r3, [r7, #112] @ 0x70
8003a6c: 677a str r2, [r7, #116] @ 0x74
8003a6e: e9d7 231c ldrd r2, r3, [r7, #112] @ 0x70
8003a72: f7fc fbc7 bl 8000204 <__aeabi_uldivmod>
8003a76: 4602 mov r2, r0
8003a78: 460b mov r3, r1
8003a7a: 4613 mov r3, r2
8003a7c: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
}
pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
8003a80: 4b41 ldr r3, [pc, #260] @ (8003b88 <HAL_RCC_GetSysClockFreq+0x354>)
8003a82: 685b ldr r3, [r3, #4]
8003a84: 0c1b lsrs r3, r3, #16
8003a86: f003 0303 and.w r3, r3, #3
8003a8a: 3301 adds r3, #1
8003a8c: 005b lsls r3, r3, #1
8003a8e: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
sysclockfreq = pllvco/pllp;
8003a92: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
8003a96: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8003a9a: fbb2 f3f3 udiv r3, r2, r3
8003a9e: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
break;
8003aa2: e0eb b.n 8003c7c <HAL_RCC_GetSysClockFreq+0x448>
}
case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */
{
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR */
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
8003aa4: 4b38 ldr r3, [pc, #224] @ (8003b88 <HAL_RCC_GetSysClockFreq+0x354>)
8003aa6: 685b ldr r3, [r3, #4]
8003aa8: f003 033f and.w r3, r3, #63 @ 0x3f
8003aac: f8c7 30ac str.w r3, [r7, #172] @ 0xac
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
8003ab0: 4b35 ldr r3, [pc, #212] @ (8003b88 <HAL_RCC_GetSysClockFreq+0x354>)
8003ab2: 685b ldr r3, [r3, #4]
8003ab4: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8003ab8: 2b00 cmp r3, #0
8003aba: d06b beq.n 8003b94 <HAL_RCC_GetSysClockFreq+0x360>
{
/* HSE used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8003abc: 4b32 ldr r3, [pc, #200] @ (8003b88 <HAL_RCC_GetSysClockFreq+0x354>)
8003abe: 685b ldr r3, [r3, #4]
8003ac0: 099b lsrs r3, r3, #6
8003ac2: 2200 movs r2, #0
8003ac4: 66bb str r3, [r7, #104] @ 0x68
8003ac6: 66fa str r2, [r7, #108] @ 0x6c
8003ac8: 6ebb ldr r3, [r7, #104] @ 0x68
8003aca: f3c3 0308 ubfx r3, r3, #0, #9
8003ace: 663b str r3, [r7, #96] @ 0x60
8003ad0: 2300 movs r3, #0
8003ad2: 667b str r3, [r7, #100] @ 0x64
8003ad4: e9d7 4518 ldrd r4, r5, [r7, #96] @ 0x60
8003ad8: 4622 mov r2, r4
8003ada: 462b mov r3, r5
8003adc: f04f 0000 mov.w r0, #0
8003ae0: f04f 0100 mov.w r1, #0
8003ae4: 0159 lsls r1, r3, #5
8003ae6: ea41 61d2 orr.w r1, r1, r2, lsr #27
8003aea: 0150 lsls r0, r2, #5
8003aec: 4602 mov r2, r0
8003aee: 460b mov r3, r1
8003af0: 4621 mov r1, r4
8003af2: 1a51 subs r1, r2, r1
8003af4: 61b9 str r1, [r7, #24]
8003af6: 4629 mov r1, r5
8003af8: eb63 0301 sbc.w r3, r3, r1
8003afc: 61fb str r3, [r7, #28]
8003afe: f04f 0200 mov.w r2, #0
8003b02: f04f 0300 mov.w r3, #0
8003b06: e9d7 ab06 ldrd sl, fp, [r7, #24]
8003b0a: 4659 mov r1, fp
8003b0c: 018b lsls r3, r1, #6
8003b0e: 4651 mov r1, sl
8003b10: ea43 6391 orr.w r3, r3, r1, lsr #26
8003b14: 4651 mov r1, sl
8003b16: 018a lsls r2, r1, #6
8003b18: 4651 mov r1, sl
8003b1a: ebb2 0801 subs.w r8, r2, r1
8003b1e: 4659 mov r1, fp
8003b20: eb63 0901 sbc.w r9, r3, r1
8003b24: f04f 0200 mov.w r2, #0
8003b28: f04f 0300 mov.w r3, #0
8003b2c: ea4f 03c9 mov.w r3, r9, lsl #3
8003b30: ea43 7358 orr.w r3, r3, r8, lsr #29
8003b34: ea4f 02c8 mov.w r2, r8, lsl #3
8003b38: 4690 mov r8, r2
8003b3a: 4699 mov r9, r3
8003b3c: 4623 mov r3, r4
8003b3e: eb18 0303 adds.w r3, r8, r3
8003b42: 613b str r3, [r7, #16]
8003b44: 462b mov r3, r5
8003b46: eb49 0303 adc.w r3, r9, r3
8003b4a: 617b str r3, [r7, #20]
8003b4c: f04f 0200 mov.w r2, #0
8003b50: f04f 0300 mov.w r3, #0
8003b54: e9d7 4504 ldrd r4, r5, [r7, #16]
8003b58: 4629 mov r1, r5
8003b5a: 024b lsls r3, r1, #9
8003b5c: 4621 mov r1, r4
8003b5e: ea43 53d1 orr.w r3, r3, r1, lsr #23
8003b62: 4621 mov r1, r4
8003b64: 024a lsls r2, r1, #9
8003b66: 4610 mov r0, r2
8003b68: 4619 mov r1, r3
8003b6a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8003b6e: 2200 movs r2, #0
8003b70: 65bb str r3, [r7, #88] @ 0x58
8003b72: 65fa str r2, [r7, #92] @ 0x5c
8003b74: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58
8003b78: f7fc fb44 bl 8000204 <__aeabi_uldivmod>
8003b7c: 4602 mov r2, r0
8003b7e: 460b mov r3, r1
8003b80: 4613 mov r3, r2
8003b82: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
8003b86: e065 b.n 8003c54 <HAL_RCC_GetSysClockFreq+0x420>
8003b88: 40023800 .word 0x40023800
8003b8c: 00f42400 .word 0x00f42400
8003b90: 007a1200 .word 0x007a1200
}
else
{
/* HSI used as PLL clock source */
pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
8003b94: 4b3d ldr r3, [pc, #244] @ (8003c8c <HAL_RCC_GetSysClockFreq+0x458>)
8003b96: 685b ldr r3, [r3, #4]
8003b98: 099b lsrs r3, r3, #6
8003b9a: 2200 movs r2, #0
8003b9c: 4618 mov r0, r3
8003b9e: 4611 mov r1, r2
8003ba0: f3c0 0308 ubfx r3, r0, #0, #9
8003ba4: 653b str r3, [r7, #80] @ 0x50
8003ba6: 2300 movs r3, #0
8003ba8: 657b str r3, [r7, #84] @ 0x54
8003baa: e9d7 8914 ldrd r8, r9, [r7, #80] @ 0x50
8003bae: 4642 mov r2, r8
8003bb0: 464b mov r3, r9
8003bb2: f04f 0000 mov.w r0, #0
8003bb6: f04f 0100 mov.w r1, #0
8003bba: 0159 lsls r1, r3, #5
8003bbc: ea41 61d2 orr.w r1, r1, r2, lsr #27
8003bc0: 0150 lsls r0, r2, #5
8003bc2: 4602 mov r2, r0
8003bc4: 460b mov r3, r1
8003bc6: 4641 mov r1, r8
8003bc8: 1a51 subs r1, r2, r1
8003bca: 60b9 str r1, [r7, #8]
8003bcc: 4649 mov r1, r9
8003bce: eb63 0301 sbc.w r3, r3, r1
8003bd2: 60fb str r3, [r7, #12]
8003bd4: f04f 0200 mov.w r2, #0
8003bd8: f04f 0300 mov.w r3, #0
8003bdc: e9d7 ab02 ldrd sl, fp, [r7, #8]
8003be0: 4659 mov r1, fp
8003be2: 018b lsls r3, r1, #6
8003be4: 4651 mov r1, sl
8003be6: ea43 6391 orr.w r3, r3, r1, lsr #26
8003bea: 4651 mov r1, sl
8003bec: 018a lsls r2, r1, #6
8003bee: 4651 mov r1, sl
8003bf0: 1a54 subs r4, r2, r1
8003bf2: 4659 mov r1, fp
8003bf4: eb63 0501 sbc.w r5, r3, r1
8003bf8: f04f 0200 mov.w r2, #0
8003bfc: f04f 0300 mov.w r3, #0
8003c00: 00eb lsls r3, r5, #3
8003c02: ea43 7354 orr.w r3, r3, r4, lsr #29
8003c06: 00e2 lsls r2, r4, #3
8003c08: 4614 mov r4, r2
8003c0a: 461d mov r5, r3
8003c0c: 4643 mov r3, r8
8003c0e: 18e3 adds r3, r4, r3
8003c10: 603b str r3, [r7, #0]
8003c12: 464b mov r3, r9
8003c14: eb45 0303 adc.w r3, r5, r3
8003c18: 607b str r3, [r7, #4]
8003c1a: f04f 0200 mov.w r2, #0
8003c1e: f04f 0300 mov.w r3, #0
8003c22: e9d7 4500 ldrd r4, r5, [r7]
8003c26: 4629 mov r1, r5
8003c28: 028b lsls r3, r1, #10
8003c2a: 4621 mov r1, r4
8003c2c: ea43 5391 orr.w r3, r3, r1, lsr #22
8003c30: 4621 mov r1, r4
8003c32: 028a lsls r2, r1, #10
8003c34: 4610 mov r0, r2
8003c36: 4619 mov r1, r3
8003c38: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
8003c3c: 2200 movs r2, #0
8003c3e: 64bb str r3, [r7, #72] @ 0x48
8003c40: 64fa str r2, [r7, #76] @ 0x4c
8003c42: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48
8003c46: f7fc fadd bl 8000204 <__aeabi_uldivmod>
8003c4a: 4602 mov r2, r0
8003c4c: 460b mov r3, r1
8003c4e: 4613 mov r3, r2
8003c50: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
}
pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);
8003c54: 4b0d ldr r3, [pc, #52] @ (8003c8c <HAL_RCC_GetSysClockFreq+0x458>)
8003c56: 685b ldr r3, [r3, #4]
8003c58: 0f1b lsrs r3, r3, #28
8003c5a: f003 0307 and.w r3, r3, #7
8003c5e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
sysclockfreq = pllvco/pllr;
8003c62: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
8003c66: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
8003c6a: fbb2 f3f3 udiv r3, r2, r3
8003c6e: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
break;
8003c72: e003 b.n 8003c7c <HAL_RCC_GetSysClockFreq+0x448>
}
default:
{
sysclockfreq = HSI_VALUE;
8003c74: 4b06 ldr r3, [pc, #24] @ (8003c90 <HAL_RCC_GetSysClockFreq+0x45c>)
8003c76: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
break;
8003c7a: bf00 nop
}
}
return sysclockfreq;
8003c7c: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0
}
8003c80: 4618 mov r0, r3
8003c82: 37b8 adds r7, #184 @ 0xb8
8003c84: 46bd mov sp, r7
8003c86: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
8003c8a: bf00 nop
8003c8c: 40023800 .word 0x40023800
8003c90: 00f42400 .word 0x00f42400
08003c94 <HAL_RCC_OscConfig>:
* @note This function add the PLL/PLLR factor management during PLL configuration this feature
* is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
8003c94: b580 push {r7, lr}
8003c96: b086 sub sp, #24
8003c98: af00 add r7, sp, #0
8003c9a: 6078 str r0, [r7, #4]
uint32_t tickstart, pll_config;
/* Check Null pointer */
if(RCC_OscInitStruct == NULL)
8003c9c: 687b ldr r3, [r7, #4]
8003c9e: 2b00 cmp r3, #0
8003ca0: d101 bne.n 8003ca6 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
8003ca2: 2301 movs r3, #1
8003ca4: e28d b.n 80041c2 <HAL_RCC_OscConfig+0x52e>
}
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8003ca6: 687b ldr r3, [r7, #4]
8003ca8: 681b ldr r3, [r3, #0]
8003caa: f003 0301 and.w r3, r3, #1
8003cae: 2b00 cmp r3, #0
8003cb0: f000 8083 beq.w 8003dba <HAL_RCC_OscConfig+0x126>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
#if defined(STM32F446xx)
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
8003cb4: 4b94 ldr r3, [pc, #592] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003cb6: 689b ldr r3, [r3, #8]
8003cb8: f003 030c and.w r3, r3, #12
8003cbc: 2b04 cmp r3, #4
8003cbe: d019 beq.n 8003cf4 <HAL_RCC_OscConfig+0x60>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\
8003cc0: 4b91 ldr r3, [pc, #580] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003cc2: 689b ldr r3, [r3, #8]
8003cc4: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
8003cc8: 2b08 cmp r3, #8
8003cca: d106 bne.n 8003cda <HAL_RCC_OscConfig+0x46>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\
8003ccc: 4b8e ldr r3, [pc, #568] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003cce: 685b ldr r3, [r3, #4]
8003cd0: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8003cd4: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
8003cd8: d00c beq.n 8003cf4 <HAL_RCC_OscConfig+0x60>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
8003cda: 4b8b ldr r3, [pc, #556] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003cdc: 689b ldr r3, [r3, #8]
8003cde: f003 030c and.w r3, r3, #12
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) ||\
8003ce2: 2b0c cmp r3, #12
8003ce4: d112 bne.n 8003d0c <HAL_RCC_OscConfig+0x78>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
8003ce6: 4b88 ldr r3, [pc, #544] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003ce8: 685b ldr r3, [r3, #4]
8003cea: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8003cee: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
8003cf2: d10b bne.n 8003d0c <HAL_RCC_OscConfig+0x78>
#else
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
#endif /* STM32F446xx */
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8003cf4: 4b84 ldr r3, [pc, #528] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003cf6: 681b ldr r3, [r3, #0]
8003cf8: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003cfc: 2b00 cmp r3, #0
8003cfe: d05b beq.n 8003db8 <HAL_RCC_OscConfig+0x124>
8003d00: 687b ldr r3, [r7, #4]
8003d02: 685b ldr r3, [r3, #4]
8003d04: 2b00 cmp r3, #0
8003d06: d157 bne.n 8003db8 <HAL_RCC_OscConfig+0x124>
{
return HAL_ERROR;
8003d08: 2301 movs r3, #1
8003d0a: e25a b.n 80041c2 <HAL_RCC_OscConfig+0x52e>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
8003d0c: 687b ldr r3, [r7, #4]
8003d0e: 685b ldr r3, [r3, #4]
8003d10: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8003d14: d106 bne.n 8003d24 <HAL_RCC_OscConfig+0x90>
8003d16: 4b7c ldr r3, [pc, #496] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003d18: 681b ldr r3, [r3, #0]
8003d1a: 4a7b ldr r2, [pc, #492] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003d1c: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8003d20: 6013 str r3, [r2, #0]
8003d22: e01d b.n 8003d60 <HAL_RCC_OscConfig+0xcc>
8003d24: 687b ldr r3, [r7, #4]
8003d26: 685b ldr r3, [r3, #4]
8003d28: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
8003d2c: d10c bne.n 8003d48 <HAL_RCC_OscConfig+0xb4>
8003d2e: 4b76 ldr r3, [pc, #472] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003d30: 681b ldr r3, [r3, #0]
8003d32: 4a75 ldr r2, [pc, #468] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003d34: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8003d38: 6013 str r3, [r2, #0]
8003d3a: 4b73 ldr r3, [pc, #460] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003d3c: 681b ldr r3, [r3, #0]
8003d3e: 4a72 ldr r2, [pc, #456] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003d40: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8003d44: 6013 str r3, [r2, #0]
8003d46: e00b b.n 8003d60 <HAL_RCC_OscConfig+0xcc>
8003d48: 4b6f ldr r3, [pc, #444] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003d4a: 681b ldr r3, [r3, #0]
8003d4c: 4a6e ldr r2, [pc, #440] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003d4e: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8003d52: 6013 str r3, [r2, #0]
8003d54: 4b6c ldr r3, [pc, #432] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003d56: 681b ldr r3, [r3, #0]
8003d58: 4a6b ldr r2, [pc, #428] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003d5a: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8003d5e: 6013 str r3, [r2, #0]
/* Check the HSE State */
if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
8003d60: 687b ldr r3, [r7, #4]
8003d62: 685b ldr r3, [r3, #4]
8003d64: 2b00 cmp r3, #0
8003d66: d013 beq.n 8003d90 <HAL_RCC_OscConfig+0xfc>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003d68: f7fd ff70 bl 8001c4c <HAL_GetTick>
8003d6c: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8003d6e: e008 b.n 8003d82 <HAL_RCC_OscConfig+0xee>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8003d70: f7fd ff6c bl 8001c4c <HAL_GetTick>
8003d74: 4602 mov r2, r0
8003d76: 693b ldr r3, [r7, #16]
8003d78: 1ad3 subs r3, r2, r3
8003d7a: 2b64 cmp r3, #100 @ 0x64
8003d7c: d901 bls.n 8003d82 <HAL_RCC_OscConfig+0xee>
{
return HAL_TIMEOUT;
8003d7e: 2303 movs r3, #3
8003d80: e21f b.n 80041c2 <HAL_RCC_OscConfig+0x52e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
8003d82: 4b61 ldr r3, [pc, #388] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003d84: 681b ldr r3, [r3, #0]
8003d86: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003d8a: 2b00 cmp r3, #0
8003d8c: d0f0 beq.n 8003d70 <HAL_RCC_OscConfig+0xdc>
8003d8e: e014 b.n 8003dba <HAL_RCC_OscConfig+0x126>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003d90: f7fd ff5c bl 8001c4c <HAL_GetTick>
8003d94: 6138 str r0, [r7, #16]
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8003d96: e008 b.n 8003daa <HAL_RCC_OscConfig+0x116>
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
8003d98: f7fd ff58 bl 8001c4c <HAL_GetTick>
8003d9c: 4602 mov r2, r0
8003d9e: 693b ldr r3, [r7, #16]
8003da0: 1ad3 subs r3, r2, r3
8003da2: 2b64 cmp r3, #100 @ 0x64
8003da4: d901 bls.n 8003daa <HAL_RCC_OscConfig+0x116>
{
return HAL_TIMEOUT;
8003da6: 2303 movs r3, #3
8003da8: e20b b.n 80041c2 <HAL_RCC_OscConfig+0x52e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
8003daa: 4b57 ldr r3, [pc, #348] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003dac: 681b ldr r3, [r3, #0]
8003dae: f403 3300 and.w r3, r3, #131072 @ 0x20000
8003db2: 2b00 cmp r3, #0
8003db4: d1f0 bne.n 8003d98 <HAL_RCC_OscConfig+0x104>
8003db6: e000 b.n 8003dba <HAL_RCC_OscConfig+0x126>
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8003db8: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
8003dba: 687b ldr r3, [r7, #4]
8003dbc: 681b ldr r3, [r3, #0]
8003dbe: f003 0302 and.w r3, r3, #2
8003dc2: 2b00 cmp r3, #0
8003dc4: d06f beq.n 8003ea6 <HAL_RCC_OscConfig+0x212>
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
#if defined(STM32F446xx)
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
8003dc6: 4b50 ldr r3, [pc, #320] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003dc8: 689b ldr r3, [r3, #8]
8003dca: f003 030c and.w r3, r3, #12
8003dce: 2b00 cmp r3, #0
8003dd0: d017 beq.n 8003e02 <HAL_RCC_OscConfig+0x16e>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\
8003dd2: 4b4d ldr r3, [pc, #308] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003dd4: 689b ldr r3, [r3, #8]
8003dd6: f003 030c and.w r3, r3, #12
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
8003dda: 2b08 cmp r3, #8
8003ddc: d105 bne.n 8003dea <HAL_RCC_OscConfig+0x156>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\
8003dde: 4b4a ldr r3, [pc, #296] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003de0: 685b ldr r3, [r3, #4]
8003de2: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8003de6: 2b00 cmp r3, #0
8003de8: d00b beq.n 8003e02 <HAL_RCC_OscConfig+0x16e>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
8003dea: 4b47 ldr r3, [pc, #284] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003dec: 689b ldr r3, [r3, #8]
8003dee: f003 030c and.w r3, r3, #12
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) ||\
8003df2: 2b0c cmp r3, #12
8003df4: d11c bne.n 8003e30 <HAL_RCC_OscConfig+0x19c>
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
8003df6: 4b44 ldr r3, [pc, #272] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003df8: 685b ldr r3, [r3, #4]
8003dfa: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8003dfe: 2b00 cmp r3, #0
8003e00: d116 bne.n 8003e30 <HAL_RCC_OscConfig+0x19c>
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
#endif /* STM32F446xx */
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8003e02: 4b41 ldr r3, [pc, #260] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003e04: 681b ldr r3, [r3, #0]
8003e06: f003 0302 and.w r3, r3, #2
8003e0a: 2b00 cmp r3, #0
8003e0c: d005 beq.n 8003e1a <HAL_RCC_OscConfig+0x186>
8003e0e: 687b ldr r3, [r7, #4]
8003e10: 68db ldr r3, [r3, #12]
8003e12: 2b01 cmp r3, #1
8003e14: d001 beq.n 8003e1a <HAL_RCC_OscConfig+0x186>
{
return HAL_ERROR;
8003e16: 2301 movs r3, #1
8003e18: e1d3 b.n 80041c2 <HAL_RCC_OscConfig+0x52e>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8003e1a: 4b3b ldr r3, [pc, #236] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003e1c: 681b ldr r3, [r3, #0]
8003e1e: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8003e22: 687b ldr r3, [r7, #4]
8003e24: 691b ldr r3, [r3, #16]
8003e26: 00db lsls r3, r3, #3
8003e28: 4937 ldr r1, [pc, #220] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003e2a: 4313 orrs r3, r2
8003e2c: 600b str r3, [r1, #0]
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
8003e2e: e03a b.n 8003ea6 <HAL_RCC_OscConfig+0x212>
}
}
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
8003e30: 687b ldr r3, [r7, #4]
8003e32: 68db ldr r3, [r3, #12]
8003e34: 2b00 cmp r3, #0
8003e36: d020 beq.n 8003e7a <HAL_RCC_OscConfig+0x1e6>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8003e38: 4b34 ldr r3, [pc, #208] @ (8003f0c <HAL_RCC_OscConfig+0x278>)
8003e3a: 2201 movs r2, #1
8003e3c: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003e3e: f7fd ff05 bl 8001c4c <HAL_GetTick>
8003e42: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8003e44: e008 b.n 8003e58 <HAL_RCC_OscConfig+0x1c4>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8003e46: f7fd ff01 bl 8001c4c <HAL_GetTick>
8003e4a: 4602 mov r2, r0
8003e4c: 693b ldr r3, [r7, #16]
8003e4e: 1ad3 subs r3, r2, r3
8003e50: 2b02 cmp r3, #2
8003e52: d901 bls.n 8003e58 <HAL_RCC_OscConfig+0x1c4>
{
return HAL_TIMEOUT;
8003e54: 2303 movs r3, #3
8003e56: e1b4 b.n 80041c2 <HAL_RCC_OscConfig+0x52e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
8003e58: 4b2b ldr r3, [pc, #172] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003e5a: 681b ldr r3, [r3, #0]
8003e5c: f003 0302 and.w r3, r3, #2
8003e60: 2b00 cmp r3, #0
8003e62: d0f0 beq.n 8003e46 <HAL_RCC_OscConfig+0x1b2>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8003e64: 4b28 ldr r3, [pc, #160] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003e66: 681b ldr r3, [r3, #0]
8003e68: f023 02f8 bic.w r2, r3, #248 @ 0xf8
8003e6c: 687b ldr r3, [r7, #4]
8003e6e: 691b ldr r3, [r3, #16]
8003e70: 00db lsls r3, r3, #3
8003e72: 4925 ldr r1, [pc, #148] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003e74: 4313 orrs r3, r2
8003e76: 600b str r3, [r1, #0]
8003e78: e015 b.n 8003ea6 <HAL_RCC_OscConfig+0x212>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
8003e7a: 4b24 ldr r3, [pc, #144] @ (8003f0c <HAL_RCC_OscConfig+0x278>)
8003e7c: 2200 movs r2, #0
8003e7e: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003e80: f7fd fee4 bl 8001c4c <HAL_GetTick>
8003e84: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8003e86: e008 b.n 8003e9a <HAL_RCC_OscConfig+0x206>
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
8003e88: f7fd fee0 bl 8001c4c <HAL_GetTick>
8003e8c: 4602 mov r2, r0
8003e8e: 693b ldr r3, [r7, #16]
8003e90: 1ad3 subs r3, r2, r3
8003e92: 2b02 cmp r3, #2
8003e94: d901 bls.n 8003e9a <HAL_RCC_OscConfig+0x206>
{
return HAL_TIMEOUT;
8003e96: 2303 movs r3, #3
8003e98: e193 b.n 80041c2 <HAL_RCC_OscConfig+0x52e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
8003e9a: 4b1b ldr r3, [pc, #108] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003e9c: 681b ldr r3, [r3, #0]
8003e9e: f003 0302 and.w r3, r3, #2
8003ea2: 2b00 cmp r3, #0
8003ea4: d1f0 bne.n 8003e88 <HAL_RCC_OscConfig+0x1f4>
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8003ea6: 687b ldr r3, [r7, #4]
8003ea8: 681b ldr r3, [r3, #0]
8003eaa: f003 0308 and.w r3, r3, #8
8003eae: 2b00 cmp r3, #0
8003eb0: d036 beq.n 8003f20 <HAL_RCC_OscConfig+0x28c>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
8003eb2: 687b ldr r3, [r7, #4]
8003eb4: 695b ldr r3, [r3, #20]
8003eb6: 2b00 cmp r3, #0
8003eb8: d016 beq.n 8003ee8 <HAL_RCC_OscConfig+0x254>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
8003eba: 4b15 ldr r3, [pc, #84] @ (8003f10 <HAL_RCC_OscConfig+0x27c>)
8003ebc: 2201 movs r2, #1
8003ebe: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003ec0: f7fd fec4 bl 8001c4c <HAL_GetTick>
8003ec4: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8003ec6: e008 b.n 8003eda <HAL_RCC_OscConfig+0x246>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8003ec8: f7fd fec0 bl 8001c4c <HAL_GetTick>
8003ecc: 4602 mov r2, r0
8003ece: 693b ldr r3, [r7, #16]
8003ed0: 1ad3 subs r3, r2, r3
8003ed2: 2b02 cmp r3, #2
8003ed4: d901 bls.n 8003eda <HAL_RCC_OscConfig+0x246>
{
return HAL_TIMEOUT;
8003ed6: 2303 movs r3, #3
8003ed8: e173 b.n 80041c2 <HAL_RCC_OscConfig+0x52e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
8003eda: 4b0b ldr r3, [pc, #44] @ (8003f08 <HAL_RCC_OscConfig+0x274>)
8003edc: 6f5b ldr r3, [r3, #116] @ 0x74
8003ede: f003 0302 and.w r3, r3, #2
8003ee2: 2b00 cmp r3, #0
8003ee4: d0f0 beq.n 8003ec8 <HAL_RCC_OscConfig+0x234>
8003ee6: e01b b.n 8003f20 <HAL_RCC_OscConfig+0x28c>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8003ee8: 4b09 ldr r3, [pc, #36] @ (8003f10 <HAL_RCC_OscConfig+0x27c>)
8003eea: 2200 movs r2, #0
8003eec: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003eee: f7fd fead bl 8001c4c <HAL_GetTick>
8003ef2: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8003ef4: e00e b.n 8003f14 <HAL_RCC_OscConfig+0x280>
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
8003ef6: f7fd fea9 bl 8001c4c <HAL_GetTick>
8003efa: 4602 mov r2, r0
8003efc: 693b ldr r3, [r7, #16]
8003efe: 1ad3 subs r3, r2, r3
8003f00: 2b02 cmp r3, #2
8003f02: d907 bls.n 8003f14 <HAL_RCC_OscConfig+0x280>
{
return HAL_TIMEOUT;
8003f04: 2303 movs r3, #3
8003f06: e15c b.n 80041c2 <HAL_RCC_OscConfig+0x52e>
8003f08: 40023800 .word 0x40023800
8003f0c: 42470000 .word 0x42470000
8003f10: 42470e80 .word 0x42470e80
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
8003f14: 4b8a ldr r3, [pc, #552] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8003f16: 6f5b ldr r3, [r3, #116] @ 0x74
8003f18: f003 0302 and.w r3, r3, #2
8003f1c: 2b00 cmp r3, #0
8003f1e: d1ea bne.n 8003ef6 <HAL_RCC_OscConfig+0x262>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8003f20: 687b ldr r3, [r7, #4]
8003f22: 681b ldr r3, [r3, #0]
8003f24: f003 0304 and.w r3, r3, #4
8003f28: 2b00 cmp r3, #0
8003f2a: f000 8097 beq.w 800405c <HAL_RCC_OscConfig+0x3c8>
{
FlagStatus pwrclkchanged = RESET;
8003f2e: 2300 movs r3, #0
8003f30: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8003f32: 4b83 ldr r3, [pc, #524] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8003f34: 6c1b ldr r3, [r3, #64] @ 0x40
8003f36: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8003f3a: 2b00 cmp r3, #0
8003f3c: d10f bne.n 8003f5e <HAL_RCC_OscConfig+0x2ca>
{
__HAL_RCC_PWR_CLK_ENABLE();
8003f3e: 2300 movs r3, #0
8003f40: 60bb str r3, [r7, #8]
8003f42: 4b7f ldr r3, [pc, #508] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8003f44: 6c1b ldr r3, [r3, #64] @ 0x40
8003f46: 4a7e ldr r2, [pc, #504] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8003f48: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8003f4c: 6413 str r3, [r2, #64] @ 0x40
8003f4e: 4b7c ldr r3, [pc, #496] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8003f50: 6c1b ldr r3, [r3, #64] @ 0x40
8003f52: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8003f56: 60bb str r3, [r7, #8]
8003f58: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8003f5a: 2301 movs r3, #1
8003f5c: 75fb strb r3, [r7, #23]
}
if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003f5e: 4b79 ldr r3, [pc, #484] @ (8004144 <HAL_RCC_OscConfig+0x4b0>)
8003f60: 681b ldr r3, [r3, #0]
8003f62: f403 7380 and.w r3, r3, #256 @ 0x100
8003f66: 2b00 cmp r3, #0
8003f68: d118 bne.n 8003f9c <HAL_RCC_OscConfig+0x308>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR, PWR_CR_DBP);
8003f6a: 4b76 ldr r3, [pc, #472] @ (8004144 <HAL_RCC_OscConfig+0x4b0>)
8003f6c: 681b ldr r3, [r3, #0]
8003f6e: 4a75 ldr r2, [pc, #468] @ (8004144 <HAL_RCC_OscConfig+0x4b0>)
8003f70: f443 7380 orr.w r3, r3, #256 @ 0x100
8003f74: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8003f76: f7fd fe69 bl 8001c4c <HAL_GetTick>
8003f7a: 6138 str r0, [r7, #16]
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003f7c: e008 b.n 8003f90 <HAL_RCC_OscConfig+0x2fc>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8003f7e: f7fd fe65 bl 8001c4c <HAL_GetTick>
8003f82: 4602 mov r2, r0
8003f84: 693b ldr r3, [r7, #16]
8003f86: 1ad3 subs r3, r2, r3
8003f88: 2b02 cmp r3, #2
8003f8a: d901 bls.n 8003f90 <HAL_RCC_OscConfig+0x2fc>
{
return HAL_TIMEOUT;
8003f8c: 2303 movs r3, #3
8003f8e: e118 b.n 80041c2 <HAL_RCC_OscConfig+0x52e>
while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
8003f90: 4b6c ldr r3, [pc, #432] @ (8004144 <HAL_RCC_OscConfig+0x4b0>)
8003f92: 681b ldr r3, [r3, #0]
8003f94: f403 7380 and.w r3, r3, #256 @ 0x100
8003f98: 2b00 cmp r3, #0
8003f9a: d0f0 beq.n 8003f7e <HAL_RCC_OscConfig+0x2ea>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8003f9c: 687b ldr r3, [r7, #4]
8003f9e: 689b ldr r3, [r3, #8]
8003fa0: 2b01 cmp r3, #1
8003fa2: d106 bne.n 8003fb2 <HAL_RCC_OscConfig+0x31e>
8003fa4: 4b66 ldr r3, [pc, #408] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8003fa6: 6f1b ldr r3, [r3, #112] @ 0x70
8003fa8: 4a65 ldr r2, [pc, #404] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8003faa: f043 0301 orr.w r3, r3, #1
8003fae: 6713 str r3, [r2, #112] @ 0x70
8003fb0: e01c b.n 8003fec <HAL_RCC_OscConfig+0x358>
8003fb2: 687b ldr r3, [r7, #4]
8003fb4: 689b ldr r3, [r3, #8]
8003fb6: 2b05 cmp r3, #5
8003fb8: d10c bne.n 8003fd4 <HAL_RCC_OscConfig+0x340>
8003fba: 4b61 ldr r3, [pc, #388] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8003fbc: 6f1b ldr r3, [r3, #112] @ 0x70
8003fbe: 4a60 ldr r2, [pc, #384] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8003fc0: f043 0304 orr.w r3, r3, #4
8003fc4: 6713 str r3, [r2, #112] @ 0x70
8003fc6: 4b5e ldr r3, [pc, #376] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8003fc8: 6f1b ldr r3, [r3, #112] @ 0x70
8003fca: 4a5d ldr r2, [pc, #372] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8003fcc: f043 0301 orr.w r3, r3, #1
8003fd0: 6713 str r3, [r2, #112] @ 0x70
8003fd2: e00b b.n 8003fec <HAL_RCC_OscConfig+0x358>
8003fd4: 4b5a ldr r3, [pc, #360] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8003fd6: 6f1b ldr r3, [r3, #112] @ 0x70
8003fd8: 4a59 ldr r2, [pc, #356] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8003fda: f023 0301 bic.w r3, r3, #1
8003fde: 6713 str r3, [r2, #112] @ 0x70
8003fe0: 4b57 ldr r3, [pc, #348] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8003fe2: 6f1b ldr r3, [r3, #112] @ 0x70
8003fe4: 4a56 ldr r2, [pc, #344] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8003fe6: f023 0304 bic.w r3, r3, #4
8003fea: 6713 str r3, [r2, #112] @ 0x70
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
8003fec: 687b ldr r3, [r7, #4]
8003fee: 689b ldr r3, [r3, #8]
8003ff0: 2b00 cmp r3, #0
8003ff2: d015 beq.n 8004020 <HAL_RCC_OscConfig+0x38c>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8003ff4: f7fd fe2a bl 8001c4c <HAL_GetTick>
8003ff8: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8003ffa: e00a b.n 8004012 <HAL_RCC_OscConfig+0x37e>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8003ffc: f7fd fe26 bl 8001c4c <HAL_GetTick>
8004000: 4602 mov r2, r0
8004002: 693b ldr r3, [r7, #16]
8004004: 1ad3 subs r3, r2, r3
8004006: f241 3288 movw r2, #5000 @ 0x1388
800400a: 4293 cmp r3, r2
800400c: d901 bls.n 8004012 <HAL_RCC_OscConfig+0x37e>
{
return HAL_TIMEOUT;
800400e: 2303 movs r3, #3
8004010: e0d7 b.n 80041c2 <HAL_RCC_OscConfig+0x52e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
8004012: 4b4b ldr r3, [pc, #300] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8004014: 6f1b ldr r3, [r3, #112] @ 0x70
8004016: f003 0302 and.w r3, r3, #2
800401a: 2b00 cmp r3, #0
800401c: d0ee beq.n 8003ffc <HAL_RCC_OscConfig+0x368>
800401e: e014 b.n 800404a <HAL_RCC_OscConfig+0x3b6>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004020: f7fd fe14 bl 8001c4c <HAL_GetTick>
8004024: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
8004026: e00a b.n 800403e <HAL_RCC_OscConfig+0x3aa>
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
8004028: f7fd fe10 bl 8001c4c <HAL_GetTick>
800402c: 4602 mov r2, r0
800402e: 693b ldr r3, [r7, #16]
8004030: 1ad3 subs r3, r2, r3
8004032: f241 3288 movw r2, #5000 @ 0x1388
8004036: 4293 cmp r3, r2
8004038: d901 bls.n 800403e <HAL_RCC_OscConfig+0x3aa>
{
return HAL_TIMEOUT;
800403a: 2303 movs r3, #3
800403c: e0c1 b.n 80041c2 <HAL_RCC_OscConfig+0x52e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
800403e: 4b40 ldr r3, [pc, #256] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8004040: 6f1b ldr r3, [r3, #112] @ 0x70
8004042: f003 0302 and.w r3, r3, #2
8004046: 2b00 cmp r3, #0
8004048: d1ee bne.n 8004028 <HAL_RCC_OscConfig+0x394>
}
}
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
800404a: 7dfb ldrb r3, [r7, #23]
800404c: 2b01 cmp r3, #1
800404e: d105 bne.n 800405c <HAL_RCC_OscConfig+0x3c8>
{
__HAL_RCC_PWR_CLK_DISABLE();
8004050: 4b3b ldr r3, [pc, #236] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8004052: 6c1b ldr r3, [r3, #64] @ 0x40
8004054: 4a3a ldr r2, [pc, #232] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8004056: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
800405a: 6413 str r3, [r2, #64] @ 0x40
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
800405c: 687b ldr r3, [r7, #4]
800405e: 699b ldr r3, [r3, #24]
8004060: 2b00 cmp r3, #0
8004062: f000 80ad beq.w 80041c0 <HAL_RCC_OscConfig+0x52c>
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
8004066: 4b36 ldr r3, [pc, #216] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8004068: 689b ldr r3, [r3, #8]
800406a: f003 030c and.w r3, r3, #12
800406e: 2b08 cmp r3, #8
8004070: d060 beq.n 8004134 <HAL_RCC_OscConfig+0x4a0>
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
8004072: 687b ldr r3, [r7, #4]
8004074: 699b ldr r3, [r3, #24]
8004076: 2b02 cmp r3, #2
8004078: d145 bne.n 8004106 <HAL_RCC_OscConfig+0x472>
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
800407a: 4b33 ldr r3, [pc, #204] @ (8004148 <HAL_RCC_OscConfig+0x4b4>)
800407c: 2200 movs r2, #0
800407e: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8004080: f7fd fde4 bl 8001c4c <HAL_GetTick>
8004084: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8004086: e008 b.n 800409a <HAL_RCC_OscConfig+0x406>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8004088: f7fd fde0 bl 8001c4c <HAL_GetTick>
800408c: 4602 mov r2, r0
800408e: 693b ldr r3, [r7, #16]
8004090: 1ad3 subs r3, r2, r3
8004092: 2b02 cmp r3, #2
8004094: d901 bls.n 800409a <HAL_RCC_OscConfig+0x406>
{
return HAL_TIMEOUT;
8004096: 2303 movs r3, #3
8004098: e093 b.n 80041c2 <HAL_RCC_OscConfig+0x52e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
800409a: 4b29 ldr r3, [pc, #164] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
800409c: 681b ldr r3, [r3, #0]
800409e: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80040a2: 2b00 cmp r3, #0
80040a4: d1f0 bne.n 8004088 <HAL_RCC_OscConfig+0x3f4>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
80040a6: 687b ldr r3, [r7, #4]
80040a8: 69da ldr r2, [r3, #28]
80040aa: 687b ldr r3, [r7, #4]
80040ac: 6a1b ldr r3, [r3, #32]
80040ae: 431a orrs r2, r3
80040b0: 687b ldr r3, [r7, #4]
80040b2: 6a5b ldr r3, [r3, #36] @ 0x24
80040b4: 019b lsls r3, r3, #6
80040b6: 431a orrs r2, r3
80040b8: 687b ldr r3, [r7, #4]
80040ba: 6a9b ldr r3, [r3, #40] @ 0x28
80040bc: 085b lsrs r3, r3, #1
80040be: 3b01 subs r3, #1
80040c0: 041b lsls r3, r3, #16
80040c2: 431a orrs r2, r3
80040c4: 687b ldr r3, [r7, #4]
80040c6: 6adb ldr r3, [r3, #44] @ 0x2c
80040c8: 061b lsls r3, r3, #24
80040ca: 431a orrs r2, r3
80040cc: 687b ldr r3, [r7, #4]
80040ce: 6b1b ldr r3, [r3, #48] @ 0x30
80040d0: 071b lsls r3, r3, #28
80040d2: 491b ldr r1, [pc, #108] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
80040d4: 4313 orrs r3, r2
80040d6: 604b str r3, [r1, #4]
(RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
(((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
(RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos) | \
(RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80040d8: 4b1b ldr r3, [pc, #108] @ (8004148 <HAL_RCC_OscConfig+0x4b4>)
80040da: 2201 movs r2, #1
80040dc: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80040de: f7fd fdb5 bl 8001c4c <HAL_GetTick>
80040e2: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80040e4: e008 b.n 80040f8 <HAL_RCC_OscConfig+0x464>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
80040e6: f7fd fdb1 bl 8001c4c <HAL_GetTick>
80040ea: 4602 mov r2, r0
80040ec: 693b ldr r3, [r7, #16]
80040ee: 1ad3 subs r3, r2, r3
80040f0: 2b02 cmp r3, #2
80040f2: d901 bls.n 80040f8 <HAL_RCC_OscConfig+0x464>
{
return HAL_TIMEOUT;
80040f4: 2303 movs r3, #3
80040f6: e064 b.n 80041c2 <HAL_RCC_OscConfig+0x52e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
80040f8: 4b11 ldr r3, [pc, #68] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
80040fa: 681b ldr r3, [r3, #0]
80040fc: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8004100: 2b00 cmp r3, #0
8004102: d0f0 beq.n 80040e6 <HAL_RCC_OscConfig+0x452>
8004104: e05c b.n 80041c0 <HAL_RCC_OscConfig+0x52c>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8004106: 4b10 ldr r3, [pc, #64] @ (8004148 <HAL_RCC_OscConfig+0x4b4>)
8004108: 2200 movs r2, #0
800410a: 601a str r2, [r3, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800410c: f7fd fd9e bl 8001c4c <HAL_GetTick>
8004110: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8004112: e008 b.n 8004126 <HAL_RCC_OscConfig+0x492>
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
8004114: f7fd fd9a bl 8001c4c <HAL_GetTick>
8004118: 4602 mov r2, r0
800411a: 693b ldr r3, [r7, #16]
800411c: 1ad3 subs r3, r2, r3
800411e: 2b02 cmp r3, #2
8004120: d901 bls.n 8004126 <HAL_RCC_OscConfig+0x492>
{
return HAL_TIMEOUT;
8004122: 2303 movs r3, #3
8004124: e04d b.n 80041c2 <HAL_RCC_OscConfig+0x52e>
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
8004126: 4b06 ldr r3, [pc, #24] @ (8004140 <HAL_RCC_OscConfig+0x4ac>)
8004128: 681b ldr r3, [r3, #0]
800412a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
800412e: 2b00 cmp r3, #0
8004130: d1f0 bne.n 8004114 <HAL_RCC_OscConfig+0x480>
8004132: e045 b.n 80041c0 <HAL_RCC_OscConfig+0x52c>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8004134: 687b ldr r3, [r7, #4]
8004136: 699b ldr r3, [r3, #24]
8004138: 2b01 cmp r3, #1
800413a: d107 bne.n 800414c <HAL_RCC_OscConfig+0x4b8>
{
return HAL_ERROR;
800413c: 2301 movs r3, #1
800413e: e040 b.n 80041c2 <HAL_RCC_OscConfig+0x52e>
8004140: 40023800 .word 0x40023800
8004144: 40007000 .word 0x40007000
8004148: 42470060 .word 0x42470060
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
pll_config = RCC->PLLCFGR;
800414c: 4b1f ldr r3, [pc, #124] @ (80041cc <HAL_RCC_OscConfig+0x538>)
800414e: 685b ldr r3, [r3, #4]
8004150: 60fb str r3, [r7, #12]
#if defined (RCC_PLLCFGR_PLLR)
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8004152: 687b ldr r3, [r7, #4]
8004154: 699b ldr r3, [r3, #24]
8004156: 2b01 cmp r3, #1
8004158: d030 beq.n 80041bc <HAL_RCC_OscConfig+0x528>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
800415a: 68fb ldr r3, [r7, #12]
800415c: f403 0280 and.w r2, r3, #4194304 @ 0x400000
8004160: 687b ldr r3, [r7, #4]
8004162: 69db ldr r3, [r3, #28]
if (((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) ||
8004164: 429a cmp r2, r3
8004166: d129 bne.n 80041bc <HAL_RCC_OscConfig+0x528>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
8004168: 68fb ldr r3, [r7, #12]
800416a: f003 023f and.w r2, r3, #63 @ 0x3f
800416e: 687b ldr r3, [r7, #4]
8004170: 6a1b ldr r3, [r3, #32]
(READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8004172: 429a cmp r2, r3
8004174: d122 bne.n 80041bc <HAL_RCC_OscConfig+0x528>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
8004176: 68fa ldr r2, [r7, #12]
8004178: f647 73c0 movw r3, #32704 @ 0x7fc0
800417c: 4013 ands r3, r2
800417e: 687a ldr r2, [r7, #4]
8004180: 6a52 ldr r2, [r2, #36] @ 0x24
8004182: 0192 lsls r2, r2, #6
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != (RCC_OscInitStruct->PLL.PLLM) << RCC_PLLCFGR_PLLM_Pos) ||
8004184: 4293 cmp r3, r2
8004186: d119 bne.n 80041bc <HAL_RCC_OscConfig+0x528>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
8004188: 68fb ldr r3, [r7, #12]
800418a: f403 3240 and.w r2, r3, #196608 @ 0x30000
800418e: 687b ldr r3, [r7, #4]
8004190: 6a9b ldr r3, [r3, #40] @ 0x28
8004192: 085b lsrs r3, r3, #1
8004194: 3b01 subs r3, #1
8004196: 041b lsls r3, r3, #16
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
8004198: 429a cmp r2, r3
800419a: d10f bne.n 80041bc <HAL_RCC_OscConfig+0x528>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
800419c: 68fb ldr r3, [r7, #12]
800419e: f003 6270 and.w r2, r3, #251658240 @ 0xf000000
80041a2: 687b ldr r3, [r7, #4]
80041a4: 6adb ldr r3, [r3, #44] @ 0x2c
80041a6: 061b lsls r3, r3, #24
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
80041a8: 429a cmp r2, r3
80041aa: d107 bne.n 80041bc <HAL_RCC_OscConfig+0x528>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != (RCC_OscInitStruct->PLL.PLLR << RCC_PLLCFGR_PLLR_Pos)))
80041ac: 68fb ldr r3, [r7, #12]
80041ae: f003 42e0 and.w r2, r3, #1879048192 @ 0x70000000
80041b2: 687b ldr r3, [r7, #4]
80041b4: 6b1b ldr r3, [r3, #48] @ 0x30
80041b6: 071b lsls r3, r3, #28
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)) ||
80041b8: 429a cmp r2, r3
80041ba: d001 beq.n 80041c0 <HAL_RCC_OscConfig+0x52c>
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U)) << RCC_PLLCFGR_PLLP_Pos) ||
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)))
#endif
{
return HAL_ERROR;
80041bc: 2301 movs r3, #1
80041be: e000 b.n 80041c2 <HAL_RCC_OscConfig+0x52e>
}
}
}
}
return HAL_OK;
80041c0: 2300 movs r3, #0
}
80041c2: 4618 mov r0, r3
80041c4: 3718 adds r7, #24
80041c6: 46bd mov sp, r7
80041c8: bd80 pop {r7, pc}
80041ca: bf00 nop
80041cc: 40023800 .word 0x40023800
080041d0 <HAL_SPI_Init>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
{
80041d0: b580 push {r7, lr}
80041d2: b082 sub sp, #8
80041d4: af00 add r7, sp, #0
80041d6: 6078 str r0, [r7, #4]
/* Check the SPI handle allocation */
if (hspi == NULL)
80041d8: 687b ldr r3, [r7, #4]
80041da: 2b00 cmp r3, #0
80041dc: d101 bne.n 80041e2 <HAL_SPI_Init+0x12>
{
return HAL_ERROR;
80041de: 2301 movs r3, #1
80041e0: e07b b.n 80042da <HAL_SPI_Init+0x10a>
assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
assert_param(IS_SPI_NSS(hspi->Init.NSS));
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
80041e2: 687b ldr r3, [r7, #4]
80041e4: 6a5b ldr r3, [r3, #36] @ 0x24
80041e6: 2b00 cmp r3, #0
80041e8: d108 bne.n 80041fc <HAL_SPI_Init+0x2c>
{
assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
if (hspi->Init.Mode == SPI_MODE_MASTER)
80041ea: 687b ldr r3, [r7, #4]
80041ec: 685b ldr r3, [r3, #4]
80041ee: f5b3 7f82 cmp.w r3, #260 @ 0x104
80041f2: d009 beq.n 8004208 <HAL_SPI_Init+0x38>
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
}
else
{
/* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
80041f4: 687b ldr r3, [r7, #4]
80041f6: 2200 movs r2, #0
80041f8: 61da str r2, [r3, #28]
80041fa: e005 b.n 8004208 <HAL_SPI_Init+0x38>
else
{
assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
/* Force polarity and phase to TI protocaol requirements */
hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
80041fc: 687b ldr r3, [r7, #4]
80041fe: 2200 movs r2, #0
8004200: 611a str r2, [r3, #16]
hspi->Init.CLKPhase = SPI_PHASE_1EDGE;
8004202: 687b ldr r3, [r7, #4]
8004204: 2200 movs r2, #0
8004206: 615a str r2, [r3, #20]
if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
{
assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
}
#else
hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
8004208: 687b ldr r3, [r7, #4]
800420a: 2200 movs r2, #0
800420c: 629a str r2, [r3, #40] @ 0x28
#endif /* USE_SPI_CRC */
if (hspi->State == HAL_SPI_STATE_RESET)
800420e: 687b ldr r3, [r7, #4]
8004210: f893 3051 ldrb.w r3, [r3, #81] @ 0x51
8004214: b2db uxtb r3, r3
8004216: 2b00 cmp r3, #0
8004218: d106 bne.n 8004228 <HAL_SPI_Init+0x58>
{
/* Allocate lock resource and initialize it */
hspi->Lock = HAL_UNLOCKED;
800421a: 687b ldr r3, [r7, #4]
800421c: 2200 movs r2, #0
800421e: f883 2050 strb.w r2, [r3, #80] @ 0x50
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
hspi->MspInitCallback(hspi);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit(hspi);
8004222: 6878 ldr r0, [r7, #4]
8004224: f7fd f8e2 bl 80013ec <HAL_SPI_MspInit>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
hspi->State = HAL_SPI_STATE_BUSY;
8004228: 687b ldr r3, [r7, #4]
800422a: 2202 movs r2, #2
800422c: f883 2051 strb.w r2, [r3, #81] @ 0x51
/* Disable the selected SPI peripheral */
__HAL_SPI_DISABLE(hspi);
8004230: 687b ldr r3, [r7, #4]
8004232: 681b ldr r3, [r3, #0]
8004234: 681a ldr r2, [r3, #0]
8004236: 687b ldr r3, [r7, #4]
8004238: 681b ldr r3, [r3, #0]
800423a: f022 0240 bic.w r2, r2, #64 @ 0x40
800423e: 601a str r2, [r3, #0]
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
8004240: 687b ldr r3, [r7, #4]
8004242: 685b ldr r3, [r3, #4]
8004244: f403 7282 and.w r2, r3, #260 @ 0x104
8004248: 687b ldr r3, [r7, #4]
800424a: 689b ldr r3, [r3, #8]
800424c: f403 4304 and.w r3, r3, #33792 @ 0x8400
8004250: 431a orrs r2, r3
8004252: 687b ldr r3, [r7, #4]
8004254: 68db ldr r3, [r3, #12]
8004256: f403 6300 and.w r3, r3, #2048 @ 0x800
800425a: 431a orrs r2, r3
800425c: 687b ldr r3, [r7, #4]
800425e: 691b ldr r3, [r3, #16]
8004260: f003 0302 and.w r3, r3, #2
8004264: 431a orrs r2, r3
8004266: 687b ldr r3, [r7, #4]
8004268: 695b ldr r3, [r3, #20]
800426a: f003 0301 and.w r3, r3, #1
800426e: 431a orrs r2, r3
8004270: 687b ldr r3, [r7, #4]
8004272: 699b ldr r3, [r3, #24]
8004274: f403 7300 and.w r3, r3, #512 @ 0x200
8004278: 431a orrs r2, r3
800427a: 687b ldr r3, [r7, #4]
800427c: 69db ldr r3, [r3, #28]
800427e: f003 0338 and.w r3, r3, #56 @ 0x38
8004282: 431a orrs r2, r3
8004284: 687b ldr r3, [r7, #4]
8004286: 6a1b ldr r3, [r3, #32]
8004288: f003 0380 and.w r3, r3, #128 @ 0x80
800428c: ea42 0103 orr.w r1, r2, r3
8004290: 687b ldr r3, [r7, #4]
8004292: 6a9b ldr r3, [r3, #40] @ 0x28
8004294: f403 5200 and.w r2, r3, #8192 @ 0x2000
8004298: 687b ldr r3, [r7, #4]
800429a: 681b ldr r3, [r3, #0]
800429c: 430a orrs r2, r1
800429e: 601a str r2, [r3, #0]
(hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
(hspi->Init.FirstBit & SPI_CR1_LSBFIRST) |
(hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
/* Configure : NSS management, TI Mode */
WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF)));
80042a0: 687b ldr r3, [r7, #4]
80042a2: 699b ldr r3, [r3, #24]
80042a4: 0c1b lsrs r3, r3, #16
80042a6: f003 0104 and.w r1, r3, #4
80042aa: 687b ldr r3, [r7, #4]
80042ac: 6a5b ldr r3, [r3, #36] @ 0x24
80042ae: f003 0210 and.w r2, r3, #16
80042b2: 687b ldr r3, [r7, #4]
80042b4: 681b ldr r3, [r3, #0]
80042b6: 430a orrs r2, r1
80042b8: 605a str r2, [r3, #4]
}
#endif /* USE_SPI_CRC */
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
80042ba: 687b ldr r3, [r7, #4]
80042bc: 681b ldr r3, [r3, #0]
80042be: 69da ldr r2, [r3, #28]
80042c0: 687b ldr r3, [r7, #4]
80042c2: 681b ldr r3, [r3, #0]
80042c4: f422 6200 bic.w r2, r2, #2048 @ 0x800
80042c8: 61da str r2, [r3, #28]
#endif /* SPI_I2SCFGR_I2SMOD */
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
80042ca: 687b ldr r3, [r7, #4]
80042cc: 2200 movs r2, #0
80042ce: 655a str r2, [r3, #84] @ 0x54
hspi->State = HAL_SPI_STATE_READY;
80042d0: 687b ldr r3, [r7, #4]
80042d2: 2201 movs r2, #1
80042d4: f883 2051 strb.w r2, [r3, #81] @ 0x51
return HAL_OK;
80042d8: 2300 movs r3, #0
}
80042da: 4618 mov r0, r3
80042dc: 3708 adds r7, #8
80042de: 46bd mov sp, r7
80042e0: bd80 pop {r7, pc}
...
080042e4 <HAL_SPI_IRQHandler>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval None
*/
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
{
80042e4: b580 push {r7, lr}
80042e6: b088 sub sp, #32
80042e8: af00 add r7, sp, #0
80042ea: 6078 str r0, [r7, #4]
uint32_t itsource = hspi->Instance->CR2;
80042ec: 687b ldr r3, [r7, #4]
80042ee: 681b ldr r3, [r3, #0]
80042f0: 685b ldr r3, [r3, #4]
80042f2: 61fb str r3, [r7, #28]
uint32_t itflag = hspi->Instance->SR;
80042f4: 687b ldr r3, [r7, #4]
80042f6: 681b ldr r3, [r3, #0]
80042f8: 689b ldr r3, [r3, #8]
80042fa: 61bb str r3, [r7, #24]
/* SPI in mode Receiver ----------------------------------------------------*/
if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
80042fc: 69bb ldr r3, [r7, #24]
80042fe: f003 0340 and.w r3, r3, #64 @ 0x40
8004302: 2b00 cmp r3, #0
8004304: d10e bne.n 8004324 <HAL_SPI_IRQHandler+0x40>
(SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
8004306: 69bb ldr r3, [r7, #24]
8004308: f003 0301 and.w r3, r3, #1
if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
800430c: 2b00 cmp r3, #0
800430e: d009 beq.n 8004324 <HAL_SPI_IRQHandler+0x40>
(SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
8004310: 69fb ldr r3, [r7, #28]
8004312: f003 0340 and.w r3, r3, #64 @ 0x40
8004316: 2b00 cmp r3, #0
8004318: d004 beq.n 8004324 <HAL_SPI_IRQHandler+0x40>
{
hspi->RxISR(hspi);
800431a: 687b ldr r3, [r7, #4]
800431c: 6c1b ldr r3, [r3, #64] @ 0x40
800431e: 6878 ldr r0, [r7, #4]
8004320: 4798 blx r3
return;
8004322: e0ce b.n 80044c2 <HAL_SPI_IRQHandler+0x1de>
}
/* SPI in mode Transmitter -------------------------------------------------*/
if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
8004324: 69bb ldr r3, [r7, #24]
8004326: f003 0302 and.w r3, r3, #2
800432a: 2b00 cmp r3, #0
800432c: d009 beq.n 8004342 <HAL_SPI_IRQHandler+0x5e>
800432e: 69fb ldr r3, [r7, #28]
8004330: f003 0380 and.w r3, r3, #128 @ 0x80
8004334: 2b00 cmp r3, #0
8004336: d004 beq.n 8004342 <HAL_SPI_IRQHandler+0x5e>
{
hspi->TxISR(hspi);
8004338: 687b ldr r3, [r7, #4]
800433a: 6c5b ldr r3, [r3, #68] @ 0x44
800433c: 6878 ldr r0, [r7, #4]
800433e: 4798 blx r3
return;
8004340: e0bf b.n 80044c2 <HAL_SPI_IRQHandler+0x1de>
}
/* SPI in Error Treatment --------------------------------------------------*/
if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
8004342: 69bb ldr r3, [r7, #24]
8004344: f003 0320 and.w r3, r3, #32
8004348: 2b00 cmp r3, #0
800434a: d10a bne.n 8004362 <HAL_SPI_IRQHandler+0x7e>
800434c: 69bb ldr r3, [r7, #24]
800434e: f003 0340 and.w r3, r3, #64 @ 0x40
8004352: 2b00 cmp r3, #0
8004354: d105 bne.n 8004362 <HAL_SPI_IRQHandler+0x7e>
|| (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
8004356: 69bb ldr r3, [r7, #24]
8004358: f403 7380 and.w r3, r3, #256 @ 0x100
800435c: 2b00 cmp r3, #0
800435e: f000 80b0 beq.w 80044c2 <HAL_SPI_IRQHandler+0x1de>
8004362: 69fb ldr r3, [r7, #28]
8004364: f003 0320 and.w r3, r3, #32
8004368: 2b00 cmp r3, #0
800436a: f000 80aa beq.w 80044c2 <HAL_SPI_IRQHandler+0x1de>
{
/* SPI Overrun error interrupt occurred ----------------------------------*/
if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
800436e: 69bb ldr r3, [r7, #24]
8004370: f003 0340 and.w r3, r3, #64 @ 0x40
8004374: 2b00 cmp r3, #0
8004376: d023 beq.n 80043c0 <HAL_SPI_IRQHandler+0xdc>
{
if (hspi->State != HAL_SPI_STATE_BUSY_TX)
8004378: 687b ldr r3, [r7, #4]
800437a: f893 3051 ldrb.w r3, [r3, #81] @ 0x51
800437e: b2db uxtb r3, r3
8004380: 2b03 cmp r3, #3
8004382: d011 beq.n 80043a8 <HAL_SPI_IRQHandler+0xc4>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
8004384: 687b ldr r3, [r7, #4]
8004386: 6d5b ldr r3, [r3, #84] @ 0x54
8004388: f043 0204 orr.w r2, r3, #4
800438c: 687b ldr r3, [r7, #4]
800438e: 655a str r2, [r3, #84] @ 0x54
__HAL_SPI_CLEAR_OVRFLAG(hspi);
8004390: 2300 movs r3, #0
8004392: 617b str r3, [r7, #20]
8004394: 687b ldr r3, [r7, #4]
8004396: 681b ldr r3, [r3, #0]
8004398: 68db ldr r3, [r3, #12]
800439a: 617b str r3, [r7, #20]
800439c: 687b ldr r3, [r7, #4]
800439e: 681b ldr r3, [r3, #0]
80043a0: 689b ldr r3, [r3, #8]
80043a2: 617b str r3, [r7, #20]
80043a4: 697b ldr r3, [r7, #20]
80043a6: e00b b.n 80043c0 <HAL_SPI_IRQHandler+0xdc>
}
else
{
__HAL_SPI_CLEAR_OVRFLAG(hspi);
80043a8: 2300 movs r3, #0
80043aa: 613b str r3, [r7, #16]
80043ac: 687b ldr r3, [r7, #4]
80043ae: 681b ldr r3, [r3, #0]
80043b0: 68db ldr r3, [r3, #12]
80043b2: 613b str r3, [r7, #16]
80043b4: 687b ldr r3, [r7, #4]
80043b6: 681b ldr r3, [r3, #0]
80043b8: 689b ldr r3, [r3, #8]
80043ba: 613b str r3, [r7, #16]
80043bc: 693b ldr r3, [r7, #16]
return;
80043be: e080 b.n 80044c2 <HAL_SPI_IRQHandler+0x1de>
}
}
/* SPI Mode Fault error interrupt occurred -------------------------------*/
if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
80043c0: 69bb ldr r3, [r7, #24]
80043c2: f003 0320 and.w r3, r3, #32
80043c6: 2b00 cmp r3, #0
80043c8: d014 beq.n 80043f4 <HAL_SPI_IRQHandler+0x110>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
80043ca: 687b ldr r3, [r7, #4]
80043cc: 6d5b ldr r3, [r3, #84] @ 0x54
80043ce: f043 0201 orr.w r2, r3, #1
80043d2: 687b ldr r3, [r7, #4]
80043d4: 655a str r2, [r3, #84] @ 0x54
__HAL_SPI_CLEAR_MODFFLAG(hspi);
80043d6: 2300 movs r3, #0
80043d8: 60fb str r3, [r7, #12]
80043da: 687b ldr r3, [r7, #4]
80043dc: 681b ldr r3, [r3, #0]
80043de: 689b ldr r3, [r3, #8]
80043e0: 60fb str r3, [r7, #12]
80043e2: 687b ldr r3, [r7, #4]
80043e4: 681b ldr r3, [r3, #0]
80043e6: 681a ldr r2, [r3, #0]
80043e8: 687b ldr r3, [r7, #4]
80043ea: 681b ldr r3, [r3, #0]
80043ec: f022 0240 bic.w r2, r2, #64 @ 0x40
80043f0: 601a str r2, [r3, #0]
80043f2: 68fb ldr r3, [r7, #12]
}
/* SPI Frame error interrupt occurred ------------------------------------*/
if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
80043f4: 69bb ldr r3, [r7, #24]
80043f6: f403 7380 and.w r3, r3, #256 @ 0x100
80043fa: 2b00 cmp r3, #0
80043fc: d00c beq.n 8004418 <HAL_SPI_IRQHandler+0x134>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
80043fe: 687b ldr r3, [r7, #4]
8004400: 6d5b ldr r3, [r3, #84] @ 0x54
8004402: f043 0208 orr.w r2, r3, #8
8004406: 687b ldr r3, [r7, #4]
8004408: 655a str r2, [r3, #84] @ 0x54
__HAL_SPI_CLEAR_FREFLAG(hspi);
800440a: 2300 movs r3, #0
800440c: 60bb str r3, [r7, #8]
800440e: 687b ldr r3, [r7, #4]
8004410: 681b ldr r3, [r3, #0]
8004412: 689b ldr r3, [r3, #8]
8004414: 60bb str r3, [r7, #8]
8004416: 68bb ldr r3, [r7, #8]
}
if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
8004418: 687b ldr r3, [r7, #4]
800441a: 6d5b ldr r3, [r3, #84] @ 0x54
800441c: 2b00 cmp r3, #0
800441e: d04f beq.n 80044c0 <HAL_SPI_IRQHandler+0x1dc>
{
/* Disable all interrupts */
__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
8004420: 687b ldr r3, [r7, #4]
8004422: 681b ldr r3, [r3, #0]
8004424: 685a ldr r2, [r3, #4]
8004426: 687b ldr r3, [r7, #4]
8004428: 681b ldr r3, [r3, #0]
800442a: f022 02e0 bic.w r2, r2, #224 @ 0xe0
800442e: 605a str r2, [r3, #4]
hspi->State = HAL_SPI_STATE_READY;
8004430: 687b ldr r3, [r7, #4]
8004432: 2201 movs r2, #1
8004434: f883 2051 strb.w r2, [r3, #81] @ 0x51
/* Disable the SPI DMA requests if enabled */
if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
8004438: 69fb ldr r3, [r7, #28]
800443a: f003 0302 and.w r3, r3, #2
800443e: 2b00 cmp r3, #0
8004440: d104 bne.n 800444c <HAL_SPI_IRQHandler+0x168>
8004442: 69fb ldr r3, [r7, #28]
8004444: f003 0301 and.w r3, r3, #1
8004448: 2b00 cmp r3, #0
800444a: d034 beq.n 80044b6 <HAL_SPI_IRQHandler+0x1d2>
{
CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
800444c: 687b ldr r3, [r7, #4]
800444e: 681b ldr r3, [r3, #0]
8004450: 685a ldr r2, [r3, #4]
8004452: 687b ldr r3, [r7, #4]
8004454: 681b ldr r3, [r3, #0]
8004456: f022 0203 bic.w r2, r2, #3
800445a: 605a str r2, [r3, #4]
/* Abort the SPI DMA Rx channel */
if (hspi->hdmarx != NULL)
800445c: 687b ldr r3, [r7, #4]
800445e: 6cdb ldr r3, [r3, #76] @ 0x4c
8004460: 2b00 cmp r3, #0
8004462: d011 beq.n 8004488 <HAL_SPI_IRQHandler+0x1a4>
{
/* Set the SPI DMA Abort callback :
will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
8004464: 687b ldr r3, [r7, #4]
8004466: 6cdb ldr r3, [r3, #76] @ 0x4c
8004468: 4a17 ldr r2, [pc, #92] @ (80044c8 <HAL_SPI_IRQHandler+0x1e4>)
800446a: 651a str r2, [r3, #80] @ 0x50
if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
800446c: 687b ldr r3, [r7, #4]
800446e: 6cdb ldr r3, [r3, #76] @ 0x4c
8004470: 4618 mov r0, r3
8004472: f7fe fbbd bl 8002bf0 <HAL_DMA_Abort_IT>
8004476: 4603 mov r3, r0
8004478: 2b00 cmp r3, #0
800447a: d005 beq.n 8004488 <HAL_SPI_IRQHandler+0x1a4>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
800447c: 687b ldr r3, [r7, #4]
800447e: 6d5b ldr r3, [r3, #84] @ 0x54
8004480: f043 0240 orr.w r2, r3, #64 @ 0x40
8004484: 687b ldr r3, [r7, #4]
8004486: 655a str r2, [r3, #84] @ 0x54
}
}
/* Abort the SPI DMA Tx channel */
if (hspi->hdmatx != NULL)
8004488: 687b ldr r3, [r7, #4]
800448a: 6c9b ldr r3, [r3, #72] @ 0x48
800448c: 2b00 cmp r3, #0
800448e: d016 beq.n 80044be <HAL_SPI_IRQHandler+0x1da>
{
/* Set the SPI DMA Abort callback :
will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
8004490: 687b ldr r3, [r7, #4]
8004492: 6c9b ldr r3, [r3, #72] @ 0x48
8004494: 4a0c ldr r2, [pc, #48] @ (80044c8 <HAL_SPI_IRQHandler+0x1e4>)
8004496: 651a str r2, [r3, #80] @ 0x50
if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
8004498: 687b ldr r3, [r7, #4]
800449a: 6c9b ldr r3, [r3, #72] @ 0x48
800449c: 4618 mov r0, r3
800449e: f7fe fba7 bl 8002bf0 <HAL_DMA_Abort_IT>
80044a2: 4603 mov r3, r0
80044a4: 2b00 cmp r3, #0
80044a6: d00a beq.n 80044be <HAL_SPI_IRQHandler+0x1da>
{
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
80044a8: 687b ldr r3, [r7, #4]
80044aa: 6d5b ldr r3, [r3, #84] @ 0x54
80044ac: f043 0240 orr.w r2, r3, #64 @ 0x40
80044b0: 687b ldr r3, [r7, #4]
80044b2: 655a str r2, [r3, #84] @ 0x54
if (hspi->hdmatx != NULL)
80044b4: e003 b.n 80044be <HAL_SPI_IRQHandler+0x1da>
{
/* Call user error callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->ErrorCallback(hspi);
#else
HAL_SPI_ErrorCallback(hspi);
80044b6: 6878 ldr r0, [r7, #4]
80044b8: f000 f808 bl 80044cc <HAL_SPI_ErrorCallback>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
}
return;
80044bc: e000 b.n 80044c0 <HAL_SPI_IRQHandler+0x1dc>
if (hspi->hdmatx != NULL)
80044be: bf00 nop
return;
80044c0: bf00 nop
}
}
80044c2: 3720 adds r7, #32
80044c4: 46bd mov sp, r7
80044c6: bd80 pop {r7, pc}
80044c8: 080044e1 .word 0x080044e1
080044cc <HAL_SPI_ErrorCallback>:
* @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
{
80044cc: b480 push {r7}
80044ce: b083 sub sp, #12
80044d0: af00 add r7, sp, #0
80044d2: 6078 str r0, [r7, #4]
the HAL_SPI_ErrorCallback should be implemented in the user file
*/
/* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
and user can use HAL_SPI_GetError() API to check the latest error occurred
*/
}
80044d4: bf00 nop
80044d6: 370c adds r7, #12
80044d8: 46bd mov sp, r7
80044da: f85d 7b04 ldr.w r7, [sp], #4
80044de: 4770 bx lr
080044e0 <SPI_DMAAbortOnError>:
* (To be called at end of DMA Abort procedure following error occurrence).
* @param hdma DMA handle.
* @retval None
*/
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
80044e0: b580 push {r7, lr}
80044e2: b084 sub sp, #16
80044e4: af00 add r7, sp, #0
80044e6: 6078 str r0, [r7, #4]
SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
80044e8: 687b ldr r3, [r7, #4]
80044ea: 6b9b ldr r3, [r3, #56] @ 0x38
80044ec: 60fb str r3, [r7, #12]
hspi->RxXferCount = 0U;
80044ee: 68fb ldr r3, [r7, #12]
80044f0: 2200 movs r2, #0
80044f2: 87da strh r2, [r3, #62] @ 0x3e
hspi->TxXferCount = 0U;
80044f4: 68fb ldr r3, [r7, #12]
80044f6: 2200 movs r2, #0
80044f8: 86da strh r2, [r3, #54] @ 0x36
/* Call user error callback */
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
hspi->ErrorCallback(hspi);
#else
HAL_SPI_ErrorCallback(hspi);
80044fa: 68f8 ldr r0, [r7, #12]
80044fc: f7ff ffe6 bl 80044cc <HAL_SPI_ErrorCallback>
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
}
8004500: bf00 nop
8004502: 3710 adds r7, #16
8004504: 46bd mov sp, r7
8004506: bd80 pop {r7, pc}
08004508 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
8004508: b580 push {r7, lr}
800450a: b082 sub sp, #8
800450c: af00 add r7, sp, #0
800450e: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8004510: 687b ldr r3, [r7, #4]
8004512: 2b00 cmp r3, #0
8004514: d101 bne.n 800451a <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
8004516: 2301 movs r3, #1
8004518: e041 b.n 800459e <HAL_TIM_Base_Init+0x96>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
800451a: 687b ldr r3, [r7, #4]
800451c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
8004520: b2db uxtb r3, r3
8004522: 2b00 cmp r3, #0
8004524: d106 bne.n 8004534 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8004526: 687b ldr r3, [r7, #4]
8004528: 2200 movs r2, #0
800452a: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
800452e: 6878 ldr r0, [r7, #4]
8004530: f7fd fa2c bl 800198c <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8004534: 687b ldr r3, [r7, #4]
8004536: 2202 movs r2, #2
8004538: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
800453c: 687b ldr r3, [r7, #4]
800453e: 681a ldr r2, [r3, #0]
8004540: 687b ldr r3, [r7, #4]
8004542: 3304 adds r3, #4
8004544: 4619 mov r1, r3
8004546: 4610 mov r0, r2
8004548: f000 fb9a bl 8004c80 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
800454c: 687b ldr r3, [r7, #4]
800454e: 2201 movs r2, #1
8004550: f883 2046 strb.w r2, [r3, #70] @ 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8004554: 687b ldr r3, [r7, #4]
8004556: 2201 movs r2, #1
8004558: f883 203e strb.w r2, [r3, #62] @ 0x3e
800455c: 687b ldr r3, [r7, #4]
800455e: 2201 movs r2, #1
8004560: f883 203f strb.w r2, [r3, #63] @ 0x3f
8004564: 687b ldr r3, [r7, #4]
8004566: 2201 movs r2, #1
8004568: f883 2040 strb.w r2, [r3, #64] @ 0x40
800456c: 687b ldr r3, [r7, #4]
800456e: 2201 movs r2, #1
8004570: f883 2041 strb.w r2, [r3, #65] @ 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8004574: 687b ldr r3, [r7, #4]
8004576: 2201 movs r2, #1
8004578: f883 2042 strb.w r2, [r3, #66] @ 0x42
800457c: 687b ldr r3, [r7, #4]
800457e: 2201 movs r2, #1
8004580: f883 2043 strb.w r2, [r3, #67] @ 0x43
8004584: 687b ldr r3, [r7, #4]
8004586: 2201 movs r2, #1
8004588: f883 2044 strb.w r2, [r3, #68] @ 0x44
800458c: 687b ldr r3, [r7, #4]
800458e: 2201 movs r2, #1
8004590: f883 2045 strb.w r2, [r3, #69] @ 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8004594: 687b ldr r3, [r7, #4]
8004596: 2201 movs r2, #1
8004598: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
800459c: 2300 movs r3, #0
}
800459e: 4618 mov r0, r3
80045a0: 3708 adds r7, #8
80045a2: 46bd mov sp, r7
80045a4: bd80 pop {r7, pc}
...
080045a8 <HAL_TIM_Base_Start_IT>:
* @brief Starts the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
{
80045a8: b480 push {r7}
80045aa: b085 sub sp, #20
80045ac: af00 add r7, sp, #0
80045ae: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Check the TIM state */
if (htim->State != HAL_TIM_STATE_READY)
80045b0: 687b ldr r3, [r7, #4]
80045b2: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
80045b6: b2db uxtb r3, r3
80045b8: 2b01 cmp r3, #1
80045ba: d001 beq.n 80045c0 <HAL_TIM_Base_Start_IT+0x18>
{
return HAL_ERROR;
80045bc: 2301 movs r3, #1
80045be: e04e b.n 800465e <HAL_TIM_Base_Start_IT+0xb6>
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
80045c0: 687b ldr r3, [r7, #4]
80045c2: 2202 movs r2, #2
80045c4: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Enable the TIM Update interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
80045c8: 687b ldr r3, [r7, #4]
80045ca: 681b ldr r3, [r3, #0]
80045cc: 68da ldr r2, [r3, #12]
80045ce: 687b ldr r3, [r7, #4]
80045d0: 681b ldr r3, [r3, #0]
80045d2: f042 0201 orr.w r2, r2, #1
80045d6: 60da str r2, [r3, #12]
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80045d8: 687b ldr r3, [r7, #4]
80045da: 681b ldr r3, [r3, #0]
80045dc: 4a23 ldr r2, [pc, #140] @ (800466c <HAL_TIM_Base_Start_IT+0xc4>)
80045de: 4293 cmp r3, r2
80045e0: d022 beq.n 8004628 <HAL_TIM_Base_Start_IT+0x80>
80045e2: 687b ldr r3, [r7, #4]
80045e4: 681b ldr r3, [r3, #0]
80045e6: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80045ea: d01d beq.n 8004628 <HAL_TIM_Base_Start_IT+0x80>
80045ec: 687b ldr r3, [r7, #4]
80045ee: 681b ldr r3, [r3, #0]
80045f0: 4a1f ldr r2, [pc, #124] @ (8004670 <HAL_TIM_Base_Start_IT+0xc8>)
80045f2: 4293 cmp r3, r2
80045f4: d018 beq.n 8004628 <HAL_TIM_Base_Start_IT+0x80>
80045f6: 687b ldr r3, [r7, #4]
80045f8: 681b ldr r3, [r3, #0]
80045fa: 4a1e ldr r2, [pc, #120] @ (8004674 <HAL_TIM_Base_Start_IT+0xcc>)
80045fc: 4293 cmp r3, r2
80045fe: d013 beq.n 8004628 <HAL_TIM_Base_Start_IT+0x80>
8004600: 687b ldr r3, [r7, #4]
8004602: 681b ldr r3, [r3, #0]
8004604: 4a1c ldr r2, [pc, #112] @ (8004678 <HAL_TIM_Base_Start_IT+0xd0>)
8004606: 4293 cmp r3, r2
8004608: d00e beq.n 8004628 <HAL_TIM_Base_Start_IT+0x80>
800460a: 687b ldr r3, [r7, #4]
800460c: 681b ldr r3, [r3, #0]
800460e: 4a1b ldr r2, [pc, #108] @ (800467c <HAL_TIM_Base_Start_IT+0xd4>)
8004610: 4293 cmp r3, r2
8004612: d009 beq.n 8004628 <HAL_TIM_Base_Start_IT+0x80>
8004614: 687b ldr r3, [r7, #4]
8004616: 681b ldr r3, [r3, #0]
8004618: 4a19 ldr r2, [pc, #100] @ (8004680 <HAL_TIM_Base_Start_IT+0xd8>)
800461a: 4293 cmp r3, r2
800461c: d004 beq.n 8004628 <HAL_TIM_Base_Start_IT+0x80>
800461e: 687b ldr r3, [r7, #4]
8004620: 681b ldr r3, [r3, #0]
8004622: 4a18 ldr r2, [pc, #96] @ (8004684 <HAL_TIM_Base_Start_IT+0xdc>)
8004624: 4293 cmp r3, r2
8004626: d111 bne.n 800464c <HAL_TIM_Base_Start_IT+0xa4>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8004628: 687b ldr r3, [r7, #4]
800462a: 681b ldr r3, [r3, #0]
800462c: 689b ldr r3, [r3, #8]
800462e: f003 0307 and.w r3, r3, #7
8004632: 60fb str r3, [r7, #12]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8004634: 68fb ldr r3, [r7, #12]
8004636: 2b06 cmp r3, #6
8004638: d010 beq.n 800465c <HAL_TIM_Base_Start_IT+0xb4>
{
__HAL_TIM_ENABLE(htim);
800463a: 687b ldr r3, [r7, #4]
800463c: 681b ldr r3, [r3, #0]
800463e: 681a ldr r2, [r3, #0]
8004640: 687b ldr r3, [r7, #4]
8004642: 681b ldr r3, [r3, #0]
8004644: f042 0201 orr.w r2, r2, #1
8004648: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
800464a: e007 b.n 800465c <HAL_TIM_Base_Start_IT+0xb4>
}
}
else
{
__HAL_TIM_ENABLE(htim);
800464c: 687b ldr r3, [r7, #4]
800464e: 681b ldr r3, [r3, #0]
8004650: 681a ldr r2, [r3, #0]
8004652: 687b ldr r3, [r7, #4]
8004654: 681b ldr r3, [r3, #0]
8004656: f042 0201 orr.w r2, r2, #1
800465a: 601a str r2, [r3, #0]
}
/* Return function status */
return HAL_OK;
800465c: 2300 movs r3, #0
}
800465e: 4618 mov r0, r3
8004660: 3714 adds r7, #20
8004662: 46bd mov sp, r7
8004664: f85d 7b04 ldr.w r7, [sp], #4
8004668: 4770 bx lr
800466a: bf00 nop
800466c: 40010000 .word 0x40010000
8004670: 40000400 .word 0x40000400
8004674: 40000800 .word 0x40000800
8004678: 40000c00 .word 0x40000c00
800467c: 40010400 .word 0x40010400
8004680: 40014000 .word 0x40014000
8004684: 40001800 .word 0x40001800
08004688 <HAL_TIM_PWM_Init>:
* Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
* @param htim TIM PWM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
{
8004688: b580 push {r7, lr}
800468a: b082 sub sp, #8
800468c: af00 add r7, sp, #0
800468e: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
8004690: 687b ldr r3, [r7, #4]
8004692: 2b00 cmp r3, #0
8004694: d101 bne.n 800469a <HAL_TIM_PWM_Init+0x12>
{
return HAL_ERROR;
8004696: 2301 movs r3, #1
8004698: e041 b.n 800471e <HAL_TIM_PWM_Init+0x96>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
800469a: 687b ldr r3, [r7, #4]
800469c: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
80046a0: b2db uxtb r3, r3
80046a2: 2b00 cmp r3, #0
80046a4: d106 bne.n 80046b4 <HAL_TIM_PWM_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
80046a6: 687b ldr r3, [r7, #4]
80046a8: 2200 movs r2, #0
80046aa: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->PWM_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
80046ae: 6878 ldr r0, [r7, #4]
80046b0: f000 f839 bl 8004726 <HAL_TIM_PWM_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
80046b4: 687b ldr r3, [r7, #4]
80046b6: 2202 movs r2, #2
80046b8: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Init the base time for the PWM */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
80046bc: 687b ldr r3, [r7, #4]
80046be: 681a ldr r2, [r3, #0]
80046c0: 687b ldr r3, [r7, #4]
80046c2: 3304 adds r3, #4
80046c4: 4619 mov r1, r3
80046c6: 4610 mov r0, r2
80046c8: f000 fada bl 8004c80 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
80046cc: 687b ldr r3, [r7, #4]
80046ce: 2201 movs r2, #1
80046d0: f883 2046 strb.w r2, [r3, #70] @ 0x46
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80046d4: 687b ldr r3, [r7, #4]
80046d6: 2201 movs r2, #1
80046d8: f883 203e strb.w r2, [r3, #62] @ 0x3e
80046dc: 687b ldr r3, [r7, #4]
80046de: 2201 movs r2, #1
80046e0: f883 203f strb.w r2, [r3, #63] @ 0x3f
80046e4: 687b ldr r3, [r7, #4]
80046e6: 2201 movs r2, #1
80046e8: f883 2040 strb.w r2, [r3, #64] @ 0x40
80046ec: 687b ldr r3, [r7, #4]
80046ee: 2201 movs r2, #1
80046f0: f883 2041 strb.w r2, [r3, #65] @ 0x41
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
80046f4: 687b ldr r3, [r7, #4]
80046f6: 2201 movs r2, #1
80046f8: f883 2042 strb.w r2, [r3, #66] @ 0x42
80046fc: 687b ldr r3, [r7, #4]
80046fe: 2201 movs r2, #1
8004700: f883 2043 strb.w r2, [r3, #67] @ 0x43
8004704: 687b ldr r3, [r7, #4]
8004706: 2201 movs r2, #1
8004708: f883 2044 strb.w r2, [r3, #68] @ 0x44
800470c: 687b ldr r3, [r7, #4]
800470e: 2201 movs r2, #1
8004710: f883 2045 strb.w r2, [r3, #69] @ 0x45
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8004714: 687b ldr r3, [r7, #4]
8004716: 2201 movs r2, #1
8004718: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
800471c: 2300 movs r3, #0
}
800471e: 4618 mov r0, r3
8004720: 3708 adds r7, #8
8004722: 46bd mov sp, r7
8004724: bd80 pop {r7, pc}
08004726 <HAL_TIM_PWM_MspInit>:
* @brief Initializes the TIM PWM MSP.
* @param htim TIM PWM handle
* @retval None
*/
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
{
8004726: b480 push {r7}
8004728: b083 sub sp, #12
800472a: af00 add r7, sp, #0
800472c: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_MspInit could be implemented in the user file
*/
}
800472e: bf00 nop
8004730: 370c adds r7, #12
8004732: 46bd mov sp, r7
8004734: f85d 7b04 ldr.w r7, [sp], #4
8004738: 4770 bx lr
0800473a <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
800473a: b580 push {r7, lr}
800473c: b084 sub sp, #16
800473e: af00 add r7, sp, #0
8004740: 6078 str r0, [r7, #4]
uint32_t itsource = htim->Instance->DIER;
8004742: 687b ldr r3, [r7, #4]
8004744: 681b ldr r3, [r3, #0]
8004746: 68db ldr r3, [r3, #12]
8004748: 60fb str r3, [r7, #12]
uint32_t itflag = htim->Instance->SR;
800474a: 687b ldr r3, [r7, #4]
800474c: 681b ldr r3, [r3, #0]
800474e: 691b ldr r3, [r3, #16]
8004750: 60bb str r3, [r7, #8]
/* Capture compare 1 event */
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
8004752: 68bb ldr r3, [r7, #8]
8004754: f003 0302 and.w r3, r3, #2
8004758: 2b00 cmp r3, #0
800475a: d020 beq.n 800479e <HAL_TIM_IRQHandler+0x64>
{
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
800475c: 68fb ldr r3, [r7, #12]
800475e: f003 0302 and.w r3, r3, #2
8004762: 2b00 cmp r3, #0
8004764: d01b beq.n 800479e <HAL_TIM_IRQHandler+0x64>
{
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
8004766: 687b ldr r3, [r7, #4]
8004768: 681b ldr r3, [r3, #0]
800476a: f06f 0202 mvn.w r2, #2
800476e: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8004770: 687b ldr r3, [r7, #4]
8004772: 2201 movs r2, #1
8004774: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8004776: 687b ldr r3, [r7, #4]
8004778: 681b ldr r3, [r3, #0]
800477a: 699b ldr r3, [r3, #24]
800477c: f003 0303 and.w r3, r3, #3
8004780: 2b00 cmp r3, #0
8004782: d003 beq.n 800478c <HAL_TIM_IRQHandler+0x52>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8004784: 6878 ldr r0, [r7, #4]
8004786: f000 fa5c bl 8004c42 <HAL_TIM_IC_CaptureCallback>
800478a: e005 b.n 8004798 <HAL_TIM_IRQHandler+0x5e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800478c: 6878 ldr r0, [r7, #4]
800478e: f000 fa4e bl 8004c2e <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8004792: 6878 ldr r0, [r7, #4]
8004794: f000 fa5f bl 8004c56 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8004798: 687b ldr r3, [r7, #4]
800479a: 2200 movs r2, #0
800479c: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
800479e: 68bb ldr r3, [r7, #8]
80047a0: f003 0304 and.w r3, r3, #4
80047a4: 2b00 cmp r3, #0
80047a6: d020 beq.n 80047ea <HAL_TIM_IRQHandler+0xb0>
{
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
80047a8: 68fb ldr r3, [r7, #12]
80047aa: f003 0304 and.w r3, r3, #4
80047ae: 2b00 cmp r3, #0
80047b0: d01b beq.n 80047ea <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
80047b2: 687b ldr r3, [r7, #4]
80047b4: 681b ldr r3, [r3, #0]
80047b6: f06f 0204 mvn.w r2, #4
80047ba: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
80047bc: 687b ldr r3, [r7, #4]
80047be: 2202 movs r2, #2
80047c0: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
80047c2: 687b ldr r3, [r7, #4]
80047c4: 681b ldr r3, [r3, #0]
80047c6: 699b ldr r3, [r3, #24]
80047c8: f403 7340 and.w r3, r3, #768 @ 0x300
80047cc: 2b00 cmp r3, #0
80047ce: d003 beq.n 80047d8 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
80047d0: 6878 ldr r0, [r7, #4]
80047d2: f000 fa36 bl 8004c42 <HAL_TIM_IC_CaptureCallback>
80047d6: e005 b.n 80047e4 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
80047d8: 6878 ldr r0, [r7, #4]
80047da: f000 fa28 bl 8004c2e <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80047de: 6878 ldr r0, [r7, #4]
80047e0: f000 fa39 bl 8004c56 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80047e4: 687b ldr r3, [r7, #4]
80047e6: 2200 movs r2, #0
80047e8: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
80047ea: 68bb ldr r3, [r7, #8]
80047ec: f003 0308 and.w r3, r3, #8
80047f0: 2b00 cmp r3, #0
80047f2: d020 beq.n 8004836 <HAL_TIM_IRQHandler+0xfc>
{
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
80047f4: 68fb ldr r3, [r7, #12]
80047f6: f003 0308 and.w r3, r3, #8
80047fa: 2b00 cmp r3, #0
80047fc: d01b beq.n 8004836 <HAL_TIM_IRQHandler+0xfc>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
80047fe: 687b ldr r3, [r7, #4]
8004800: 681b ldr r3, [r3, #0]
8004802: f06f 0208 mvn.w r2, #8
8004806: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8004808: 687b ldr r3, [r7, #4]
800480a: 2204 movs r2, #4
800480c: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
800480e: 687b ldr r3, [r7, #4]
8004810: 681b ldr r3, [r3, #0]
8004812: 69db ldr r3, [r3, #28]
8004814: f003 0303 and.w r3, r3, #3
8004818: 2b00 cmp r3, #0
800481a: d003 beq.n 8004824 <HAL_TIM_IRQHandler+0xea>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800481c: 6878 ldr r0, [r7, #4]
800481e: f000 fa10 bl 8004c42 <HAL_TIM_IC_CaptureCallback>
8004822: e005 b.n 8004830 <HAL_TIM_IRQHandler+0xf6>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8004824: 6878 ldr r0, [r7, #4]
8004826: f000 fa02 bl 8004c2e <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
800482a: 6878 ldr r0, [r7, #4]
800482c: f000 fa13 bl 8004c56 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8004830: 687b ldr r3, [r7, #4]
8004832: 2200 movs r2, #0
8004834: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
8004836: 68bb ldr r3, [r7, #8]
8004838: f003 0310 and.w r3, r3, #16
800483c: 2b00 cmp r3, #0
800483e: d020 beq.n 8004882 <HAL_TIM_IRQHandler+0x148>
{
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
8004840: 68fb ldr r3, [r7, #12]
8004842: f003 0310 and.w r3, r3, #16
8004846: 2b00 cmp r3, #0
8004848: d01b beq.n 8004882 <HAL_TIM_IRQHandler+0x148>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
800484a: 687b ldr r3, [r7, #4]
800484c: 681b ldr r3, [r3, #0]
800484e: f06f 0210 mvn.w r2, #16
8004852: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8004854: 687b ldr r3, [r7, #4]
8004856: 2208 movs r2, #8
8004858: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
800485a: 687b ldr r3, [r7, #4]
800485c: 681b ldr r3, [r3, #0]
800485e: 69db ldr r3, [r3, #28]
8004860: f403 7340 and.w r3, r3, #768 @ 0x300
8004864: 2b00 cmp r3, #0
8004866: d003 beq.n 8004870 <HAL_TIM_IRQHandler+0x136>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8004868: 6878 ldr r0, [r7, #4]
800486a: f000 f9ea bl 8004c42 <HAL_TIM_IC_CaptureCallback>
800486e: e005 b.n 800487c <HAL_TIM_IRQHandler+0x142>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8004870: 6878 ldr r0, [r7, #4]
8004872: f000 f9dc bl 8004c2e <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8004876: 6878 ldr r0, [r7, #4]
8004878: f000 f9ed bl 8004c56 <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800487c: 687b ldr r3, [r7, #4]
800487e: 2200 movs r2, #0
8004880: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
8004882: 68bb ldr r3, [r7, #8]
8004884: f003 0301 and.w r3, r3, #1
8004888: 2b00 cmp r3, #0
800488a: d00c beq.n 80048a6 <HAL_TIM_IRQHandler+0x16c>
{
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
800488c: 68fb ldr r3, [r7, #12]
800488e: f003 0301 and.w r3, r3, #1
8004892: 2b00 cmp r3, #0
8004894: d007 beq.n 80048a6 <HAL_TIM_IRQHandler+0x16c>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
8004896: 687b ldr r3, [r7, #4]
8004898: 681b ldr r3, [r3, #0]
800489a: f06f 0201 mvn.w r2, #1
800489e: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
80048a0: 6878 ldr r0, [r7, #4]
80048a2: f7fc fd55 bl 8001350 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
80048a6: 68bb ldr r3, [r7, #8]
80048a8: f003 0380 and.w r3, r3, #128 @ 0x80
80048ac: 2b00 cmp r3, #0
80048ae: d00c beq.n 80048ca <HAL_TIM_IRQHandler+0x190>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
80048b0: 68fb ldr r3, [r7, #12]
80048b2: f003 0380 and.w r3, r3, #128 @ 0x80
80048b6: 2b00 cmp r3, #0
80048b8: d007 beq.n 80048ca <HAL_TIM_IRQHandler+0x190>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
80048ba: 687b ldr r3, [r7, #4]
80048bc: 681b ldr r3, [r3, #0]
80048be: f06f 0280 mvn.w r2, #128 @ 0x80
80048c2: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
80048c4: 6878 ldr r0, [r7, #4]
80048c6: f000 fda9 bl 800541c <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
80048ca: 68bb ldr r3, [r7, #8]
80048cc: f003 0340 and.w r3, r3, #64 @ 0x40
80048d0: 2b00 cmp r3, #0
80048d2: d00c beq.n 80048ee <HAL_TIM_IRQHandler+0x1b4>
{
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
80048d4: 68fb ldr r3, [r7, #12]
80048d6: f003 0340 and.w r3, r3, #64 @ 0x40
80048da: 2b00 cmp r3, #0
80048dc: d007 beq.n 80048ee <HAL_TIM_IRQHandler+0x1b4>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
80048de: 687b ldr r3, [r7, #4]
80048e0: 681b ldr r3, [r3, #0]
80048e2: f06f 0240 mvn.w r2, #64 @ 0x40
80048e6: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
80048e8: 6878 ldr r0, [r7, #4]
80048ea: f000 f9be bl 8004c6a <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
80048ee: 68bb ldr r3, [r7, #8]
80048f0: f003 0320 and.w r3, r3, #32
80048f4: 2b00 cmp r3, #0
80048f6: d00c beq.n 8004912 <HAL_TIM_IRQHandler+0x1d8>
{
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
80048f8: 68fb ldr r3, [r7, #12]
80048fa: f003 0320 and.w r3, r3, #32
80048fe: 2b00 cmp r3, #0
8004900: d007 beq.n 8004912 <HAL_TIM_IRQHandler+0x1d8>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
8004902: 687b ldr r3, [r7, #4]
8004904: 681b ldr r3, [r3, #0]
8004906: f06f 0220 mvn.w r2, #32
800490a: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
800490c: 6878 ldr r0, [r7, #4]
800490e: f000 fd7b bl 8005408 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8004912: bf00 nop
8004914: 3710 adds r7, #16
8004916: 46bd mov sp, r7
8004918: bd80 pop {r7, pc}
...
0800491c <HAL_TIM_PWM_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
800491c: b580 push {r7, lr}
800491e: b086 sub sp, #24
8004920: af00 add r7, sp, #0
8004922: 60f8 str r0, [r7, #12]
8004924: 60b9 str r1, [r7, #8]
8004926: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8004928: 2300 movs r3, #0
800492a: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
/* Process Locked */
__HAL_LOCK(htim);
800492c: 68fb ldr r3, [r7, #12]
800492e: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8004932: 2b01 cmp r3, #1
8004934: d101 bne.n 800493a <HAL_TIM_PWM_ConfigChannel+0x1e>
8004936: 2302 movs r3, #2
8004938: e0ae b.n 8004a98 <HAL_TIM_PWM_ConfigChannel+0x17c>
800493a: 68fb ldr r3, [r7, #12]
800493c: 2201 movs r2, #1
800493e: f883 203c strb.w r2, [r3, #60] @ 0x3c
switch (Channel)
8004942: 687b ldr r3, [r7, #4]
8004944: 2b0c cmp r3, #12
8004946: f200 809f bhi.w 8004a88 <HAL_TIM_PWM_ConfigChannel+0x16c>
800494a: a201 add r2, pc, #4 @ (adr r2, 8004950 <HAL_TIM_PWM_ConfigChannel+0x34>)
800494c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8004950: 08004985 .word 0x08004985
8004954: 08004a89 .word 0x08004a89
8004958: 08004a89 .word 0x08004a89
800495c: 08004a89 .word 0x08004a89
8004960: 080049c5 .word 0x080049c5
8004964: 08004a89 .word 0x08004a89
8004968: 08004a89 .word 0x08004a89
800496c: 08004a89 .word 0x08004a89
8004970: 08004a07 .word 0x08004a07
8004974: 08004a89 .word 0x08004a89
8004978: 08004a89 .word 0x08004a89
800497c: 08004a89 .word 0x08004a89
8004980: 08004a47 .word 0x08004a47
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the Channel 1 in PWM mode */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8004984: 68fb ldr r3, [r7, #12]
8004986: 681b ldr r3, [r3, #0]
8004988: 68b9 ldr r1, [r7, #8]
800498a: 4618 mov r0, r3
800498c: f000 fa24 bl 8004dd8 <TIM_OC1_SetConfig>
/* Set the Preload enable bit for channel1 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8004990: 68fb ldr r3, [r7, #12]
8004992: 681b ldr r3, [r3, #0]
8004994: 699a ldr r2, [r3, #24]
8004996: 68fb ldr r3, [r7, #12]
8004998: 681b ldr r3, [r3, #0]
800499a: f042 0208 orr.w r2, r2, #8
800499e: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
80049a0: 68fb ldr r3, [r7, #12]
80049a2: 681b ldr r3, [r3, #0]
80049a4: 699a ldr r2, [r3, #24]
80049a6: 68fb ldr r3, [r7, #12]
80049a8: 681b ldr r3, [r3, #0]
80049aa: f022 0204 bic.w r2, r2, #4
80049ae: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
80049b0: 68fb ldr r3, [r7, #12]
80049b2: 681b ldr r3, [r3, #0]
80049b4: 6999 ldr r1, [r3, #24]
80049b6: 68bb ldr r3, [r7, #8]
80049b8: 691a ldr r2, [r3, #16]
80049ba: 68fb ldr r3, [r7, #12]
80049bc: 681b ldr r3, [r3, #0]
80049be: 430a orrs r2, r1
80049c0: 619a str r2, [r3, #24]
break;
80049c2: e064 b.n 8004a8e <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the Channel 2 in PWM mode */
TIM_OC2_SetConfig(htim->Instance, sConfig);
80049c4: 68fb ldr r3, [r7, #12]
80049c6: 681b ldr r3, [r3, #0]
80049c8: 68b9 ldr r1, [r7, #8]
80049ca: 4618 mov r0, r3
80049cc: f000 fa74 bl 8004eb8 <TIM_OC2_SetConfig>
/* Set the Preload enable bit for channel2 */
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
80049d0: 68fb ldr r3, [r7, #12]
80049d2: 681b ldr r3, [r3, #0]
80049d4: 699a ldr r2, [r3, #24]
80049d6: 68fb ldr r3, [r7, #12]
80049d8: 681b ldr r3, [r3, #0]
80049da: f442 6200 orr.w r2, r2, #2048 @ 0x800
80049de: 619a str r2, [r3, #24]
/* Configure the Output Fast mode */
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
80049e0: 68fb ldr r3, [r7, #12]
80049e2: 681b ldr r3, [r3, #0]
80049e4: 699a ldr r2, [r3, #24]
80049e6: 68fb ldr r3, [r7, #12]
80049e8: 681b ldr r3, [r3, #0]
80049ea: f422 6280 bic.w r2, r2, #1024 @ 0x400
80049ee: 619a str r2, [r3, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
80049f0: 68fb ldr r3, [r7, #12]
80049f2: 681b ldr r3, [r3, #0]
80049f4: 6999 ldr r1, [r3, #24]
80049f6: 68bb ldr r3, [r7, #8]
80049f8: 691b ldr r3, [r3, #16]
80049fa: 021a lsls r2, r3, #8
80049fc: 68fb ldr r3, [r7, #12]
80049fe: 681b ldr r3, [r3, #0]
8004a00: 430a orrs r2, r1
8004a02: 619a str r2, [r3, #24]
break;
8004a04: e043 b.n 8004a8e <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the Channel 3 in PWM mode */
TIM_OC3_SetConfig(htim->Instance, sConfig);
8004a06: 68fb ldr r3, [r7, #12]
8004a08: 681b ldr r3, [r3, #0]
8004a0a: 68b9 ldr r1, [r7, #8]
8004a0c: 4618 mov r0, r3
8004a0e: f000 fac9 bl 8004fa4 <TIM_OC3_SetConfig>
/* Set the Preload enable bit for channel3 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
8004a12: 68fb ldr r3, [r7, #12]
8004a14: 681b ldr r3, [r3, #0]
8004a16: 69da ldr r2, [r3, #28]
8004a18: 68fb ldr r3, [r7, #12]
8004a1a: 681b ldr r3, [r3, #0]
8004a1c: f042 0208 orr.w r2, r2, #8
8004a20: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
8004a22: 68fb ldr r3, [r7, #12]
8004a24: 681b ldr r3, [r3, #0]
8004a26: 69da ldr r2, [r3, #28]
8004a28: 68fb ldr r3, [r7, #12]
8004a2a: 681b ldr r3, [r3, #0]
8004a2c: f022 0204 bic.w r2, r2, #4
8004a30: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
8004a32: 68fb ldr r3, [r7, #12]
8004a34: 681b ldr r3, [r3, #0]
8004a36: 69d9 ldr r1, [r3, #28]
8004a38: 68bb ldr r3, [r7, #8]
8004a3a: 691a ldr r2, [r3, #16]
8004a3c: 68fb ldr r3, [r7, #12]
8004a3e: 681b ldr r3, [r3, #0]
8004a40: 430a orrs r2, r1
8004a42: 61da str r2, [r3, #28]
break;
8004a44: e023 b.n 8004a8e <HAL_TIM_PWM_ConfigChannel+0x172>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the Channel 4 in PWM mode */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8004a46: 68fb ldr r3, [r7, #12]
8004a48: 681b ldr r3, [r3, #0]
8004a4a: 68b9 ldr r1, [r7, #8]
8004a4c: 4618 mov r0, r3
8004a4e: f000 fb1d bl 800508c <TIM_OC4_SetConfig>
/* Set the Preload enable bit for channel4 */
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
8004a52: 68fb ldr r3, [r7, #12]
8004a54: 681b ldr r3, [r3, #0]
8004a56: 69da ldr r2, [r3, #28]
8004a58: 68fb ldr r3, [r7, #12]
8004a5a: 681b ldr r3, [r3, #0]
8004a5c: f442 6200 orr.w r2, r2, #2048 @ 0x800
8004a60: 61da str r2, [r3, #28]
/* Configure the Output Fast mode */
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
8004a62: 68fb ldr r3, [r7, #12]
8004a64: 681b ldr r3, [r3, #0]
8004a66: 69da ldr r2, [r3, #28]
8004a68: 68fb ldr r3, [r7, #12]
8004a6a: 681b ldr r3, [r3, #0]
8004a6c: f422 6280 bic.w r2, r2, #1024 @ 0x400
8004a70: 61da str r2, [r3, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
8004a72: 68fb ldr r3, [r7, #12]
8004a74: 681b ldr r3, [r3, #0]
8004a76: 69d9 ldr r1, [r3, #28]
8004a78: 68bb ldr r3, [r7, #8]
8004a7a: 691b ldr r3, [r3, #16]
8004a7c: 021a lsls r2, r3, #8
8004a7e: 68fb ldr r3, [r7, #12]
8004a80: 681b ldr r3, [r3, #0]
8004a82: 430a orrs r2, r1
8004a84: 61da str r2, [r3, #28]
break;
8004a86: e002 b.n 8004a8e <HAL_TIM_PWM_ConfigChannel+0x172>
}
default:
status = HAL_ERROR;
8004a88: 2301 movs r3, #1
8004a8a: 75fb strb r3, [r7, #23]
break;
8004a8c: bf00 nop
}
__HAL_UNLOCK(htim);
8004a8e: 68fb ldr r3, [r7, #12]
8004a90: 2200 movs r2, #0
8004a92: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
8004a96: 7dfb ldrb r3, [r7, #23]
}
8004a98: 4618 mov r0, r3
8004a9a: 3718 adds r7, #24
8004a9c: 46bd mov sp, r7
8004a9e: bd80 pop {r7, pc}
08004aa0 <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
8004aa0: b580 push {r7, lr}
8004aa2: b084 sub sp, #16
8004aa4: af00 add r7, sp, #0
8004aa6: 6078 str r0, [r7, #4]
8004aa8: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8004aaa: 2300 movs r3, #0
8004aac: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
8004aae: 687b ldr r3, [r7, #4]
8004ab0: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8004ab4: 2b01 cmp r3, #1
8004ab6: d101 bne.n 8004abc <HAL_TIM_ConfigClockSource+0x1c>
8004ab8: 2302 movs r3, #2
8004aba: e0b4 b.n 8004c26 <HAL_TIM_ConfigClockSource+0x186>
8004abc: 687b ldr r3, [r7, #4]
8004abe: 2201 movs r2, #1
8004ac0: f883 203c strb.w r2, [r3, #60] @ 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8004ac4: 687b ldr r3, [r7, #4]
8004ac6: 2202 movs r2, #2
8004ac8: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
8004acc: 687b ldr r3, [r7, #4]
8004ace: 681b ldr r3, [r3, #0]
8004ad0: 689b ldr r3, [r3, #8]
8004ad2: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
8004ad4: 68bb ldr r3, [r7, #8]
8004ad6: f023 0377 bic.w r3, r3, #119 @ 0x77
8004ada: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8004adc: 68bb ldr r3, [r7, #8]
8004ade: f423 437f bic.w r3, r3, #65280 @ 0xff00
8004ae2: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
8004ae4: 687b ldr r3, [r7, #4]
8004ae6: 681b ldr r3, [r3, #0]
8004ae8: 68ba ldr r2, [r7, #8]
8004aea: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
8004aec: 683b ldr r3, [r7, #0]
8004aee: 681b ldr r3, [r3, #0]
8004af0: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8004af4: d03e beq.n 8004b74 <HAL_TIM_ConfigClockSource+0xd4>
8004af6: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8004afa: f200 8087 bhi.w 8004c0c <HAL_TIM_ConfigClockSource+0x16c>
8004afe: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8004b02: f000 8086 beq.w 8004c12 <HAL_TIM_ConfigClockSource+0x172>
8004b06: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8004b0a: d87f bhi.n 8004c0c <HAL_TIM_ConfigClockSource+0x16c>
8004b0c: 2b70 cmp r3, #112 @ 0x70
8004b0e: d01a beq.n 8004b46 <HAL_TIM_ConfigClockSource+0xa6>
8004b10: 2b70 cmp r3, #112 @ 0x70
8004b12: d87b bhi.n 8004c0c <HAL_TIM_ConfigClockSource+0x16c>
8004b14: 2b60 cmp r3, #96 @ 0x60
8004b16: d050 beq.n 8004bba <HAL_TIM_ConfigClockSource+0x11a>
8004b18: 2b60 cmp r3, #96 @ 0x60
8004b1a: d877 bhi.n 8004c0c <HAL_TIM_ConfigClockSource+0x16c>
8004b1c: 2b50 cmp r3, #80 @ 0x50
8004b1e: d03c beq.n 8004b9a <HAL_TIM_ConfigClockSource+0xfa>
8004b20: 2b50 cmp r3, #80 @ 0x50
8004b22: d873 bhi.n 8004c0c <HAL_TIM_ConfigClockSource+0x16c>
8004b24: 2b40 cmp r3, #64 @ 0x40
8004b26: d058 beq.n 8004bda <HAL_TIM_ConfigClockSource+0x13a>
8004b28: 2b40 cmp r3, #64 @ 0x40
8004b2a: d86f bhi.n 8004c0c <HAL_TIM_ConfigClockSource+0x16c>
8004b2c: 2b30 cmp r3, #48 @ 0x30
8004b2e: d064 beq.n 8004bfa <HAL_TIM_ConfigClockSource+0x15a>
8004b30: 2b30 cmp r3, #48 @ 0x30
8004b32: d86b bhi.n 8004c0c <HAL_TIM_ConfigClockSource+0x16c>
8004b34: 2b20 cmp r3, #32
8004b36: d060 beq.n 8004bfa <HAL_TIM_ConfigClockSource+0x15a>
8004b38: 2b20 cmp r3, #32
8004b3a: d867 bhi.n 8004c0c <HAL_TIM_ConfigClockSource+0x16c>
8004b3c: 2b00 cmp r3, #0
8004b3e: d05c beq.n 8004bfa <HAL_TIM_ConfigClockSource+0x15a>
8004b40: 2b10 cmp r3, #16
8004b42: d05a beq.n 8004bfa <HAL_TIM_ConfigClockSource+0x15a>
8004b44: e062 b.n 8004c0c <HAL_TIM_ConfigClockSource+0x16c>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8004b46: 687b ldr r3, [r7, #4]
8004b48: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
8004b4a: 683b ldr r3, [r7, #0]
8004b4c: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
8004b4e: 683b ldr r3, [r7, #0]
8004b50: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
8004b52: 683b ldr r3, [r7, #0]
8004b54: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8004b56: f000 fb69 bl 800522c <TIM_ETR_SetConfig>
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
8004b5a: 687b ldr r3, [r7, #4]
8004b5c: 681b ldr r3, [r3, #0]
8004b5e: 689b ldr r3, [r3, #8]
8004b60: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
8004b62: 68bb ldr r3, [r7, #8]
8004b64: f043 0377 orr.w r3, r3, #119 @ 0x77
8004b68: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8004b6a: 687b ldr r3, [r7, #4]
8004b6c: 681b ldr r3, [r3, #0]
8004b6e: 68ba ldr r2, [r7, #8]
8004b70: 609a str r2, [r3, #8]
break;
8004b72: e04f b.n 8004c14 <HAL_TIM_ConfigClockSource+0x174>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8004b74: 687b ldr r3, [r7, #4]
8004b76: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
8004b78: 683b ldr r3, [r7, #0]
8004b7a: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
8004b7c: 683b ldr r3, [r7, #0]
8004b7e: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
8004b80: 683b ldr r3, [r7, #0]
8004b82: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8004b84: f000 fb52 bl 800522c <TIM_ETR_SetConfig>
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
8004b88: 687b ldr r3, [r7, #4]
8004b8a: 681b ldr r3, [r3, #0]
8004b8c: 689a ldr r2, [r3, #8]
8004b8e: 687b ldr r3, [r7, #4]
8004b90: 681b ldr r3, [r3, #0]
8004b92: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8004b96: 609a str r2, [r3, #8]
break;
8004b98: e03c b.n 8004c14 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8004b9a: 687b ldr r3, [r7, #4]
8004b9c: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
8004b9e: 683b ldr r3, [r7, #0]
8004ba0: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8004ba2: 683b ldr r3, [r7, #0]
8004ba4: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
8004ba6: 461a mov r2, r3
8004ba8: f000 fac6 bl 8005138 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
8004bac: 687b ldr r3, [r7, #4]
8004bae: 681b ldr r3, [r3, #0]
8004bb0: 2150 movs r1, #80 @ 0x50
8004bb2: 4618 mov r0, r3
8004bb4: f000 fb1f bl 80051f6 <TIM_ITRx_SetConfig>
break;
8004bb8: e02c b.n 8004c14 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
8004bba: 687b ldr r3, [r7, #4]
8004bbc: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
8004bbe: 683b ldr r3, [r7, #0]
8004bc0: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8004bc2: 683b ldr r3, [r7, #0]
8004bc4: 68db ldr r3, [r3, #12]
TIM_TI2_ConfigInputStage(htim->Instance,
8004bc6: 461a mov r2, r3
8004bc8: f000 fae5 bl 8005196 <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
8004bcc: 687b ldr r3, [r7, #4]
8004bce: 681b ldr r3, [r3, #0]
8004bd0: 2160 movs r1, #96 @ 0x60
8004bd2: 4618 mov r0, r3
8004bd4: f000 fb0f bl 80051f6 <TIM_ITRx_SetConfig>
break;
8004bd8: e01c b.n 8004c14 <HAL_TIM_ConfigClockSource+0x174>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8004bda: 687b ldr r3, [r7, #4]
8004bdc: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
8004bde: 683b ldr r3, [r7, #0]
8004be0: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8004be2: 683b ldr r3, [r7, #0]
8004be4: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
8004be6: 461a mov r2, r3
8004be8: f000 faa6 bl 8005138 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
8004bec: 687b ldr r3, [r7, #4]
8004bee: 681b ldr r3, [r3, #0]
8004bf0: 2140 movs r1, #64 @ 0x40
8004bf2: 4618 mov r0, r3
8004bf4: f000 faff bl 80051f6 <TIM_ITRx_SetConfig>
break;
8004bf8: e00c b.n 8004c14 <HAL_TIM_ConfigClockSource+0x174>
case TIM_CLOCKSOURCE_ITR3:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
8004bfa: 687b ldr r3, [r7, #4]
8004bfc: 681a ldr r2, [r3, #0]
8004bfe: 683b ldr r3, [r7, #0]
8004c00: 681b ldr r3, [r3, #0]
8004c02: 4619 mov r1, r3
8004c04: 4610 mov r0, r2
8004c06: f000 faf6 bl 80051f6 <TIM_ITRx_SetConfig>
break;
8004c0a: e003 b.n 8004c14 <HAL_TIM_ConfigClockSource+0x174>
}
default:
status = HAL_ERROR;
8004c0c: 2301 movs r3, #1
8004c0e: 73fb strb r3, [r7, #15]
break;
8004c10: e000 b.n 8004c14 <HAL_TIM_ConfigClockSource+0x174>
break;
8004c12: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
8004c14: 687b ldr r3, [r7, #4]
8004c16: 2201 movs r2, #1
8004c18: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
8004c1c: 687b ldr r3, [r7, #4]
8004c1e: 2200 movs r2, #0
8004c20: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
8004c24: 7bfb ldrb r3, [r7, #15]
}
8004c26: 4618 mov r0, r3
8004c28: 3710 adds r7, #16
8004c2a: 46bd mov sp, r7
8004c2c: bd80 pop {r7, pc}
08004c2e <HAL_TIM_OC_DelayElapsedCallback>:
* @brief Output Compare callback in non-blocking mode
* @param htim TIM OC handle
* @retval None
*/
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8004c2e: b480 push {r7}
8004c30: b083 sub sp, #12
8004c32: af00 add r7, sp, #0
8004c34: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
*/
}
8004c36: bf00 nop
8004c38: 370c adds r7, #12
8004c3a: 46bd mov sp, r7
8004c3c: f85d 7b04 ldr.w r7, [sp], #4
8004c40: 4770 bx lr
08004c42 <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
8004c42: b480 push {r7}
8004c44: b083 sub sp, #12
8004c46: af00 add r7, sp, #0
8004c48: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
8004c4a: bf00 nop
8004c4c: 370c adds r7, #12
8004c4e: 46bd mov sp, r7
8004c50: f85d 7b04 ldr.w r7, [sp], #4
8004c54: 4770 bx lr
08004c56 <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
8004c56: b480 push {r7}
8004c58: b083 sub sp, #12
8004c5a: af00 add r7, sp, #0
8004c5c: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
8004c5e: bf00 nop
8004c60: 370c adds r7, #12
8004c62: 46bd mov sp, r7
8004c64: f85d 7b04 ldr.w r7, [sp], #4
8004c68: 4770 bx lr
08004c6a <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
8004c6a: b480 push {r7}
8004c6c: b083 sub sp, #12
8004c6e: af00 add r7, sp, #0
8004c70: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
8004c72: bf00 nop
8004c74: 370c adds r7, #12
8004c76: 46bd mov sp, r7
8004c78: f85d 7b04 ldr.w r7, [sp], #4
8004c7c: 4770 bx lr
...
08004c80 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
8004c80: b480 push {r7}
8004c82: b085 sub sp, #20
8004c84: af00 add r7, sp, #0
8004c86: 6078 str r0, [r7, #4]
8004c88: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8004c8a: 687b ldr r3, [r7, #4]
8004c8c: 681b ldr r3, [r3, #0]
8004c8e: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8004c90: 687b ldr r3, [r7, #4]
8004c92: 4a46 ldr r2, [pc, #280] @ (8004dac <TIM_Base_SetConfig+0x12c>)
8004c94: 4293 cmp r3, r2
8004c96: d013 beq.n 8004cc0 <TIM_Base_SetConfig+0x40>
8004c98: 687b ldr r3, [r7, #4]
8004c9a: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8004c9e: d00f beq.n 8004cc0 <TIM_Base_SetConfig+0x40>
8004ca0: 687b ldr r3, [r7, #4]
8004ca2: 4a43 ldr r2, [pc, #268] @ (8004db0 <TIM_Base_SetConfig+0x130>)
8004ca4: 4293 cmp r3, r2
8004ca6: d00b beq.n 8004cc0 <TIM_Base_SetConfig+0x40>
8004ca8: 687b ldr r3, [r7, #4]
8004caa: 4a42 ldr r2, [pc, #264] @ (8004db4 <TIM_Base_SetConfig+0x134>)
8004cac: 4293 cmp r3, r2
8004cae: d007 beq.n 8004cc0 <TIM_Base_SetConfig+0x40>
8004cb0: 687b ldr r3, [r7, #4]
8004cb2: 4a41 ldr r2, [pc, #260] @ (8004db8 <TIM_Base_SetConfig+0x138>)
8004cb4: 4293 cmp r3, r2
8004cb6: d003 beq.n 8004cc0 <TIM_Base_SetConfig+0x40>
8004cb8: 687b ldr r3, [r7, #4]
8004cba: 4a40 ldr r2, [pc, #256] @ (8004dbc <TIM_Base_SetConfig+0x13c>)
8004cbc: 4293 cmp r3, r2
8004cbe: d108 bne.n 8004cd2 <TIM_Base_SetConfig+0x52>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8004cc0: 68fb ldr r3, [r7, #12]
8004cc2: f023 0370 bic.w r3, r3, #112 @ 0x70
8004cc6: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8004cc8: 683b ldr r3, [r7, #0]
8004cca: 685b ldr r3, [r3, #4]
8004ccc: 68fa ldr r2, [r7, #12]
8004cce: 4313 orrs r3, r2
8004cd0: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8004cd2: 687b ldr r3, [r7, #4]
8004cd4: 4a35 ldr r2, [pc, #212] @ (8004dac <TIM_Base_SetConfig+0x12c>)
8004cd6: 4293 cmp r3, r2
8004cd8: d02b beq.n 8004d32 <TIM_Base_SetConfig+0xb2>
8004cda: 687b ldr r3, [r7, #4]
8004cdc: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8004ce0: d027 beq.n 8004d32 <TIM_Base_SetConfig+0xb2>
8004ce2: 687b ldr r3, [r7, #4]
8004ce4: 4a32 ldr r2, [pc, #200] @ (8004db0 <TIM_Base_SetConfig+0x130>)
8004ce6: 4293 cmp r3, r2
8004ce8: d023 beq.n 8004d32 <TIM_Base_SetConfig+0xb2>
8004cea: 687b ldr r3, [r7, #4]
8004cec: 4a31 ldr r2, [pc, #196] @ (8004db4 <TIM_Base_SetConfig+0x134>)
8004cee: 4293 cmp r3, r2
8004cf0: d01f beq.n 8004d32 <TIM_Base_SetConfig+0xb2>
8004cf2: 687b ldr r3, [r7, #4]
8004cf4: 4a30 ldr r2, [pc, #192] @ (8004db8 <TIM_Base_SetConfig+0x138>)
8004cf6: 4293 cmp r3, r2
8004cf8: d01b beq.n 8004d32 <TIM_Base_SetConfig+0xb2>
8004cfa: 687b ldr r3, [r7, #4]
8004cfc: 4a2f ldr r2, [pc, #188] @ (8004dbc <TIM_Base_SetConfig+0x13c>)
8004cfe: 4293 cmp r3, r2
8004d00: d017 beq.n 8004d32 <TIM_Base_SetConfig+0xb2>
8004d02: 687b ldr r3, [r7, #4]
8004d04: 4a2e ldr r2, [pc, #184] @ (8004dc0 <TIM_Base_SetConfig+0x140>)
8004d06: 4293 cmp r3, r2
8004d08: d013 beq.n 8004d32 <TIM_Base_SetConfig+0xb2>
8004d0a: 687b ldr r3, [r7, #4]
8004d0c: 4a2d ldr r2, [pc, #180] @ (8004dc4 <TIM_Base_SetConfig+0x144>)
8004d0e: 4293 cmp r3, r2
8004d10: d00f beq.n 8004d32 <TIM_Base_SetConfig+0xb2>
8004d12: 687b ldr r3, [r7, #4]
8004d14: 4a2c ldr r2, [pc, #176] @ (8004dc8 <TIM_Base_SetConfig+0x148>)
8004d16: 4293 cmp r3, r2
8004d18: d00b beq.n 8004d32 <TIM_Base_SetConfig+0xb2>
8004d1a: 687b ldr r3, [r7, #4]
8004d1c: 4a2b ldr r2, [pc, #172] @ (8004dcc <TIM_Base_SetConfig+0x14c>)
8004d1e: 4293 cmp r3, r2
8004d20: d007 beq.n 8004d32 <TIM_Base_SetConfig+0xb2>
8004d22: 687b ldr r3, [r7, #4]
8004d24: 4a2a ldr r2, [pc, #168] @ (8004dd0 <TIM_Base_SetConfig+0x150>)
8004d26: 4293 cmp r3, r2
8004d28: d003 beq.n 8004d32 <TIM_Base_SetConfig+0xb2>
8004d2a: 687b ldr r3, [r7, #4]
8004d2c: 4a29 ldr r2, [pc, #164] @ (8004dd4 <TIM_Base_SetConfig+0x154>)
8004d2e: 4293 cmp r3, r2
8004d30: d108 bne.n 8004d44 <TIM_Base_SetConfig+0xc4>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8004d32: 68fb ldr r3, [r7, #12]
8004d34: f423 7340 bic.w r3, r3, #768 @ 0x300
8004d38: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8004d3a: 683b ldr r3, [r7, #0]
8004d3c: 68db ldr r3, [r3, #12]
8004d3e: 68fa ldr r2, [r7, #12]
8004d40: 4313 orrs r3, r2
8004d42: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8004d44: 68fb ldr r3, [r7, #12]
8004d46: f023 0280 bic.w r2, r3, #128 @ 0x80
8004d4a: 683b ldr r3, [r7, #0]
8004d4c: 695b ldr r3, [r3, #20]
8004d4e: 4313 orrs r3, r2
8004d50: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
8004d52: 687b ldr r3, [r7, #4]
8004d54: 68fa ldr r2, [r7, #12]
8004d56: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8004d58: 683b ldr r3, [r7, #0]
8004d5a: 689a ldr r2, [r3, #8]
8004d5c: 687b ldr r3, [r7, #4]
8004d5e: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8004d60: 683b ldr r3, [r7, #0]
8004d62: 681a ldr r2, [r3, #0]
8004d64: 687b ldr r3, [r7, #4]
8004d66: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8004d68: 687b ldr r3, [r7, #4]
8004d6a: 4a10 ldr r2, [pc, #64] @ (8004dac <TIM_Base_SetConfig+0x12c>)
8004d6c: 4293 cmp r3, r2
8004d6e: d003 beq.n 8004d78 <TIM_Base_SetConfig+0xf8>
8004d70: 687b ldr r3, [r7, #4]
8004d72: 4a12 ldr r2, [pc, #72] @ (8004dbc <TIM_Base_SetConfig+0x13c>)
8004d74: 4293 cmp r3, r2
8004d76: d103 bne.n 8004d80 <TIM_Base_SetConfig+0x100>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8004d78: 683b ldr r3, [r7, #0]
8004d7a: 691a ldr r2, [r3, #16]
8004d7c: 687b ldr r3, [r7, #4]
8004d7e: 631a str r2, [r3, #48] @ 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8004d80: 687b ldr r3, [r7, #4]
8004d82: 2201 movs r2, #1
8004d84: 615a str r2, [r3, #20]
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
8004d86: 687b ldr r3, [r7, #4]
8004d88: 691b ldr r3, [r3, #16]
8004d8a: f003 0301 and.w r3, r3, #1
8004d8e: 2b01 cmp r3, #1
8004d90: d105 bne.n 8004d9e <TIM_Base_SetConfig+0x11e>
{
/* Clear the update flag */
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
8004d92: 687b ldr r3, [r7, #4]
8004d94: 691b ldr r3, [r3, #16]
8004d96: f023 0201 bic.w r2, r3, #1
8004d9a: 687b ldr r3, [r7, #4]
8004d9c: 611a str r2, [r3, #16]
}
}
8004d9e: bf00 nop
8004da0: 3714 adds r7, #20
8004da2: 46bd mov sp, r7
8004da4: f85d 7b04 ldr.w r7, [sp], #4
8004da8: 4770 bx lr
8004daa: bf00 nop
8004dac: 40010000 .word 0x40010000
8004db0: 40000400 .word 0x40000400
8004db4: 40000800 .word 0x40000800
8004db8: 40000c00 .word 0x40000c00
8004dbc: 40010400 .word 0x40010400
8004dc0: 40014000 .word 0x40014000
8004dc4: 40014400 .word 0x40014400
8004dc8: 40014800 .word 0x40014800
8004dcc: 40001800 .word 0x40001800
8004dd0: 40001c00 .word 0x40001c00
8004dd4: 40002000 .word 0x40002000
08004dd8 <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8004dd8: b480 push {r7}
8004dda: b087 sub sp, #28
8004ddc: af00 add r7, sp, #0
8004dde: 6078 str r0, [r7, #4]
8004de0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8004de2: 687b ldr r3, [r7, #4]
8004de4: 6a1b ldr r3, [r3, #32]
8004de6: 617b str r3, [r7, #20]
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
8004de8: 687b ldr r3, [r7, #4]
8004dea: 6a1b ldr r3, [r3, #32]
8004dec: f023 0201 bic.w r2, r3, #1
8004df0: 687b ldr r3, [r7, #4]
8004df2: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8004df4: 687b ldr r3, [r7, #4]
8004df6: 685b ldr r3, [r3, #4]
8004df8: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8004dfa: 687b ldr r3, [r7, #4]
8004dfc: 699b ldr r3, [r3, #24]
8004dfe: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
8004e00: 68fb ldr r3, [r7, #12]
8004e02: f023 0370 bic.w r3, r3, #112 @ 0x70
8004e06: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
8004e08: 68fb ldr r3, [r7, #12]
8004e0a: f023 0303 bic.w r3, r3, #3
8004e0e: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8004e10: 683b ldr r3, [r7, #0]
8004e12: 681b ldr r3, [r3, #0]
8004e14: 68fa ldr r2, [r7, #12]
8004e16: 4313 orrs r3, r2
8004e18: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
8004e1a: 697b ldr r3, [r7, #20]
8004e1c: f023 0302 bic.w r3, r3, #2
8004e20: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
8004e22: 683b ldr r3, [r7, #0]
8004e24: 689b ldr r3, [r3, #8]
8004e26: 697a ldr r2, [r7, #20]
8004e28: 4313 orrs r3, r2
8004e2a: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8004e2c: 687b ldr r3, [r7, #4]
8004e2e: 4a20 ldr r2, [pc, #128] @ (8004eb0 <TIM_OC1_SetConfig+0xd8>)
8004e30: 4293 cmp r3, r2
8004e32: d003 beq.n 8004e3c <TIM_OC1_SetConfig+0x64>
8004e34: 687b ldr r3, [r7, #4]
8004e36: 4a1f ldr r2, [pc, #124] @ (8004eb4 <TIM_OC1_SetConfig+0xdc>)
8004e38: 4293 cmp r3, r2
8004e3a: d10c bne.n 8004e56 <TIM_OC1_SetConfig+0x7e>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8004e3c: 697b ldr r3, [r7, #20]
8004e3e: f023 0308 bic.w r3, r3, #8
8004e42: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8004e44: 683b ldr r3, [r7, #0]
8004e46: 68db ldr r3, [r3, #12]
8004e48: 697a ldr r2, [r7, #20]
8004e4a: 4313 orrs r3, r2
8004e4c: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
8004e4e: 697b ldr r3, [r7, #20]
8004e50: f023 0304 bic.w r3, r3, #4
8004e54: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8004e56: 687b ldr r3, [r7, #4]
8004e58: 4a15 ldr r2, [pc, #84] @ (8004eb0 <TIM_OC1_SetConfig+0xd8>)
8004e5a: 4293 cmp r3, r2
8004e5c: d003 beq.n 8004e66 <TIM_OC1_SetConfig+0x8e>
8004e5e: 687b ldr r3, [r7, #4]
8004e60: 4a14 ldr r2, [pc, #80] @ (8004eb4 <TIM_OC1_SetConfig+0xdc>)
8004e62: 4293 cmp r3, r2
8004e64: d111 bne.n 8004e8a <TIM_OC1_SetConfig+0xb2>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
8004e66: 693b ldr r3, [r7, #16]
8004e68: f423 7380 bic.w r3, r3, #256 @ 0x100
8004e6c: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
8004e6e: 693b ldr r3, [r7, #16]
8004e70: f423 7300 bic.w r3, r3, #512 @ 0x200
8004e74: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
8004e76: 683b ldr r3, [r7, #0]
8004e78: 695b ldr r3, [r3, #20]
8004e7a: 693a ldr r2, [r7, #16]
8004e7c: 4313 orrs r3, r2
8004e7e: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
8004e80: 683b ldr r3, [r7, #0]
8004e82: 699b ldr r3, [r3, #24]
8004e84: 693a ldr r2, [r7, #16]
8004e86: 4313 orrs r3, r2
8004e88: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8004e8a: 687b ldr r3, [r7, #4]
8004e8c: 693a ldr r2, [r7, #16]
8004e8e: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8004e90: 687b ldr r3, [r7, #4]
8004e92: 68fa ldr r2, [r7, #12]
8004e94: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
8004e96: 683b ldr r3, [r7, #0]
8004e98: 685a ldr r2, [r3, #4]
8004e9a: 687b ldr r3, [r7, #4]
8004e9c: 635a str r2, [r3, #52] @ 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8004e9e: 687b ldr r3, [r7, #4]
8004ea0: 697a ldr r2, [r7, #20]
8004ea2: 621a str r2, [r3, #32]
}
8004ea4: bf00 nop
8004ea6: 371c adds r7, #28
8004ea8: 46bd mov sp, r7
8004eaa: f85d 7b04 ldr.w r7, [sp], #4
8004eae: 4770 bx lr
8004eb0: 40010000 .word 0x40010000
8004eb4: 40010400 .word 0x40010400
08004eb8 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8004eb8: b480 push {r7}
8004eba: b087 sub sp, #28
8004ebc: af00 add r7, sp, #0
8004ebe: 6078 str r0, [r7, #4]
8004ec0: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8004ec2: 687b ldr r3, [r7, #4]
8004ec4: 6a1b ldr r3, [r3, #32]
8004ec6: 617b str r3, [r7, #20]
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8004ec8: 687b ldr r3, [r7, #4]
8004eca: 6a1b ldr r3, [r3, #32]
8004ecc: f023 0210 bic.w r2, r3, #16
8004ed0: 687b ldr r3, [r7, #4]
8004ed2: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8004ed4: 687b ldr r3, [r7, #4]
8004ed6: 685b ldr r3, [r3, #4]
8004ed8: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8004eda: 687b ldr r3, [r7, #4]
8004edc: 699b ldr r3, [r3, #24]
8004ede: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8004ee0: 68fb ldr r3, [r7, #12]
8004ee2: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8004ee6: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8004ee8: 68fb ldr r3, [r7, #12]
8004eea: f423 7340 bic.w r3, r3, #768 @ 0x300
8004eee: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8004ef0: 683b ldr r3, [r7, #0]
8004ef2: 681b ldr r3, [r3, #0]
8004ef4: 021b lsls r3, r3, #8
8004ef6: 68fa ldr r2, [r7, #12]
8004ef8: 4313 orrs r3, r2
8004efa: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8004efc: 697b ldr r3, [r7, #20]
8004efe: f023 0320 bic.w r3, r3, #32
8004f02: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8004f04: 683b ldr r3, [r7, #0]
8004f06: 689b ldr r3, [r3, #8]
8004f08: 011b lsls r3, r3, #4
8004f0a: 697a ldr r2, [r7, #20]
8004f0c: 4313 orrs r3, r2
8004f0e: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
8004f10: 687b ldr r3, [r7, #4]
8004f12: 4a22 ldr r2, [pc, #136] @ (8004f9c <TIM_OC2_SetConfig+0xe4>)
8004f14: 4293 cmp r3, r2
8004f16: d003 beq.n 8004f20 <TIM_OC2_SetConfig+0x68>
8004f18: 687b ldr r3, [r7, #4]
8004f1a: 4a21 ldr r2, [pc, #132] @ (8004fa0 <TIM_OC2_SetConfig+0xe8>)
8004f1c: 4293 cmp r3, r2
8004f1e: d10d bne.n 8004f3c <TIM_OC2_SetConfig+0x84>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
8004f20: 697b ldr r3, [r7, #20]
8004f22: f023 0380 bic.w r3, r3, #128 @ 0x80
8004f26: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
8004f28: 683b ldr r3, [r7, #0]
8004f2a: 68db ldr r3, [r3, #12]
8004f2c: 011b lsls r3, r3, #4
8004f2e: 697a ldr r2, [r7, #20]
8004f30: 4313 orrs r3, r2
8004f32: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8004f34: 697b ldr r3, [r7, #20]
8004f36: f023 0340 bic.w r3, r3, #64 @ 0x40
8004f3a: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8004f3c: 687b ldr r3, [r7, #4]
8004f3e: 4a17 ldr r2, [pc, #92] @ (8004f9c <TIM_OC2_SetConfig+0xe4>)
8004f40: 4293 cmp r3, r2
8004f42: d003 beq.n 8004f4c <TIM_OC2_SetConfig+0x94>
8004f44: 687b ldr r3, [r7, #4]
8004f46: 4a16 ldr r2, [pc, #88] @ (8004fa0 <TIM_OC2_SetConfig+0xe8>)
8004f48: 4293 cmp r3, r2
8004f4a: d113 bne.n 8004f74 <TIM_OC2_SetConfig+0xbc>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
8004f4c: 693b ldr r3, [r7, #16]
8004f4e: f423 6380 bic.w r3, r3, #1024 @ 0x400
8004f52: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
8004f54: 693b ldr r3, [r7, #16]
8004f56: f423 6300 bic.w r3, r3, #2048 @ 0x800
8004f5a: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
8004f5c: 683b ldr r3, [r7, #0]
8004f5e: 695b ldr r3, [r3, #20]
8004f60: 009b lsls r3, r3, #2
8004f62: 693a ldr r2, [r7, #16]
8004f64: 4313 orrs r3, r2
8004f66: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8004f68: 683b ldr r3, [r7, #0]
8004f6a: 699b ldr r3, [r3, #24]
8004f6c: 009b lsls r3, r3, #2
8004f6e: 693a ldr r2, [r7, #16]
8004f70: 4313 orrs r3, r2
8004f72: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8004f74: 687b ldr r3, [r7, #4]
8004f76: 693a ldr r2, [r7, #16]
8004f78: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
8004f7a: 687b ldr r3, [r7, #4]
8004f7c: 68fa ldr r2, [r7, #12]
8004f7e: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
8004f80: 683b ldr r3, [r7, #0]
8004f82: 685a ldr r2, [r3, #4]
8004f84: 687b ldr r3, [r7, #4]
8004f86: 639a str r2, [r3, #56] @ 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8004f88: 687b ldr r3, [r7, #4]
8004f8a: 697a ldr r2, [r7, #20]
8004f8c: 621a str r2, [r3, #32]
}
8004f8e: bf00 nop
8004f90: 371c adds r7, #28
8004f92: 46bd mov sp, r7
8004f94: f85d 7b04 ldr.w r7, [sp], #4
8004f98: 4770 bx lr
8004f9a: bf00 nop
8004f9c: 40010000 .word 0x40010000
8004fa0: 40010400 .word 0x40010400
08004fa4 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8004fa4: b480 push {r7}
8004fa6: b087 sub sp, #28
8004fa8: af00 add r7, sp, #0
8004faa: 6078 str r0, [r7, #4]
8004fac: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8004fae: 687b ldr r3, [r7, #4]
8004fb0: 6a1b ldr r3, [r3, #32]
8004fb2: 617b str r3, [r7, #20]
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8004fb4: 687b ldr r3, [r7, #4]
8004fb6: 6a1b ldr r3, [r3, #32]
8004fb8: f423 7280 bic.w r2, r3, #256 @ 0x100
8004fbc: 687b ldr r3, [r7, #4]
8004fbe: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8004fc0: 687b ldr r3, [r7, #4]
8004fc2: 685b ldr r3, [r3, #4]
8004fc4: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
8004fc6: 687b ldr r3, [r7, #4]
8004fc8: 69db ldr r3, [r3, #28]
8004fca: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
8004fcc: 68fb ldr r3, [r7, #12]
8004fce: f023 0370 bic.w r3, r3, #112 @ 0x70
8004fd2: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
8004fd4: 68fb ldr r3, [r7, #12]
8004fd6: f023 0303 bic.w r3, r3, #3
8004fda: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8004fdc: 683b ldr r3, [r7, #0]
8004fde: 681b ldr r3, [r3, #0]
8004fe0: 68fa ldr r2, [r7, #12]
8004fe2: 4313 orrs r3, r2
8004fe4: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
8004fe6: 697b ldr r3, [r7, #20]
8004fe8: f423 7300 bic.w r3, r3, #512 @ 0x200
8004fec: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8004fee: 683b ldr r3, [r7, #0]
8004ff0: 689b ldr r3, [r3, #8]
8004ff2: 021b lsls r3, r3, #8
8004ff4: 697a ldr r2, [r7, #20]
8004ff6: 4313 orrs r3, r2
8004ff8: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
8004ffa: 687b ldr r3, [r7, #4]
8004ffc: 4a21 ldr r2, [pc, #132] @ (8005084 <TIM_OC3_SetConfig+0xe0>)
8004ffe: 4293 cmp r3, r2
8005000: d003 beq.n 800500a <TIM_OC3_SetConfig+0x66>
8005002: 687b ldr r3, [r7, #4]
8005004: 4a20 ldr r2, [pc, #128] @ (8005088 <TIM_OC3_SetConfig+0xe4>)
8005006: 4293 cmp r3, r2
8005008: d10d bne.n 8005026 <TIM_OC3_SetConfig+0x82>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
800500a: 697b ldr r3, [r7, #20]
800500c: f423 6300 bic.w r3, r3, #2048 @ 0x800
8005010: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
8005012: 683b ldr r3, [r7, #0]
8005014: 68db ldr r3, [r3, #12]
8005016: 021b lsls r3, r3, #8
8005018: 697a ldr r2, [r7, #20]
800501a: 4313 orrs r3, r2
800501c: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
800501e: 697b ldr r3, [r7, #20]
8005020: f423 6380 bic.w r3, r3, #1024 @ 0x400
8005024: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8005026: 687b ldr r3, [r7, #4]
8005028: 4a16 ldr r2, [pc, #88] @ (8005084 <TIM_OC3_SetConfig+0xe0>)
800502a: 4293 cmp r3, r2
800502c: d003 beq.n 8005036 <TIM_OC3_SetConfig+0x92>
800502e: 687b ldr r3, [r7, #4]
8005030: 4a15 ldr r2, [pc, #84] @ (8005088 <TIM_OC3_SetConfig+0xe4>)
8005032: 4293 cmp r3, r2
8005034: d113 bne.n 800505e <TIM_OC3_SetConfig+0xba>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
8005036: 693b ldr r3, [r7, #16]
8005038: f423 5380 bic.w r3, r3, #4096 @ 0x1000
800503c: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
800503e: 693b ldr r3, [r7, #16]
8005040: f423 5300 bic.w r3, r3, #8192 @ 0x2000
8005044: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
8005046: 683b ldr r3, [r7, #0]
8005048: 695b ldr r3, [r3, #20]
800504a: 011b lsls r3, r3, #4
800504c: 693a ldr r2, [r7, #16]
800504e: 4313 orrs r3, r2
8005050: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
8005052: 683b ldr r3, [r7, #0]
8005054: 699b ldr r3, [r3, #24]
8005056: 011b lsls r3, r3, #4
8005058: 693a ldr r2, [r7, #16]
800505a: 4313 orrs r3, r2
800505c: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800505e: 687b ldr r3, [r7, #4]
8005060: 693a ldr r2, [r7, #16]
8005062: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8005064: 687b ldr r3, [r7, #4]
8005066: 68fa ldr r2, [r7, #12]
8005068: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
800506a: 683b ldr r3, [r7, #0]
800506c: 685a ldr r2, [r3, #4]
800506e: 687b ldr r3, [r7, #4]
8005070: 63da str r2, [r3, #60] @ 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8005072: 687b ldr r3, [r7, #4]
8005074: 697a ldr r2, [r7, #20]
8005076: 621a str r2, [r3, #32]
}
8005078: bf00 nop
800507a: 371c adds r7, #28
800507c: 46bd mov sp, r7
800507e: f85d 7b04 ldr.w r7, [sp], #4
8005082: 4770 bx lr
8005084: 40010000 .word 0x40010000
8005088: 40010400 .word 0x40010400
0800508c <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
800508c: b480 push {r7}
800508e: b087 sub sp, #28
8005090: af00 add r7, sp, #0
8005092: 6078 str r0, [r7, #4]
8005094: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8005096: 687b ldr r3, [r7, #4]
8005098: 6a1b ldr r3, [r3, #32]
800509a: 613b str r3, [r7, #16]
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
800509c: 687b ldr r3, [r7, #4]
800509e: 6a1b ldr r3, [r3, #32]
80050a0: f423 5280 bic.w r2, r3, #4096 @ 0x1000
80050a4: 687b ldr r3, [r7, #4]
80050a6: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80050a8: 687b ldr r3, [r7, #4]
80050aa: 685b ldr r3, [r3, #4]
80050ac: 617b str r3, [r7, #20]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
80050ae: 687b ldr r3, [r7, #4]
80050b0: 69db ldr r3, [r3, #28]
80050b2: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
80050b4: 68fb ldr r3, [r7, #12]
80050b6: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
80050ba: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
80050bc: 68fb ldr r3, [r7, #12]
80050be: f423 7340 bic.w r3, r3, #768 @ 0x300
80050c2: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
80050c4: 683b ldr r3, [r7, #0]
80050c6: 681b ldr r3, [r3, #0]
80050c8: 021b lsls r3, r3, #8
80050ca: 68fa ldr r2, [r7, #12]
80050cc: 4313 orrs r3, r2
80050ce: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
80050d0: 693b ldr r3, [r7, #16]
80050d2: f423 5300 bic.w r3, r3, #8192 @ 0x2000
80050d6: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
80050d8: 683b ldr r3, [r7, #0]
80050da: 689b ldr r3, [r3, #8]
80050dc: 031b lsls r3, r3, #12
80050de: 693a ldr r2, [r7, #16]
80050e0: 4313 orrs r3, r2
80050e2: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
80050e4: 687b ldr r3, [r7, #4]
80050e6: 4a12 ldr r2, [pc, #72] @ (8005130 <TIM_OC4_SetConfig+0xa4>)
80050e8: 4293 cmp r3, r2
80050ea: d003 beq.n 80050f4 <TIM_OC4_SetConfig+0x68>
80050ec: 687b ldr r3, [r7, #4]
80050ee: 4a11 ldr r2, [pc, #68] @ (8005134 <TIM_OC4_SetConfig+0xa8>)
80050f0: 4293 cmp r3, r2
80050f2: d109 bne.n 8005108 <TIM_OC4_SetConfig+0x7c>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
80050f4: 697b ldr r3, [r7, #20]
80050f6: f423 4380 bic.w r3, r3, #16384 @ 0x4000
80050fa: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
80050fc: 683b ldr r3, [r7, #0]
80050fe: 695b ldr r3, [r3, #20]
8005100: 019b lsls r3, r3, #6
8005102: 697a ldr r2, [r7, #20]
8005104: 4313 orrs r3, r2
8005106: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8005108: 687b ldr r3, [r7, #4]
800510a: 697a ldr r2, [r7, #20]
800510c: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
800510e: 687b ldr r3, [r7, #4]
8005110: 68fa ldr r2, [r7, #12]
8005112: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
8005114: 683b ldr r3, [r7, #0]
8005116: 685a ldr r2, [r3, #4]
8005118: 687b ldr r3, [r7, #4]
800511a: 641a str r2, [r3, #64] @ 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800511c: 687b ldr r3, [r7, #4]
800511e: 693a ldr r2, [r7, #16]
8005120: 621a str r2, [r3, #32]
}
8005122: bf00 nop
8005124: 371c adds r7, #28
8005126: 46bd mov sp, r7
8005128: f85d 7b04 ldr.w r7, [sp], #4
800512c: 4770 bx lr
800512e: bf00 nop
8005130: 40010000 .word 0x40010000
8005134: 40010400 .word 0x40010400
08005138 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8005138: b480 push {r7}
800513a: b087 sub sp, #28
800513c: af00 add r7, sp, #0
800513e: 60f8 str r0, [r7, #12]
8005140: 60b9 str r1, [r7, #8]
8005142: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
8005144: 68fb ldr r3, [r7, #12]
8005146: 6a1b ldr r3, [r3, #32]
8005148: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
800514a: 68fb ldr r3, [r7, #12]
800514c: 6a1b ldr r3, [r3, #32]
800514e: f023 0201 bic.w r2, r3, #1
8005152: 68fb ldr r3, [r7, #12]
8005154: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
8005156: 68fb ldr r3, [r7, #12]
8005158: 699b ldr r3, [r3, #24]
800515a: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
800515c: 693b ldr r3, [r7, #16]
800515e: f023 03f0 bic.w r3, r3, #240 @ 0xf0
8005162: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
8005164: 687b ldr r3, [r7, #4]
8005166: 011b lsls r3, r3, #4
8005168: 693a ldr r2, [r7, #16]
800516a: 4313 orrs r3, r2
800516c: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
800516e: 697b ldr r3, [r7, #20]
8005170: f023 030a bic.w r3, r3, #10
8005174: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
8005176: 697a ldr r2, [r7, #20]
8005178: 68bb ldr r3, [r7, #8]
800517a: 4313 orrs r3, r2
800517c: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
800517e: 68fb ldr r3, [r7, #12]
8005180: 693a ldr r2, [r7, #16]
8005182: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
8005184: 68fb ldr r3, [r7, #12]
8005186: 697a ldr r2, [r7, #20]
8005188: 621a str r2, [r3, #32]
}
800518a: bf00 nop
800518c: 371c adds r7, #28
800518e: 46bd mov sp, r7
8005190: f85d 7b04 ldr.w r7, [sp], #4
8005194: 4770 bx lr
08005196 <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8005196: b480 push {r7}
8005198: b087 sub sp, #28
800519a: af00 add r7, sp, #0
800519c: 60f8 str r0, [r7, #12]
800519e: 60b9 str r1, [r7, #8]
80051a0: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
80051a2: 68fb ldr r3, [r7, #12]
80051a4: 6a1b ldr r3, [r3, #32]
80051a6: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC2E;
80051a8: 68fb ldr r3, [r7, #12]
80051aa: 6a1b ldr r3, [r3, #32]
80051ac: f023 0210 bic.w r2, r3, #16
80051b0: 68fb ldr r3, [r7, #12]
80051b2: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
80051b4: 68fb ldr r3, [r7, #12]
80051b6: 699b ldr r3, [r3, #24]
80051b8: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
80051ba: 693b ldr r3, [r7, #16]
80051bc: f423 4370 bic.w r3, r3, #61440 @ 0xf000
80051c0: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 12U);
80051c2: 687b ldr r3, [r7, #4]
80051c4: 031b lsls r3, r3, #12
80051c6: 693a ldr r2, [r7, #16]
80051c8: 4313 orrs r3, r2
80051ca: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
80051cc: 697b ldr r3, [r7, #20]
80051ce: f023 03a0 bic.w r3, r3, #160 @ 0xa0
80051d2: 617b str r3, [r7, #20]
tmpccer |= (TIM_ICPolarity << 4U);
80051d4: 68bb ldr r3, [r7, #8]
80051d6: 011b lsls r3, r3, #4
80051d8: 697a ldr r2, [r7, #20]
80051da: 4313 orrs r3, r2
80051dc: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
80051de: 68fb ldr r3, [r7, #12]
80051e0: 693a ldr r2, [r7, #16]
80051e2: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
80051e4: 68fb ldr r3, [r7, #12]
80051e6: 697a ldr r2, [r7, #20]
80051e8: 621a str r2, [r3, #32]
}
80051ea: bf00 nop
80051ec: 371c adds r7, #28
80051ee: 46bd mov sp, r7
80051f0: f85d 7b04 ldr.w r7, [sp], #4
80051f4: 4770 bx lr
080051f6 <TIM_ITRx_SetConfig>:
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
* @arg TIM_TS_ETRF: External Trigger input
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
80051f6: b480 push {r7}
80051f8: b085 sub sp, #20
80051fa: af00 add r7, sp, #0
80051fc: 6078 str r0, [r7, #4]
80051fe: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
8005200: 687b ldr r3, [r7, #4]
8005202: 689b ldr r3, [r3, #8]
8005204: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
8005206: 68fb ldr r3, [r7, #12]
8005208: f023 0370 bic.w r3, r3, #112 @ 0x70
800520c: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
800520e: 683a ldr r2, [r7, #0]
8005210: 68fb ldr r3, [r7, #12]
8005212: 4313 orrs r3, r2
8005214: f043 0307 orr.w r3, r3, #7
8005218: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
800521a: 687b ldr r3, [r7, #4]
800521c: 68fa ldr r2, [r7, #12]
800521e: 609a str r2, [r3, #8]
}
8005220: bf00 nop
8005222: 3714 adds r7, #20
8005224: 46bd mov sp, r7
8005226: f85d 7b04 ldr.w r7, [sp], #4
800522a: 4770 bx lr
0800522c <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
800522c: b480 push {r7}
800522e: b087 sub sp, #28
8005230: af00 add r7, sp, #0
8005232: 60f8 str r0, [r7, #12]
8005234: 60b9 str r1, [r7, #8]
8005236: 607a str r2, [r7, #4]
8005238: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
800523a: 68fb ldr r3, [r7, #12]
800523c: 689b ldr r3, [r3, #8]
800523e: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8005240: 697b ldr r3, [r7, #20]
8005242: f423 437f bic.w r3, r3, #65280 @ 0xff00
8005246: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8005248: 683b ldr r3, [r7, #0]
800524a: 021a lsls r2, r3, #8
800524c: 687b ldr r3, [r7, #4]
800524e: 431a orrs r2, r3
8005250: 68bb ldr r3, [r7, #8]
8005252: 4313 orrs r3, r2
8005254: 697a ldr r2, [r7, #20]
8005256: 4313 orrs r3, r2
8005258: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
800525a: 68fb ldr r3, [r7, #12]
800525c: 697a ldr r2, [r7, #20]
800525e: 609a str r2, [r3, #8]
}
8005260: bf00 nop
8005262: 371c adds r7, #28
8005264: 46bd mov sp, r7
8005266: f85d 7b04 ldr.w r7, [sp], #4
800526a: 4770 bx lr
0800526c <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
800526c: b480 push {r7}
800526e: b085 sub sp, #20
8005270: af00 add r7, sp, #0
8005272: 6078 str r0, [r7, #4]
8005274: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8005276: 687b ldr r3, [r7, #4]
8005278: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
800527c: 2b01 cmp r3, #1
800527e: d101 bne.n 8005284 <HAL_TIMEx_MasterConfigSynchronization+0x18>
8005280: 2302 movs r3, #2
8005282: e05a b.n 800533a <HAL_TIMEx_MasterConfigSynchronization+0xce>
8005284: 687b ldr r3, [r7, #4]
8005286: 2201 movs r2, #1
8005288: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
800528c: 687b ldr r3, [r7, #4]
800528e: 2202 movs r2, #2
8005290: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8005294: 687b ldr r3, [r7, #4]
8005296: 681b ldr r3, [r3, #0]
8005298: 685b ldr r3, [r3, #4]
800529a: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
800529c: 687b ldr r3, [r7, #4]
800529e: 681b ldr r3, [r3, #0]
80052a0: 689b ldr r3, [r3, #8]
80052a2: 60bb str r3, [r7, #8]
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
80052a4: 68fb ldr r3, [r7, #12]
80052a6: f023 0370 bic.w r3, r3, #112 @ 0x70
80052aa: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
80052ac: 683b ldr r3, [r7, #0]
80052ae: 681b ldr r3, [r3, #0]
80052b0: 68fa ldr r2, [r7, #12]
80052b2: 4313 orrs r3, r2
80052b4: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
80052b6: 687b ldr r3, [r7, #4]
80052b8: 681b ldr r3, [r3, #0]
80052ba: 68fa ldr r2, [r7, #12]
80052bc: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80052be: 687b ldr r3, [r7, #4]
80052c0: 681b ldr r3, [r3, #0]
80052c2: 4a21 ldr r2, [pc, #132] @ (8005348 <HAL_TIMEx_MasterConfigSynchronization+0xdc>)
80052c4: 4293 cmp r3, r2
80052c6: d022 beq.n 800530e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
80052c8: 687b ldr r3, [r7, #4]
80052ca: 681b ldr r3, [r3, #0]
80052cc: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80052d0: d01d beq.n 800530e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
80052d2: 687b ldr r3, [r7, #4]
80052d4: 681b ldr r3, [r3, #0]
80052d6: 4a1d ldr r2, [pc, #116] @ (800534c <HAL_TIMEx_MasterConfigSynchronization+0xe0>)
80052d8: 4293 cmp r3, r2
80052da: d018 beq.n 800530e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
80052dc: 687b ldr r3, [r7, #4]
80052de: 681b ldr r3, [r3, #0]
80052e0: 4a1b ldr r2, [pc, #108] @ (8005350 <HAL_TIMEx_MasterConfigSynchronization+0xe4>)
80052e2: 4293 cmp r3, r2
80052e4: d013 beq.n 800530e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
80052e6: 687b ldr r3, [r7, #4]
80052e8: 681b ldr r3, [r3, #0]
80052ea: 4a1a ldr r2, [pc, #104] @ (8005354 <HAL_TIMEx_MasterConfigSynchronization+0xe8>)
80052ec: 4293 cmp r3, r2
80052ee: d00e beq.n 800530e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
80052f0: 687b ldr r3, [r7, #4]
80052f2: 681b ldr r3, [r3, #0]
80052f4: 4a18 ldr r2, [pc, #96] @ (8005358 <HAL_TIMEx_MasterConfigSynchronization+0xec>)
80052f6: 4293 cmp r3, r2
80052f8: d009 beq.n 800530e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
80052fa: 687b ldr r3, [r7, #4]
80052fc: 681b ldr r3, [r3, #0]
80052fe: 4a17 ldr r2, [pc, #92] @ (800535c <HAL_TIMEx_MasterConfigSynchronization+0xf0>)
8005300: 4293 cmp r3, r2
8005302: d004 beq.n 800530e <HAL_TIMEx_MasterConfigSynchronization+0xa2>
8005304: 687b ldr r3, [r7, #4]
8005306: 681b ldr r3, [r3, #0]
8005308: 4a15 ldr r2, [pc, #84] @ (8005360 <HAL_TIMEx_MasterConfigSynchronization+0xf4>)
800530a: 4293 cmp r3, r2
800530c: d10c bne.n 8005328 <HAL_TIMEx_MasterConfigSynchronization+0xbc>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
800530e: 68bb ldr r3, [r7, #8]
8005310: f023 0380 bic.w r3, r3, #128 @ 0x80
8005314: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8005316: 683b ldr r3, [r7, #0]
8005318: 685b ldr r3, [r3, #4]
800531a: 68ba ldr r2, [r7, #8]
800531c: 4313 orrs r3, r2
800531e: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8005320: 687b ldr r3, [r7, #4]
8005322: 681b ldr r3, [r3, #0]
8005324: 68ba ldr r2, [r7, #8]
8005326: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8005328: 687b ldr r3, [r7, #4]
800532a: 2201 movs r2, #1
800532c: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
8005330: 687b ldr r3, [r7, #4]
8005332: 2200 movs r2, #0
8005334: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
8005338: 2300 movs r3, #0
}
800533a: 4618 mov r0, r3
800533c: 3714 adds r7, #20
800533e: 46bd mov sp, r7
8005340: f85d 7b04 ldr.w r7, [sp], #4
8005344: 4770 bx lr
8005346: bf00 nop
8005348: 40010000 .word 0x40010000
800534c: 40000400 .word 0x40000400
8005350: 40000800 .word 0x40000800
8005354: 40000c00 .word 0x40000c00
8005358: 40010400 .word 0x40010400
800535c: 40014000 .word 0x40014000
8005360: 40001800 .word 0x40001800
08005364 <HAL_TIMEx_ConfigBreakDeadTime>:
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
8005364: b480 push {r7}
8005366: b085 sub sp, #20
8005368: af00 add r7, sp, #0
800536a: 6078 str r0, [r7, #4]
800536c: 6039 str r1, [r7, #0]
/* Keep this variable initialized to 0 as it is used to configure BDTR register */
uint32_t tmpbdtr = 0U;
800536e: 2300 movs r3, #0
8005370: 60fb str r3, [r7, #12]
assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
/* Check input state */
__HAL_LOCK(htim);
8005372: 687b ldr r3, [r7, #4]
8005374: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8005378: 2b01 cmp r3, #1
800537a: d101 bne.n 8005380 <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
800537c: 2302 movs r3, #2
800537e: e03d b.n 80053fc <HAL_TIMEx_ConfigBreakDeadTime+0x98>
8005380: 687b ldr r3, [r7, #4]
8005382: 2201 movs r2, #1
8005384: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
8005388: 68fb ldr r3, [r7, #12]
800538a: f023 02ff bic.w r2, r3, #255 @ 0xff
800538e: 683b ldr r3, [r7, #0]
8005390: 68db ldr r3, [r3, #12]
8005392: 4313 orrs r3, r2
8005394: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
8005396: 68fb ldr r3, [r7, #12]
8005398: f423 7240 bic.w r2, r3, #768 @ 0x300
800539c: 683b ldr r3, [r7, #0]
800539e: 689b ldr r3, [r3, #8]
80053a0: 4313 orrs r3, r2
80053a2: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
80053a4: 68fb ldr r3, [r7, #12]
80053a6: f423 6280 bic.w r2, r3, #1024 @ 0x400
80053aa: 683b ldr r3, [r7, #0]
80053ac: 685b ldr r3, [r3, #4]
80053ae: 4313 orrs r3, r2
80053b0: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
80053b2: 68fb ldr r3, [r7, #12]
80053b4: f423 6200 bic.w r2, r3, #2048 @ 0x800
80053b8: 683b ldr r3, [r7, #0]
80053ba: 681b ldr r3, [r3, #0]
80053bc: 4313 orrs r3, r2
80053be: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
80053c0: 68fb ldr r3, [r7, #12]
80053c2: f423 5280 bic.w r2, r3, #4096 @ 0x1000
80053c6: 683b ldr r3, [r7, #0]
80053c8: 691b ldr r3, [r3, #16]
80053ca: 4313 orrs r3, r2
80053cc: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
80053ce: 68fb ldr r3, [r7, #12]
80053d0: f423 5200 bic.w r2, r3, #8192 @ 0x2000
80053d4: 683b ldr r3, [r7, #0]
80053d6: 695b ldr r3, [r3, #20]
80053d8: 4313 orrs r3, r2
80053da: 60fb str r3, [r7, #12]
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
80053dc: 68fb ldr r3, [r7, #12]
80053de: f423 4280 bic.w r2, r3, #16384 @ 0x4000
80053e2: 683b ldr r3, [r7, #0]
80053e4: 69db ldr r3, [r3, #28]
80053e6: 4313 orrs r3, r2
80053e8: 60fb str r3, [r7, #12]
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
80053ea: 687b ldr r3, [r7, #4]
80053ec: 681b ldr r3, [r3, #0]
80053ee: 68fa ldr r2, [r7, #12]
80053f0: 645a str r2, [r3, #68] @ 0x44
__HAL_UNLOCK(htim);
80053f2: 687b ldr r3, [r7, #4]
80053f4: 2200 movs r2, #0
80053f6: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
80053fa: 2300 movs r3, #0
}
80053fc: 4618 mov r0, r3
80053fe: 3714 adds r7, #20
8005400: 46bd mov sp, r7
8005402: f85d 7b04 ldr.w r7, [sp], #4
8005406: 4770 bx lr
08005408 <HAL_TIMEx_CommutCallback>:
* @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
8005408: b480 push {r7}
800540a: b083 sub sp, #12
800540c: af00 add r7, sp, #0
800540e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
8005410: bf00 nop
8005412: 370c adds r7, #12
8005414: 46bd mov sp, r7
8005416: f85d 7b04 ldr.w r7, [sp], #4
800541a: 4770 bx lr
0800541c <HAL_TIMEx_BreakCallback>:
* @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
800541c: b480 push {r7}
800541e: b083 sub sp, #12
8005420: af00 add r7, sp, #0
8005422: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
8005424: bf00 nop
8005426: 370c adds r7, #12
8005428: 46bd mov sp, r7
800542a: f85d 7b04 ldr.w r7, [sp], #4
800542e: 4770 bx lr
08005430 <HAL_UART_Init>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
8005430: b580 push {r7, lr}
8005432: b082 sub sp, #8
8005434: af00 add r7, sp, #0
8005436: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8005438: 687b ldr r3, [r7, #4]
800543a: 2b00 cmp r3, #0
800543c: d101 bne.n 8005442 <HAL_UART_Init+0x12>
{
return HAL_ERROR;
800543e: 2301 movs r3, #1
8005440: e042 b.n 80054c8 <HAL_UART_Init+0x98>
assert_param(IS_UART_INSTANCE(huart->Instance));
}
assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
if (huart->gState == HAL_UART_STATE_RESET)
8005442: 687b ldr r3, [r7, #4]
8005444: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8005448: b2db uxtb r3, r3
800544a: 2b00 cmp r3, #0
800544c: d106 bne.n 800545c <HAL_UART_Init+0x2c>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
800544e: 687b ldr r3, [r7, #4]
8005450: 2200 movs r2, #0
8005452: f883 2040 strb.w r2, [r3, #64] @ 0x40
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8005456: 6878 ldr r0, [r7, #4]
8005458: f7fc fb50 bl 8001afc <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
800545c: 687b ldr r3, [r7, #4]
800545e: 2224 movs r2, #36 @ 0x24
8005460: f883 2041 strb.w r2, [r3, #65] @ 0x41
/* Disable the peripheral */
__HAL_UART_DISABLE(huart);
8005464: 687b ldr r3, [r7, #4]
8005466: 681b ldr r3, [r3, #0]
8005468: 68da ldr r2, [r3, #12]
800546a: 687b ldr r3, [r7, #4]
800546c: 681b ldr r3, [r3, #0]
800546e: f422 5200 bic.w r2, r2, #8192 @ 0x2000
8005472: 60da str r2, [r3, #12]
/* Set the UART Communication parameters */
UART_SetConfig(huart);
8005474: 6878 ldr r0, [r7, #4]
8005476: f000 f82b bl 80054d0 <UART_SetConfig>
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
800547a: 687b ldr r3, [r7, #4]
800547c: 681b ldr r3, [r3, #0]
800547e: 691a ldr r2, [r3, #16]
8005480: 687b ldr r3, [r7, #4]
8005482: 681b ldr r3, [r3, #0]
8005484: f422 4290 bic.w r2, r2, #18432 @ 0x4800
8005488: 611a str r2, [r3, #16]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
800548a: 687b ldr r3, [r7, #4]
800548c: 681b ldr r3, [r3, #0]
800548e: 695a ldr r2, [r3, #20]
8005490: 687b ldr r3, [r7, #4]
8005492: 681b ldr r3, [r3, #0]
8005494: f022 022a bic.w r2, r2, #42 @ 0x2a
8005498: 615a str r2, [r3, #20]
/* Enable the peripheral */
__HAL_UART_ENABLE(huart);
800549a: 687b ldr r3, [r7, #4]
800549c: 681b ldr r3, [r3, #0]
800549e: 68da ldr r2, [r3, #12]
80054a0: 687b ldr r3, [r7, #4]
80054a2: 681b ldr r3, [r3, #0]
80054a4: f442 5200 orr.w r2, r2, #8192 @ 0x2000
80054a8: 60da str r2, [r3, #12]
/* Initialize the UART state */
huart->ErrorCode = HAL_UART_ERROR_NONE;
80054aa: 687b ldr r3, [r7, #4]
80054ac: 2200 movs r2, #0
80054ae: 645a str r2, [r3, #68] @ 0x44
huart->gState = HAL_UART_STATE_READY;
80054b0: 687b ldr r3, [r7, #4]
80054b2: 2220 movs r2, #32
80054b4: f883 2041 strb.w r2, [r3, #65] @ 0x41
huart->RxState = HAL_UART_STATE_READY;
80054b8: 687b ldr r3, [r7, #4]
80054ba: 2220 movs r2, #32
80054bc: f883 2042 strb.w r2, [r3, #66] @ 0x42
huart->RxEventType = HAL_UART_RXEVENT_TC;
80054c0: 687b ldr r3, [r7, #4]
80054c2: 2200 movs r2, #0
80054c4: 635a str r2, [r3, #52] @ 0x34
return HAL_OK;
80054c6: 2300 movs r3, #0
}
80054c8: 4618 mov r0, r3
80054ca: 3708 adds r7, #8
80054cc: 46bd mov sp, r7
80054ce: bd80 pop {r7, pc}
080054d0 <UART_SetConfig>:
* @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
static void UART_SetConfig(UART_HandleTypeDef *huart)
{
80054d0: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
80054d4: b0c0 sub sp, #256 @ 0x100
80054d6: af00 add r7, sp, #0
80054d8: f8c7 00f4 str.w r0, [r7, #244] @ 0xf4
assert_param(IS_UART_MODE(huart->Init.Mode));
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits
according to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
80054dc: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
80054e0: 681b ldr r3, [r3, #0]
80054e2: 691b ldr r3, [r3, #16]
80054e4: f423 5040 bic.w r0, r3, #12288 @ 0x3000
80054e8: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
80054ec: 68d9 ldr r1, [r3, #12]
80054ee: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
80054f2: 681a ldr r2, [r3, #0]
80054f4: ea40 0301 orr.w r3, r0, r1
80054f8: 6113 str r3, [r2, #16]
Set the M bits according to huart->Init.WordLength value
Set PCE and PS bits according to huart->Init.Parity value
Set TE and RE bits according to huart->Init.Mode value
Set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
80054fa: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
80054fe: 689a ldr r2, [r3, #8]
8005500: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005504: 691b ldr r3, [r3, #16]
8005506: 431a orrs r2, r3
8005508: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
800550c: 695b ldr r3, [r3, #20]
800550e: 431a orrs r2, r3
8005510: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005514: 69db ldr r3, [r3, #28]
8005516: 4313 orrs r3, r2
8005518: f8c7 30f8 str.w r3, [r7, #248] @ 0xf8
MODIFY_REG(huart->Instance->CR1,
800551c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005520: 681b ldr r3, [r3, #0]
8005522: 68db ldr r3, [r3, #12]
8005524: f423 4116 bic.w r1, r3, #38400 @ 0x9600
8005528: f021 010c bic.w r1, r1, #12
800552c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005530: 681a ldr r2, [r3, #0]
8005532: f8d7 30f8 ldr.w r3, [r7, #248] @ 0xf8
8005536: 430b orrs r3, r1
8005538: 60d3 str r3, [r2, #12]
(uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8),
tmpreg);
/*-------------------------- USART CR3 Configuration -----------------------*/
/* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
800553a: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
800553e: 681b ldr r3, [r3, #0]
8005540: 695b ldr r3, [r3, #20]
8005542: f423 7040 bic.w r0, r3, #768 @ 0x300
8005546: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
800554a: 6999 ldr r1, [r3, #24]
800554c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005550: 681a ldr r2, [r3, #0]
8005552: ea40 0301 orr.w r3, r0, r1
8005556: 6153 str r3, [r2, #20]
if ((huart->Instance == USART1) || (huart->Instance == USART6) || (huart->Instance == UART9) || (huart->Instance == UART10))
{
pclk = HAL_RCC_GetPCLK2Freq();
}
#elif defined(USART6)
if ((huart->Instance == USART1) || (huart->Instance == USART6))
8005558: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
800555c: 681a ldr r2, [r3, #0]
800555e: 4b8f ldr r3, [pc, #572] @ (800579c <UART_SetConfig+0x2cc>)
8005560: 429a cmp r2, r3
8005562: d005 beq.n 8005570 <UART_SetConfig+0xa0>
8005564: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005568: 681a ldr r2, [r3, #0]
800556a: 4b8d ldr r3, [pc, #564] @ (80057a0 <UART_SetConfig+0x2d0>)
800556c: 429a cmp r2, r3
800556e: d104 bne.n 800557a <UART_SetConfig+0xaa>
{
pclk = HAL_RCC_GetPCLK2Freq();
8005570: f7fe f91a bl 80037a8 <HAL_RCC_GetPCLK2Freq>
8005574: f8c7 00fc str.w r0, [r7, #252] @ 0xfc
8005578: e003 b.n 8005582 <UART_SetConfig+0xb2>
pclk = HAL_RCC_GetPCLK2Freq();
}
#endif /* USART6 */
else
{
pclk = HAL_RCC_GetPCLK1Freq();
800557a: f7fe f901 bl 8003780 <HAL_RCC_GetPCLK1Freq>
800557e: f8c7 00fc str.w r0, [r7, #252] @ 0xfc
}
/*-------------------------- USART BRR Configuration ---------------------*/
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8005582: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005586: 69db ldr r3, [r3, #28]
8005588: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
800558c: f040 810c bne.w 80057a8 <UART_SetConfig+0x2d8>
{
huart->Instance->BRR = UART_BRR_SAMPLING8(pclk, huart->Init.BaudRate);
8005590: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
8005594: 2200 movs r2, #0
8005596: f8c7 30e8 str.w r3, [r7, #232] @ 0xe8
800559a: f8c7 20ec str.w r2, [r7, #236] @ 0xec
800559e: e9d7 453a ldrd r4, r5, [r7, #232] @ 0xe8
80055a2: 4622 mov r2, r4
80055a4: 462b mov r3, r5
80055a6: 1891 adds r1, r2, r2
80055a8: 65b9 str r1, [r7, #88] @ 0x58
80055aa: 415b adcs r3, r3
80055ac: 65fb str r3, [r7, #92] @ 0x5c
80055ae: e9d7 2316 ldrd r2, r3, [r7, #88] @ 0x58
80055b2: 4621 mov r1, r4
80055b4: eb12 0801 adds.w r8, r2, r1
80055b8: 4629 mov r1, r5
80055ba: eb43 0901 adc.w r9, r3, r1
80055be: f04f 0200 mov.w r2, #0
80055c2: f04f 0300 mov.w r3, #0
80055c6: ea4f 03c9 mov.w r3, r9, lsl #3
80055ca: ea43 7358 orr.w r3, r3, r8, lsr #29
80055ce: ea4f 02c8 mov.w r2, r8, lsl #3
80055d2: 4690 mov r8, r2
80055d4: 4699 mov r9, r3
80055d6: 4623 mov r3, r4
80055d8: eb18 0303 adds.w r3, r8, r3
80055dc: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
80055e0: 462b mov r3, r5
80055e2: eb49 0303 adc.w r3, r9, r3
80055e6: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
80055ea: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
80055ee: 685b ldr r3, [r3, #4]
80055f0: 2200 movs r2, #0
80055f2: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
80055f6: f8c7 20dc str.w r2, [r7, #220] @ 0xdc
80055fa: e9d7 1236 ldrd r1, r2, [r7, #216] @ 0xd8
80055fe: 460b mov r3, r1
8005600: 18db adds r3, r3, r3
8005602: 653b str r3, [r7, #80] @ 0x50
8005604: 4613 mov r3, r2
8005606: eb42 0303 adc.w r3, r2, r3
800560a: 657b str r3, [r7, #84] @ 0x54
800560c: e9d7 2314 ldrd r2, r3, [r7, #80] @ 0x50
8005610: e9d7 0138 ldrd r0, r1, [r7, #224] @ 0xe0
8005614: f7fa fdf6 bl 8000204 <__aeabi_uldivmod>
8005618: 4602 mov r2, r0
800561a: 460b mov r3, r1
800561c: 4b61 ldr r3, [pc, #388] @ (80057a4 <UART_SetConfig+0x2d4>)
800561e: fba3 2302 umull r2, r3, r3, r2
8005622: 095b lsrs r3, r3, #5
8005624: 011c lsls r4, r3, #4
8005626: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
800562a: 2200 movs r2, #0
800562c: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
8005630: f8c7 20d4 str.w r2, [r7, #212] @ 0xd4
8005634: e9d7 8934 ldrd r8, r9, [r7, #208] @ 0xd0
8005638: 4642 mov r2, r8
800563a: 464b mov r3, r9
800563c: 1891 adds r1, r2, r2
800563e: 64b9 str r1, [r7, #72] @ 0x48
8005640: 415b adcs r3, r3
8005642: 64fb str r3, [r7, #76] @ 0x4c
8005644: e9d7 2312 ldrd r2, r3, [r7, #72] @ 0x48
8005648: 4641 mov r1, r8
800564a: eb12 0a01 adds.w sl, r2, r1
800564e: 4649 mov r1, r9
8005650: eb43 0b01 adc.w fp, r3, r1
8005654: f04f 0200 mov.w r2, #0
8005658: f04f 0300 mov.w r3, #0
800565c: ea4f 03cb mov.w r3, fp, lsl #3
8005660: ea43 735a orr.w r3, r3, sl, lsr #29
8005664: ea4f 02ca mov.w r2, sl, lsl #3
8005668: 4692 mov sl, r2
800566a: 469b mov fp, r3
800566c: 4643 mov r3, r8
800566e: eb1a 0303 adds.w r3, sl, r3
8005672: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
8005676: 464b mov r3, r9
8005678: eb4b 0303 adc.w r3, fp, r3
800567c: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
8005680: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005684: 685b ldr r3, [r3, #4]
8005686: 2200 movs r2, #0
8005688: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
800568c: f8c7 20c4 str.w r2, [r7, #196] @ 0xc4
8005690: e9d7 1230 ldrd r1, r2, [r7, #192] @ 0xc0
8005694: 460b mov r3, r1
8005696: 18db adds r3, r3, r3
8005698: 643b str r3, [r7, #64] @ 0x40
800569a: 4613 mov r3, r2
800569c: eb42 0303 adc.w r3, r2, r3
80056a0: 647b str r3, [r7, #68] @ 0x44
80056a2: e9d7 2310 ldrd r2, r3, [r7, #64] @ 0x40
80056a6: e9d7 0132 ldrd r0, r1, [r7, #200] @ 0xc8
80056aa: f7fa fdab bl 8000204 <__aeabi_uldivmod>
80056ae: 4602 mov r2, r0
80056b0: 460b mov r3, r1
80056b2: 4611 mov r1, r2
80056b4: 4b3b ldr r3, [pc, #236] @ (80057a4 <UART_SetConfig+0x2d4>)
80056b6: fba3 2301 umull r2, r3, r3, r1
80056ba: 095b lsrs r3, r3, #5
80056bc: 2264 movs r2, #100 @ 0x64
80056be: fb02 f303 mul.w r3, r2, r3
80056c2: 1acb subs r3, r1, r3
80056c4: 00db lsls r3, r3, #3
80056c6: f103 0232 add.w r2, r3, #50 @ 0x32
80056ca: 4b36 ldr r3, [pc, #216] @ (80057a4 <UART_SetConfig+0x2d4>)
80056cc: fba3 2302 umull r2, r3, r3, r2
80056d0: 095b lsrs r3, r3, #5
80056d2: 005b lsls r3, r3, #1
80056d4: f403 73f8 and.w r3, r3, #496 @ 0x1f0
80056d8: 441c add r4, r3
80056da: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
80056de: 2200 movs r2, #0
80056e0: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
80056e4: f8c7 20bc str.w r2, [r7, #188] @ 0xbc
80056e8: e9d7 892e ldrd r8, r9, [r7, #184] @ 0xb8
80056ec: 4642 mov r2, r8
80056ee: 464b mov r3, r9
80056f0: 1891 adds r1, r2, r2
80056f2: 63b9 str r1, [r7, #56] @ 0x38
80056f4: 415b adcs r3, r3
80056f6: 63fb str r3, [r7, #60] @ 0x3c
80056f8: e9d7 230e ldrd r2, r3, [r7, #56] @ 0x38
80056fc: 4641 mov r1, r8
80056fe: 1851 adds r1, r2, r1
8005700: 6339 str r1, [r7, #48] @ 0x30
8005702: 4649 mov r1, r9
8005704: 414b adcs r3, r1
8005706: 637b str r3, [r7, #52] @ 0x34
8005708: f04f 0200 mov.w r2, #0
800570c: f04f 0300 mov.w r3, #0
8005710: e9d7 ab0c ldrd sl, fp, [r7, #48] @ 0x30
8005714: 4659 mov r1, fp
8005716: 00cb lsls r3, r1, #3
8005718: 4651 mov r1, sl
800571a: ea43 7351 orr.w r3, r3, r1, lsr #29
800571e: 4651 mov r1, sl
8005720: 00ca lsls r2, r1, #3
8005722: 4610 mov r0, r2
8005724: 4619 mov r1, r3
8005726: 4603 mov r3, r0
8005728: 4642 mov r2, r8
800572a: 189b adds r3, r3, r2
800572c: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
8005730: 464b mov r3, r9
8005732: 460a mov r2, r1
8005734: eb42 0303 adc.w r3, r2, r3
8005738: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
800573c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005740: 685b ldr r3, [r3, #4]
8005742: 2200 movs r2, #0
8005744: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
8005748: f8c7 20ac str.w r2, [r7, #172] @ 0xac
800574c: e9d7 122a ldrd r1, r2, [r7, #168] @ 0xa8
8005750: 460b mov r3, r1
8005752: 18db adds r3, r3, r3
8005754: 62bb str r3, [r7, #40] @ 0x28
8005756: 4613 mov r3, r2
8005758: eb42 0303 adc.w r3, r2, r3
800575c: 62fb str r3, [r7, #44] @ 0x2c
800575e: e9d7 230a ldrd r2, r3, [r7, #40] @ 0x28
8005762: e9d7 012c ldrd r0, r1, [r7, #176] @ 0xb0
8005766: f7fa fd4d bl 8000204 <__aeabi_uldivmod>
800576a: 4602 mov r2, r0
800576c: 460b mov r3, r1
800576e: 4b0d ldr r3, [pc, #52] @ (80057a4 <UART_SetConfig+0x2d4>)
8005770: fba3 1302 umull r1, r3, r3, r2
8005774: 095b lsrs r3, r3, #5
8005776: 2164 movs r1, #100 @ 0x64
8005778: fb01 f303 mul.w r3, r1, r3
800577c: 1ad3 subs r3, r2, r3
800577e: 00db lsls r3, r3, #3
8005780: 3332 adds r3, #50 @ 0x32
8005782: 4a08 ldr r2, [pc, #32] @ (80057a4 <UART_SetConfig+0x2d4>)
8005784: fba2 2303 umull r2, r3, r2, r3
8005788: 095b lsrs r3, r3, #5
800578a: f003 0207 and.w r2, r3, #7
800578e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005792: 681b ldr r3, [r3, #0]
8005794: 4422 add r2, r4
8005796: 609a str r2, [r3, #8]
}
else
{
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
}
}
8005798: e106 b.n 80059a8 <UART_SetConfig+0x4d8>
800579a: bf00 nop
800579c: 40011000 .word 0x40011000
80057a0: 40011400 .word 0x40011400
80057a4: 51eb851f .word 0x51eb851f
huart->Instance->BRR = UART_BRR_SAMPLING16(pclk, huart->Init.BaudRate);
80057a8: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
80057ac: 2200 movs r2, #0
80057ae: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
80057b2: f8c7 20a4 str.w r2, [r7, #164] @ 0xa4
80057b6: e9d7 8928 ldrd r8, r9, [r7, #160] @ 0xa0
80057ba: 4642 mov r2, r8
80057bc: 464b mov r3, r9
80057be: 1891 adds r1, r2, r2
80057c0: 6239 str r1, [r7, #32]
80057c2: 415b adcs r3, r3
80057c4: 627b str r3, [r7, #36] @ 0x24
80057c6: e9d7 2308 ldrd r2, r3, [r7, #32]
80057ca: 4641 mov r1, r8
80057cc: 1854 adds r4, r2, r1
80057ce: 4649 mov r1, r9
80057d0: eb43 0501 adc.w r5, r3, r1
80057d4: f04f 0200 mov.w r2, #0
80057d8: f04f 0300 mov.w r3, #0
80057dc: 00eb lsls r3, r5, #3
80057de: ea43 7354 orr.w r3, r3, r4, lsr #29
80057e2: 00e2 lsls r2, r4, #3
80057e4: 4614 mov r4, r2
80057e6: 461d mov r5, r3
80057e8: 4643 mov r3, r8
80057ea: 18e3 adds r3, r4, r3
80057ec: f8c7 3098 str.w r3, [r7, #152] @ 0x98
80057f0: 464b mov r3, r9
80057f2: eb45 0303 adc.w r3, r5, r3
80057f6: f8c7 309c str.w r3, [r7, #156] @ 0x9c
80057fa: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
80057fe: 685b ldr r3, [r3, #4]
8005800: 2200 movs r2, #0
8005802: f8c7 3090 str.w r3, [r7, #144] @ 0x90
8005806: f8c7 2094 str.w r2, [r7, #148] @ 0x94
800580a: f04f 0200 mov.w r2, #0
800580e: f04f 0300 mov.w r3, #0
8005812: e9d7 4524 ldrd r4, r5, [r7, #144] @ 0x90
8005816: 4629 mov r1, r5
8005818: 008b lsls r3, r1, #2
800581a: 4621 mov r1, r4
800581c: ea43 7391 orr.w r3, r3, r1, lsr #30
8005820: 4621 mov r1, r4
8005822: 008a lsls r2, r1, #2
8005824: e9d7 0126 ldrd r0, r1, [r7, #152] @ 0x98
8005828: f7fa fcec bl 8000204 <__aeabi_uldivmod>
800582c: 4602 mov r2, r0
800582e: 460b mov r3, r1
8005830: 4b60 ldr r3, [pc, #384] @ (80059b4 <UART_SetConfig+0x4e4>)
8005832: fba3 2302 umull r2, r3, r3, r2
8005836: 095b lsrs r3, r3, #5
8005838: 011c lsls r4, r3, #4
800583a: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
800583e: 2200 movs r2, #0
8005840: f8c7 3088 str.w r3, [r7, #136] @ 0x88
8005844: f8c7 208c str.w r2, [r7, #140] @ 0x8c
8005848: e9d7 8922 ldrd r8, r9, [r7, #136] @ 0x88
800584c: 4642 mov r2, r8
800584e: 464b mov r3, r9
8005850: 1891 adds r1, r2, r2
8005852: 61b9 str r1, [r7, #24]
8005854: 415b adcs r3, r3
8005856: 61fb str r3, [r7, #28]
8005858: e9d7 2306 ldrd r2, r3, [r7, #24]
800585c: 4641 mov r1, r8
800585e: 1851 adds r1, r2, r1
8005860: 6139 str r1, [r7, #16]
8005862: 4649 mov r1, r9
8005864: 414b adcs r3, r1
8005866: 617b str r3, [r7, #20]
8005868: f04f 0200 mov.w r2, #0
800586c: f04f 0300 mov.w r3, #0
8005870: e9d7 ab04 ldrd sl, fp, [r7, #16]
8005874: 4659 mov r1, fp
8005876: 00cb lsls r3, r1, #3
8005878: 4651 mov r1, sl
800587a: ea43 7351 orr.w r3, r3, r1, lsr #29
800587e: 4651 mov r1, sl
8005880: 00ca lsls r2, r1, #3
8005882: 4610 mov r0, r2
8005884: 4619 mov r1, r3
8005886: 4603 mov r3, r0
8005888: 4642 mov r2, r8
800588a: 189b adds r3, r3, r2
800588c: f8c7 3080 str.w r3, [r7, #128] @ 0x80
8005890: 464b mov r3, r9
8005892: 460a mov r2, r1
8005894: eb42 0303 adc.w r3, r2, r3
8005898: f8c7 3084 str.w r3, [r7, #132] @ 0x84
800589c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
80058a0: 685b ldr r3, [r3, #4]
80058a2: 2200 movs r2, #0
80058a4: 67bb str r3, [r7, #120] @ 0x78
80058a6: 67fa str r2, [r7, #124] @ 0x7c
80058a8: f04f 0200 mov.w r2, #0
80058ac: f04f 0300 mov.w r3, #0
80058b0: e9d7 891e ldrd r8, r9, [r7, #120] @ 0x78
80058b4: 4649 mov r1, r9
80058b6: 008b lsls r3, r1, #2
80058b8: 4641 mov r1, r8
80058ba: ea43 7391 orr.w r3, r3, r1, lsr #30
80058be: 4641 mov r1, r8
80058c0: 008a lsls r2, r1, #2
80058c2: e9d7 0120 ldrd r0, r1, [r7, #128] @ 0x80
80058c6: f7fa fc9d bl 8000204 <__aeabi_uldivmod>
80058ca: 4602 mov r2, r0
80058cc: 460b mov r3, r1
80058ce: 4611 mov r1, r2
80058d0: 4b38 ldr r3, [pc, #224] @ (80059b4 <UART_SetConfig+0x4e4>)
80058d2: fba3 2301 umull r2, r3, r3, r1
80058d6: 095b lsrs r3, r3, #5
80058d8: 2264 movs r2, #100 @ 0x64
80058da: fb02 f303 mul.w r3, r2, r3
80058de: 1acb subs r3, r1, r3
80058e0: 011b lsls r3, r3, #4
80058e2: 3332 adds r3, #50 @ 0x32
80058e4: 4a33 ldr r2, [pc, #204] @ (80059b4 <UART_SetConfig+0x4e4>)
80058e6: fba2 2303 umull r2, r3, r2, r3
80058ea: 095b lsrs r3, r3, #5
80058ec: f003 03f0 and.w r3, r3, #240 @ 0xf0
80058f0: 441c add r4, r3
80058f2: f8d7 30fc ldr.w r3, [r7, #252] @ 0xfc
80058f6: 2200 movs r2, #0
80058f8: 673b str r3, [r7, #112] @ 0x70
80058fa: 677a str r2, [r7, #116] @ 0x74
80058fc: e9d7 891c ldrd r8, r9, [r7, #112] @ 0x70
8005900: 4642 mov r2, r8
8005902: 464b mov r3, r9
8005904: 1891 adds r1, r2, r2
8005906: 60b9 str r1, [r7, #8]
8005908: 415b adcs r3, r3
800590a: 60fb str r3, [r7, #12]
800590c: e9d7 2302 ldrd r2, r3, [r7, #8]
8005910: 4641 mov r1, r8
8005912: 1851 adds r1, r2, r1
8005914: 6039 str r1, [r7, #0]
8005916: 4649 mov r1, r9
8005918: 414b adcs r3, r1
800591a: 607b str r3, [r7, #4]
800591c: f04f 0200 mov.w r2, #0
8005920: f04f 0300 mov.w r3, #0
8005924: e9d7 ab00 ldrd sl, fp, [r7]
8005928: 4659 mov r1, fp
800592a: 00cb lsls r3, r1, #3
800592c: 4651 mov r1, sl
800592e: ea43 7351 orr.w r3, r3, r1, lsr #29
8005932: 4651 mov r1, sl
8005934: 00ca lsls r2, r1, #3
8005936: 4610 mov r0, r2
8005938: 4619 mov r1, r3
800593a: 4603 mov r3, r0
800593c: 4642 mov r2, r8
800593e: 189b adds r3, r3, r2
8005940: 66bb str r3, [r7, #104] @ 0x68
8005942: 464b mov r3, r9
8005944: 460a mov r2, r1
8005946: eb42 0303 adc.w r3, r2, r3
800594a: 66fb str r3, [r7, #108] @ 0x6c
800594c: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
8005950: 685b ldr r3, [r3, #4]
8005952: 2200 movs r2, #0
8005954: 663b str r3, [r7, #96] @ 0x60
8005956: 667a str r2, [r7, #100] @ 0x64
8005958: f04f 0200 mov.w r2, #0
800595c: f04f 0300 mov.w r3, #0
8005960: e9d7 8918 ldrd r8, r9, [r7, #96] @ 0x60
8005964: 4649 mov r1, r9
8005966: 008b lsls r3, r1, #2
8005968: 4641 mov r1, r8
800596a: ea43 7391 orr.w r3, r3, r1, lsr #30
800596e: 4641 mov r1, r8
8005970: 008a lsls r2, r1, #2
8005972: e9d7 011a ldrd r0, r1, [r7, #104] @ 0x68
8005976: f7fa fc45 bl 8000204 <__aeabi_uldivmod>
800597a: 4602 mov r2, r0
800597c: 460b mov r3, r1
800597e: 4b0d ldr r3, [pc, #52] @ (80059b4 <UART_SetConfig+0x4e4>)
8005980: fba3 1302 umull r1, r3, r3, r2
8005984: 095b lsrs r3, r3, #5
8005986: 2164 movs r1, #100 @ 0x64
8005988: fb01 f303 mul.w r3, r1, r3
800598c: 1ad3 subs r3, r2, r3
800598e: 011b lsls r3, r3, #4
8005990: 3332 adds r3, #50 @ 0x32
8005992: 4a08 ldr r2, [pc, #32] @ (80059b4 <UART_SetConfig+0x4e4>)
8005994: fba2 2303 umull r2, r3, r2, r3
8005998: 095b lsrs r3, r3, #5
800599a: f003 020f and.w r2, r3, #15
800599e: f8d7 30f4 ldr.w r3, [r7, #244] @ 0xf4
80059a2: 681b ldr r3, [r3, #0]
80059a4: 4422 add r2, r4
80059a6: 609a str r2, [r3, #8]
}
80059a8: bf00 nop
80059aa: f507 7780 add.w r7, r7, #256 @ 0x100
80059ae: 46bd mov sp, r7
80059b0: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
80059b4: 51eb851f .word 0x51eb851f
080059b8 <memset>:
80059b8: 4402 add r2, r0
80059ba: 4603 mov r3, r0
80059bc: 4293 cmp r3, r2
80059be: d100 bne.n 80059c2 <memset+0xa>
80059c0: 4770 bx lr
80059c2: f803 1b01 strb.w r1, [r3], #1
80059c6: e7f9 b.n 80059bc <memset+0x4>
080059c8 <__libc_init_array>:
80059c8: b570 push {r4, r5, r6, lr}
80059ca: 4d0d ldr r5, [pc, #52] @ (8005a00 <__libc_init_array+0x38>)
80059cc: 4c0d ldr r4, [pc, #52] @ (8005a04 <__libc_init_array+0x3c>)
80059ce: 1b64 subs r4, r4, r5
80059d0: 10a4 asrs r4, r4, #2
80059d2: 2600 movs r6, #0
80059d4: 42a6 cmp r6, r4
80059d6: d109 bne.n 80059ec <__libc_init_array+0x24>
80059d8: 4d0b ldr r5, [pc, #44] @ (8005a08 <__libc_init_array+0x40>)
80059da: 4c0c ldr r4, [pc, #48] @ (8005a0c <__libc_init_array+0x44>)
80059dc: f000 f826 bl 8005a2c <_init>
80059e0: 1b64 subs r4, r4, r5
80059e2: 10a4 asrs r4, r4, #2
80059e4: 2600 movs r6, #0
80059e6: 42a6 cmp r6, r4
80059e8: d105 bne.n 80059f6 <__libc_init_array+0x2e>
80059ea: bd70 pop {r4, r5, r6, pc}
80059ec: f855 3b04 ldr.w r3, [r5], #4
80059f0: 4798 blx r3
80059f2: 3601 adds r6, #1
80059f4: e7ee b.n 80059d4 <__libc_init_array+0xc>
80059f6: f855 3b04 ldr.w r3, [r5], #4
80059fa: 4798 blx r3
80059fc: 3601 adds r6, #1
80059fe: e7f2 b.n 80059e6 <__libc_init_array+0x1e>
8005a00: 08005a64 .word 0x08005a64
8005a04: 08005a64 .word 0x08005a64
8005a08: 08005a64 .word 0x08005a64
8005a0c: 08005a68 .word 0x08005a68
08005a10 <memcpy>:
8005a10: 440a add r2, r1
8005a12: 4291 cmp r1, r2
8005a14: f100 33ff add.w r3, r0, #4294967295
8005a18: d100 bne.n 8005a1c <memcpy+0xc>
8005a1a: 4770 bx lr
8005a1c: b510 push {r4, lr}
8005a1e: f811 4b01 ldrb.w r4, [r1], #1
8005a22: f803 4f01 strb.w r4, [r3, #1]!
8005a26: 4291 cmp r1, r2
8005a28: d1f9 bne.n 8005a1e <memcpy+0xe>
8005a2a: bd10 pop {r4, pc}
08005a2c <_init>:
8005a2c: b5f8 push {r3, r4, r5, r6, r7, lr}
8005a2e: bf00 nop
8005a30: bcf8 pop {r3, r4, r5, r6, r7}
8005a32: bc08 pop {r3}
8005a34: 469e mov lr, r3
8005a36: 4770 bx lr
08005a38 <_fini>:
8005a38: b5f8 push {r3, r4, r5, r6, r7, lr}
8005a3a: bf00 nop
8005a3c: bcf8 pop {r3, r4, r5, r6, r7}
8005a3e: bc08 pop {r3}
8005a40: 469e mov lr, r3
8005a42: 4770 bx lr
Reference in a new issue View git blame Copy permalink